meson_drv.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. * Copyright (C) 2014 Endless Mobile
  6. *
  7. * Written by:
  8. * Jasper St. Pierre <jstpierre@mecheye.net>
  9. */
  10. #include <linux/component.h>
  11. #include <linux/module.h>
  12. #include <linux/of_graph.h>
  13. #include <linux/sys_soc.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/soc/amlogic/meson-canvas.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_drv.h>
  18. #include <drm/drm_fb_helper.h>
  19. #include <drm/drm_gem_cma_helper.h>
  20. #include <drm/drm_gem_framebuffer_helper.h>
  21. #include <drm/drm_irq.h>
  22. #include <drm/drm_modeset_helper_vtables.h>
  23. #include <drm/drm_probe_helper.h>
  24. #include <drm/drm_vblank.h>
  25. #include "meson_crtc.h"
  26. #include "meson_drv.h"
  27. #include "meson_overlay.h"
  28. #include "meson_plane.h"
  29. #include "meson_osd_afbcd.h"
  30. #include "meson_registers.h"
  31. #include "meson_venc_cvbs.h"
  32. #include "meson_viu.h"
  33. #include "meson_vpp.h"
  34. #include "meson_rdma.h"
  35. #define DRIVER_NAME "meson"
  36. #define DRIVER_DESC "Amlogic Meson DRM driver"
  37. /**
  38. * DOC: Video Processing Unit
  39. *
  40. * VPU Handles the Global Video Processing, it includes management of the
  41. * clocks gates, blocks reset lines and power domains.
  42. *
  43. * What is missing :
  44. *
  45. * - Full reset of entire video processing HW blocks
  46. * - Scaling and setup of the VPU clock
  47. * - Bus clock gates
  48. * - Powering up video processing HW blocks
  49. * - Powering Up HDMI controller and PHY
  50. */
  51. static const struct drm_mode_config_funcs meson_mode_config_funcs = {
  52. .atomic_check = drm_atomic_helper_check,
  53. .atomic_commit = drm_atomic_helper_commit,
  54. .fb_create = drm_gem_fb_create,
  55. };
  56. static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
  57. .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
  58. };
  59. static irqreturn_t meson_irq(int irq, void *arg)
  60. {
  61. struct drm_device *dev = arg;
  62. struct meson_drm *priv = dev->dev_private;
  63. (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
  64. meson_crtc_irq(priv);
  65. return IRQ_HANDLED;
  66. }
  67. static int meson_dumb_create(struct drm_file *file, struct drm_device *dev,
  68. struct drm_mode_create_dumb *args)
  69. {
  70. /*
  71. * We need 64bytes aligned stride, and PAGE aligned size
  72. */
  73. args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
  74. args->size = PAGE_ALIGN(args->pitch * args->height);
  75. return drm_gem_cma_dumb_create_internal(file, dev, args);
  76. }
  77. DEFINE_DRM_GEM_CMA_FOPS(fops);
  78. static struct drm_driver meson_driver = {
  79. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
  80. /* IRQ */
  81. .irq_handler = meson_irq,
  82. /* CMA Ops */
  83. DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create),
  84. /* Misc */
  85. .fops = &fops,
  86. .name = DRIVER_NAME,
  87. .desc = DRIVER_DESC,
  88. .date = "20161109",
  89. .major = 1,
  90. .minor = 0,
  91. };
  92. static bool meson_vpu_has_available_connectors(struct device *dev)
  93. {
  94. struct device_node *ep, *remote;
  95. /* Parses each endpoint and check if remote exists */
  96. for_each_endpoint_of_node(dev->of_node, ep) {
  97. /* If the endpoint node exists, consider it enabled */
  98. remote = of_graph_get_remote_port(ep);
  99. if (remote)
  100. return true;
  101. }
  102. return false;
  103. }
  104. static struct regmap_config meson_regmap_config = {
  105. .reg_bits = 32,
  106. .val_bits = 32,
  107. .reg_stride = 4,
  108. .max_register = 0x1000,
  109. };
  110. static void meson_vpu_init(struct meson_drm *priv)
  111. {
  112. u32 value;
  113. /*
  114. * Slave dc0 and dc5 connected to master port 1.
  115. * By default other slaves are connected to master port 0.
  116. */
  117. value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
  118. VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
  119. writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
  120. /* Slave dc0 connected to master port 1 */
  121. value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
  122. writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
  123. /* Slave dc4 and dc7 connected to master port 1 */
  124. value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
  125. VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
  126. writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
  127. /* Slave dc1 connected to master port 1 */
  128. value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
  129. writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
  130. }
  131. static void meson_remove_framebuffers(void)
  132. {
  133. struct apertures_struct *ap;
  134. ap = alloc_apertures(1);
  135. if (!ap)
  136. return;
  137. /* The framebuffer can be located anywhere in RAM */
  138. ap->ranges[0].base = 0;
  139. ap->ranges[0].size = ~0;
  140. drm_fb_helper_remove_conflicting_framebuffers(ap, "meson-drm-fb",
  141. false);
  142. kfree(ap);
  143. }
  144. struct meson_drm_soc_attr {
  145. struct meson_drm_soc_limits limits;
  146. const struct soc_device_attribute *attrs;
  147. };
  148. static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = {
  149. /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */
  150. {
  151. .limits = {
  152. .max_hdmi_phy_freq = 1650000,
  153. },
  154. .attrs = (const struct soc_device_attribute []) {
  155. { .soc_id = "GXL (S805*)", },
  156. { /* sentinel */ },
  157. }
  158. },
  159. };
  160. static int meson_drv_bind_master(struct device *dev, bool has_components)
  161. {
  162. struct platform_device *pdev = to_platform_device(dev);
  163. const struct meson_drm_match_data *match;
  164. struct meson_drm *priv;
  165. struct drm_device *drm;
  166. struct resource *res;
  167. void __iomem *regs;
  168. int ret, i;
  169. /* Checks if an output connector is available */
  170. if (!meson_vpu_has_available_connectors(dev)) {
  171. dev_err(dev, "No output connector available\n");
  172. return -ENODEV;
  173. }
  174. match = of_device_get_match_data(dev);
  175. if (!match)
  176. return -ENODEV;
  177. drm = drm_dev_alloc(&meson_driver, dev);
  178. if (IS_ERR(drm))
  179. return PTR_ERR(drm);
  180. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  181. if (!priv) {
  182. ret = -ENOMEM;
  183. goto free_drm;
  184. }
  185. drm->dev_private = priv;
  186. priv->drm = drm;
  187. priv->dev = dev;
  188. priv->compat = match->compat;
  189. priv->afbcd.ops = match->afbcd_ops;
  190. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu");
  191. regs = devm_ioremap_resource(dev, res);
  192. if (IS_ERR(regs)) {
  193. ret = PTR_ERR(regs);
  194. goto free_drm;
  195. }
  196. priv->io_base = regs;
  197. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
  198. if (!res) {
  199. ret = -EINVAL;
  200. goto free_drm;
  201. }
  202. /* Simply ioremap since it may be a shared register zone */
  203. regs = devm_ioremap(dev, res->start, resource_size(res));
  204. if (!regs) {
  205. ret = -EADDRNOTAVAIL;
  206. goto free_drm;
  207. }
  208. priv->hhi = devm_regmap_init_mmio(dev, regs,
  209. &meson_regmap_config);
  210. if (IS_ERR(priv->hhi)) {
  211. dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
  212. ret = PTR_ERR(priv->hhi);
  213. goto free_drm;
  214. }
  215. priv->canvas = meson_canvas_get(dev);
  216. if (IS_ERR(priv->canvas)) {
  217. ret = PTR_ERR(priv->canvas);
  218. goto free_drm;
  219. }
  220. ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
  221. if (ret)
  222. goto free_drm;
  223. ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
  224. if (ret) {
  225. meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
  226. goto free_drm;
  227. }
  228. ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
  229. if (ret) {
  230. meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
  231. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
  232. goto free_drm;
  233. }
  234. ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
  235. if (ret) {
  236. meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
  237. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
  238. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
  239. goto free_drm;
  240. }
  241. priv->vsync_irq = platform_get_irq(pdev, 0);
  242. ret = drm_vblank_init(drm, 1);
  243. if (ret)
  244. goto free_drm;
  245. /* Assign limits per soc revision/package */
  246. for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) {
  247. if (soc_device_match(meson_drm_soc_attrs[i].attrs)) {
  248. priv->limits = &meson_drm_soc_attrs[i].limits;
  249. break;
  250. }
  251. }
  252. /* Remove early framebuffers (ie. simplefb) */
  253. meson_remove_framebuffers();
  254. ret = drmm_mode_config_init(drm);
  255. if (ret)
  256. goto free_drm;
  257. drm->mode_config.max_width = 3840;
  258. drm->mode_config.max_height = 2160;
  259. drm->mode_config.funcs = &meson_mode_config_funcs;
  260. drm->mode_config.helper_private = &meson_mode_config_helpers;
  261. /* Hardware Initialization */
  262. meson_vpu_init(priv);
  263. meson_venc_init(priv);
  264. meson_vpp_init(priv);
  265. meson_viu_init(priv);
  266. if (priv->afbcd.ops) {
  267. ret = priv->afbcd.ops->init(priv);
  268. if (ret)
  269. return ret;
  270. }
  271. /* Encoder Initialization */
  272. ret = meson_venc_cvbs_create(priv);
  273. if (ret)
  274. goto free_drm;
  275. if (has_components) {
  276. ret = component_bind_all(drm->dev, drm);
  277. if (ret) {
  278. dev_err(drm->dev, "Couldn't bind all components\n");
  279. goto free_drm;
  280. }
  281. }
  282. ret = meson_plane_create(priv);
  283. if (ret)
  284. goto free_drm;
  285. ret = meson_overlay_create(priv);
  286. if (ret)
  287. goto free_drm;
  288. ret = meson_crtc_create(priv);
  289. if (ret)
  290. goto free_drm;
  291. ret = drm_irq_install(drm, priv->vsync_irq);
  292. if (ret)
  293. goto free_drm;
  294. drm_mode_config_reset(drm);
  295. drm_kms_helper_poll_init(drm);
  296. platform_set_drvdata(pdev, priv);
  297. ret = drm_dev_register(drm, 0);
  298. if (ret)
  299. goto uninstall_irq;
  300. drm_fbdev_generic_setup(drm, 32);
  301. return 0;
  302. uninstall_irq:
  303. drm_irq_uninstall(drm);
  304. free_drm:
  305. drm_dev_put(drm);
  306. return ret;
  307. }
  308. static int meson_drv_bind(struct device *dev)
  309. {
  310. return meson_drv_bind_master(dev, true);
  311. }
  312. static void meson_drv_unbind(struct device *dev)
  313. {
  314. struct meson_drm *priv = dev_get_drvdata(dev);
  315. struct drm_device *drm = priv->drm;
  316. if (priv->canvas) {
  317. meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
  318. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
  319. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
  320. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
  321. }
  322. drm_dev_unregister(drm);
  323. drm_kms_helper_poll_fini(drm);
  324. drm_atomic_helper_shutdown(drm);
  325. component_unbind_all(dev, drm);
  326. drm_irq_uninstall(drm);
  327. drm_dev_put(drm);
  328. if (priv->afbcd.ops)
  329. priv->afbcd.ops->exit(priv);
  330. }
  331. static const struct component_master_ops meson_drv_master_ops = {
  332. .bind = meson_drv_bind,
  333. .unbind = meson_drv_unbind,
  334. };
  335. static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
  336. {
  337. struct meson_drm *priv = dev_get_drvdata(dev);
  338. if (!priv)
  339. return 0;
  340. return drm_mode_config_helper_suspend(priv->drm);
  341. }
  342. static int __maybe_unused meson_drv_pm_resume(struct device *dev)
  343. {
  344. struct meson_drm *priv = dev_get_drvdata(dev);
  345. if (!priv)
  346. return 0;
  347. meson_vpu_init(priv);
  348. meson_venc_init(priv);
  349. meson_vpp_init(priv);
  350. meson_viu_init(priv);
  351. if (priv->afbcd.ops)
  352. priv->afbcd.ops->init(priv);
  353. return drm_mode_config_helper_resume(priv->drm);
  354. }
  355. static int compare_of(struct device *dev, void *data)
  356. {
  357. DRM_DEBUG_DRIVER("Comparing of node %pOF with %pOF\n",
  358. dev->of_node, data);
  359. return dev->of_node == data;
  360. }
  361. /* Possible connectors nodes to ignore */
  362. static const struct of_device_id connectors_match[] = {
  363. { .compatible = "composite-video-connector" },
  364. { .compatible = "svideo-connector" },
  365. { .compatible = "hdmi-connector" },
  366. { .compatible = "dvi-connector" },
  367. {}
  368. };
  369. static int meson_probe_remote(struct platform_device *pdev,
  370. struct component_match **match,
  371. struct device_node *parent,
  372. struct device_node *remote)
  373. {
  374. struct device_node *ep, *remote_node;
  375. int count = 1;
  376. /* If node is a connector, return and do not add to match table */
  377. if (of_match_node(connectors_match, remote))
  378. return 1;
  379. component_match_add(&pdev->dev, match, compare_of, remote);
  380. for_each_endpoint_of_node(remote, ep) {
  381. remote_node = of_graph_get_remote_port_parent(ep);
  382. if (!remote_node ||
  383. remote_node == parent || /* Ignore parent endpoint */
  384. !of_device_is_available(remote_node)) {
  385. of_node_put(remote_node);
  386. continue;
  387. }
  388. count += meson_probe_remote(pdev, match, remote, remote_node);
  389. of_node_put(remote_node);
  390. }
  391. return count;
  392. }
  393. static void meson_drv_shutdown(struct platform_device *pdev)
  394. {
  395. struct meson_drm *priv = dev_get_drvdata(&pdev->dev);
  396. if (!priv)
  397. return;
  398. drm_kms_helper_poll_fini(priv->drm);
  399. drm_atomic_helper_shutdown(priv->drm);
  400. }
  401. static int meson_drv_probe(struct platform_device *pdev)
  402. {
  403. struct component_match *match = NULL;
  404. struct device_node *np = pdev->dev.of_node;
  405. struct device_node *ep, *remote;
  406. int count = 0;
  407. for_each_endpoint_of_node(np, ep) {
  408. remote = of_graph_get_remote_port_parent(ep);
  409. if (!remote || !of_device_is_available(remote)) {
  410. of_node_put(remote);
  411. continue;
  412. }
  413. count += meson_probe_remote(pdev, &match, np, remote);
  414. of_node_put(remote);
  415. }
  416. if (count && !match)
  417. return meson_drv_bind_master(&pdev->dev, false);
  418. /* If some endpoints were found, initialize the nodes */
  419. if (count) {
  420. dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
  421. return component_master_add_with_match(&pdev->dev,
  422. &meson_drv_master_ops,
  423. match);
  424. }
  425. /* If no output endpoints were available, simply bail out */
  426. return 0;
  427. };
  428. static struct meson_drm_match_data meson_drm_gxbb_data = {
  429. .compat = VPU_COMPATIBLE_GXBB,
  430. };
  431. static struct meson_drm_match_data meson_drm_gxl_data = {
  432. .compat = VPU_COMPATIBLE_GXL,
  433. };
  434. static struct meson_drm_match_data meson_drm_gxm_data = {
  435. .compat = VPU_COMPATIBLE_GXM,
  436. .afbcd_ops = &meson_afbcd_gxm_ops,
  437. };
  438. static struct meson_drm_match_data meson_drm_g12a_data = {
  439. .compat = VPU_COMPATIBLE_G12A,
  440. .afbcd_ops = &meson_afbcd_g12a_ops,
  441. };
  442. static const struct of_device_id dt_match[] = {
  443. { .compatible = "amlogic,meson-gxbb-vpu",
  444. .data = (void *)&meson_drm_gxbb_data },
  445. { .compatible = "amlogic,meson-gxl-vpu",
  446. .data = (void *)&meson_drm_gxl_data },
  447. { .compatible = "amlogic,meson-gxm-vpu",
  448. .data = (void *)&meson_drm_gxm_data },
  449. { .compatible = "amlogic,meson-g12a-vpu",
  450. .data = (void *)&meson_drm_g12a_data },
  451. {}
  452. };
  453. MODULE_DEVICE_TABLE(of, dt_match);
  454. static const struct dev_pm_ops meson_drv_pm_ops = {
  455. SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
  456. };
  457. static struct platform_driver meson_drm_platform_driver = {
  458. .probe = meson_drv_probe,
  459. .shutdown = meson_drv_shutdown,
  460. .driver = {
  461. .name = "meson-drm",
  462. .of_match_table = dt_match,
  463. .pm = &meson_drv_pm_ops,
  464. },
  465. };
  466. module_platform_driver(meson_drm_platform_driver);
  467. MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
  468. MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
  469. MODULE_DESCRIPTION(DRIVER_DESC);
  470. MODULE_LICENSE("GPL");