meson_crtc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
  6. * Copyright (C) 2014 Endless Mobile
  7. *
  8. * Written by:
  9. * Jasper St. Pierre <jstpierre@mecheye.net>
  10. */
  11. #include <linux/bitfield.h>
  12. #include <linux/soc/amlogic/meson-canvas.h>
  13. #include <drm/drm_atomic_helper.h>
  14. #include <drm/drm_device.h>
  15. #include <drm/drm_print.h>
  16. #include <drm/drm_probe_helper.h>
  17. #include <drm/drm_vblank.h>
  18. #include "meson_crtc.h"
  19. #include "meson_plane.h"
  20. #include "meson_registers.h"
  21. #include "meson_venc.h"
  22. #include "meson_viu.h"
  23. #include "meson_rdma.h"
  24. #include "meson_vpp.h"
  25. #include "meson_osd_afbcd.h"
  26. #define MESON_G12A_VIU_OFFSET 0x5ec0
  27. /* CRTC definition */
  28. struct meson_crtc {
  29. struct drm_crtc base;
  30. struct drm_pending_vblank_event *event;
  31. struct meson_drm *priv;
  32. void (*enable_osd1)(struct meson_drm *priv);
  33. void (*enable_vd1)(struct meson_drm *priv);
  34. void (*enable_osd1_afbc)(struct meson_drm *priv);
  35. void (*disable_osd1_afbc)(struct meson_drm *priv);
  36. unsigned int viu_offset;
  37. bool vsync_forced;
  38. bool vsync_disabled;
  39. };
  40. #define to_meson_crtc(x) container_of(x, struct meson_crtc, base)
  41. /* CRTC */
  42. static int meson_crtc_enable_vblank(struct drm_crtc *crtc)
  43. {
  44. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  45. struct meson_drm *priv = meson_crtc->priv;
  46. meson_crtc->vsync_disabled = false;
  47. meson_venc_enable_vsync(priv);
  48. return 0;
  49. }
  50. static void meson_crtc_disable_vblank(struct drm_crtc *crtc)
  51. {
  52. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  53. struct meson_drm *priv = meson_crtc->priv;
  54. if (!meson_crtc->vsync_forced) {
  55. meson_crtc->vsync_disabled = true;
  56. meson_venc_disable_vsync(priv);
  57. }
  58. }
  59. static const struct drm_crtc_funcs meson_crtc_funcs = {
  60. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  61. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  62. .destroy = drm_crtc_cleanup,
  63. .page_flip = drm_atomic_helper_page_flip,
  64. .reset = drm_atomic_helper_crtc_reset,
  65. .set_config = drm_atomic_helper_set_config,
  66. .enable_vblank = meson_crtc_enable_vblank,
  67. .disable_vblank = meson_crtc_disable_vblank,
  68. };
  69. static void meson_g12a_crtc_atomic_enable(struct drm_crtc *crtc,
  70. struct drm_crtc_state *old_state)
  71. {
  72. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  73. struct drm_crtc_state *crtc_state = crtc->state;
  74. struct meson_drm *priv = meson_crtc->priv;
  75. DRM_DEBUG_DRIVER("\n");
  76. if (!crtc_state) {
  77. DRM_ERROR("Invalid crtc_state\n");
  78. return;
  79. }
  80. /* VD1 Preblend vertical start/end */
  81. writel(FIELD_PREP(GENMASK(11, 0), 2303),
  82. priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
  83. /* Setup Blender */
  84. writel(crtc_state->mode.hdisplay |
  85. crtc_state->mode.vdisplay << 16,
  86. priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
  87. writel_relaxed(0 << 16 |
  88. (crtc_state->mode.hdisplay - 1),
  89. priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE));
  90. writel_relaxed(0 << 16 |
  91. (crtc_state->mode.vdisplay - 1),
  92. priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE));
  93. writel_relaxed(crtc_state->mode.hdisplay << 16 |
  94. crtc_state->mode.vdisplay,
  95. priv->io_base + _REG(VPP_OUT_H_V_SIZE));
  96. drm_crtc_vblank_on(crtc);
  97. }
  98. static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
  99. struct drm_crtc_state *old_state)
  100. {
  101. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  102. struct drm_crtc_state *crtc_state = crtc->state;
  103. struct meson_drm *priv = meson_crtc->priv;
  104. DRM_DEBUG_DRIVER("\n");
  105. if (!crtc_state) {
  106. DRM_ERROR("Invalid crtc_state\n");
  107. return;
  108. }
  109. /* Enable VPP Postblend */
  110. writel(crtc_state->mode.hdisplay,
  111. priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
  112. /* VD1 Preblend vertical start/end */
  113. writel(FIELD_PREP(GENMASK(11, 0), 2303),
  114. priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
  115. writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
  116. priv->io_base + _REG(VPP_MISC));
  117. drm_crtc_vblank_on(crtc);
  118. }
  119. static void meson_g12a_crtc_atomic_disable(struct drm_crtc *crtc,
  120. struct drm_crtc_state *old_state)
  121. {
  122. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  123. struct meson_drm *priv = meson_crtc->priv;
  124. DRM_DEBUG_DRIVER("\n");
  125. drm_crtc_vblank_off(crtc);
  126. priv->viu.osd1_enabled = false;
  127. priv->viu.osd1_commit = false;
  128. priv->viu.vd1_enabled = false;
  129. priv->viu.vd1_commit = false;
  130. if (crtc->state->event && !crtc->state->active) {
  131. spin_lock_irq(&crtc->dev->event_lock);
  132. drm_crtc_send_vblank_event(crtc, crtc->state->event);
  133. spin_unlock_irq(&crtc->dev->event_lock);
  134. crtc->state->event = NULL;
  135. }
  136. }
  137. static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
  138. struct drm_crtc_state *old_state)
  139. {
  140. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  141. struct meson_drm *priv = meson_crtc->priv;
  142. DRM_DEBUG_DRIVER("\n");
  143. drm_crtc_vblank_off(crtc);
  144. priv->viu.osd1_enabled = false;
  145. priv->viu.osd1_commit = false;
  146. priv->viu.vd1_enabled = false;
  147. priv->viu.vd1_commit = false;
  148. /* Disable VPP Postblend */
  149. writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND |
  150. VPP_VD1_PREBLEND | VPP_POSTBLEND_ENABLE, 0,
  151. priv->io_base + _REG(VPP_MISC));
  152. if (crtc->state->event && !crtc->state->active) {
  153. spin_lock_irq(&crtc->dev->event_lock);
  154. drm_crtc_send_vblank_event(crtc, crtc->state->event);
  155. spin_unlock_irq(&crtc->dev->event_lock);
  156. crtc->state->event = NULL;
  157. }
  158. }
  159. static void meson_crtc_atomic_begin(struct drm_crtc *crtc,
  160. struct drm_crtc_state *state)
  161. {
  162. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  163. unsigned long flags;
  164. if (crtc->state->event) {
  165. WARN_ON(drm_crtc_vblank_get(crtc) != 0);
  166. spin_lock_irqsave(&crtc->dev->event_lock, flags);
  167. meson_crtc->event = crtc->state->event;
  168. spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  169. crtc->state->event = NULL;
  170. }
  171. }
  172. static void meson_crtc_atomic_flush(struct drm_crtc *crtc,
  173. struct drm_crtc_state *old_crtc_state)
  174. {
  175. struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  176. struct meson_drm *priv = meson_crtc->priv;
  177. priv->viu.osd1_commit = true;
  178. priv->viu.vd1_commit = true;
  179. }
  180. static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
  181. .atomic_begin = meson_crtc_atomic_begin,
  182. .atomic_flush = meson_crtc_atomic_flush,
  183. .atomic_enable = meson_crtc_atomic_enable,
  184. .atomic_disable = meson_crtc_atomic_disable,
  185. };
  186. static const struct drm_crtc_helper_funcs meson_g12a_crtc_helper_funcs = {
  187. .atomic_begin = meson_crtc_atomic_begin,
  188. .atomic_flush = meson_crtc_atomic_flush,
  189. .atomic_enable = meson_g12a_crtc_atomic_enable,
  190. .atomic_disable = meson_g12a_crtc_atomic_disable,
  191. };
  192. static void meson_crtc_enable_osd1(struct meson_drm *priv)
  193. {
  194. writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
  195. priv->io_base + _REG(VPP_MISC));
  196. }
  197. static void meson_crtc_g12a_enable_osd1_afbc(struct meson_drm *priv)
  198. {
  199. writel_relaxed(priv->viu.osd1_blk2_cfg4,
  200. priv->io_base + _REG(VIU_OSD1_BLK2_CFG_W4));
  201. writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR,
  202. priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
  203. writel_relaxed(priv->viu.osd1_blk1_cfg4,
  204. priv->io_base + _REG(VIU_OSD1_BLK1_CFG_W4));
  205. meson_viu_g12a_enable_osd1_afbc(priv);
  206. writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR,
  207. priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
  208. writel_bits_relaxed(OSD_MALI_SRC_EN, OSD_MALI_SRC_EN,
  209. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
  210. }
  211. static void meson_g12a_crtc_enable_osd1(struct meson_drm *priv)
  212. {
  213. writel_relaxed(priv->viu.osd_blend_din0_scope_h,
  214. priv->io_base +
  215. _REG(VIU_OSD_BLEND_DIN0_SCOPE_H));
  216. writel_relaxed(priv->viu.osd_blend_din0_scope_v,
  217. priv->io_base +
  218. _REG(VIU_OSD_BLEND_DIN0_SCOPE_V));
  219. writel_relaxed(priv->viu.osb_blend0_size,
  220. priv->io_base +
  221. _REG(VIU_OSD_BLEND_BLEND0_SIZE));
  222. writel_relaxed(priv->viu.osb_blend1_size,
  223. priv->io_base +
  224. _REG(VIU_OSD_BLEND_BLEND1_SIZE));
  225. writel_bits_relaxed(3 << 8, 3 << 8,
  226. priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
  227. }
  228. static void meson_crtc_enable_vd1(struct meson_drm *priv)
  229. {
  230. writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
  231. VPP_COLOR_MNG_ENABLE,
  232. VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
  233. VPP_COLOR_MNG_ENABLE,
  234. priv->io_base + _REG(VPP_MISC));
  235. writel_bits_relaxed(VIU_CTRL0_AFBC_TO_VD1,
  236. priv->viu.vd1_afbc ? VIU_CTRL0_AFBC_TO_VD1 : 0,
  237. priv->io_base + _REG(VIU_MISC_CTRL0));
  238. }
  239. static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv)
  240. {
  241. writel_relaxed(VD_BLEND_PREBLD_SRC_VD1 |
  242. VD_BLEND_PREBLD_PREMULT_EN |
  243. VD_BLEND_POSTBLD_SRC_VD1 |
  244. VD_BLEND_POSTBLD_PREMULT_EN,
  245. priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
  246. writel_relaxed(priv->viu.vd1_afbc ?
  247. (VD1_AXI_SEL_AFBC | AFBC_VD1_SEL) : 0,
  248. priv->io_base + _REG(VD1_AFBCD0_MISC_CTRL));
  249. }
  250. void meson_crtc_irq(struct meson_drm *priv)
  251. {
  252. struct meson_crtc *meson_crtc = to_meson_crtc(priv->crtc);
  253. unsigned long flags;
  254. /* Update the OSD registers */
  255. if (priv->viu.osd1_enabled && priv->viu.osd1_commit) {
  256. writel_relaxed(priv->viu.osd1_ctrl_stat,
  257. priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
  258. writel_relaxed(priv->viu.osd1_ctrl_stat2,
  259. priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
  260. writel_relaxed(priv->viu.osd1_blk0_cfg[0],
  261. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
  262. writel_relaxed(priv->viu.osd1_blk0_cfg[1],
  263. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
  264. writel_relaxed(priv->viu.osd1_blk0_cfg[2],
  265. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
  266. writel_relaxed(priv->viu.osd1_blk0_cfg[3],
  267. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
  268. writel_relaxed(priv->viu.osd1_blk0_cfg[4],
  269. priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
  270. if (priv->viu.osd1_afbcd) {
  271. if (meson_crtc->enable_osd1_afbc)
  272. meson_crtc->enable_osd1_afbc(priv);
  273. } else {
  274. if (meson_crtc->disable_osd1_afbc)
  275. meson_crtc->disable_osd1_afbc(priv);
  276. if (priv->afbcd.ops) {
  277. priv->afbcd.ops->reset(priv);
  278. priv->afbcd.ops->disable(priv);
  279. }
  280. meson_crtc->vsync_forced = false;
  281. }
  282. writel_relaxed(priv->viu.osd_sc_ctrl0,
  283. priv->io_base + _REG(VPP_OSD_SC_CTRL0));
  284. writel_relaxed(priv->viu.osd_sc_i_wh_m1,
  285. priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
  286. writel_relaxed(priv->viu.osd_sc_o_h_start_end,
  287. priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
  288. writel_relaxed(priv->viu.osd_sc_o_v_start_end,
  289. priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
  290. writel_relaxed(priv->viu.osd_sc_v_ini_phase,
  291. priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
  292. writel_relaxed(priv->viu.osd_sc_v_phase_step,
  293. priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
  294. writel_relaxed(priv->viu.osd_sc_h_ini_phase,
  295. priv->io_base + _REG(VPP_OSD_HSC_INI_PHASE));
  296. writel_relaxed(priv->viu.osd_sc_h_phase_step,
  297. priv->io_base + _REG(VPP_OSD_HSC_PHASE_STEP));
  298. writel_relaxed(priv->viu.osd_sc_h_ctrl0,
  299. priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
  300. writel_relaxed(priv->viu.osd_sc_v_ctrl0,
  301. priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
  302. if (!priv->viu.osd1_afbcd)
  303. meson_canvas_config(priv->canvas, priv->canvas_id_osd1,
  304. priv->viu.osd1_addr,
  305. priv->viu.osd1_stride,
  306. priv->viu.osd1_height,
  307. MESON_CANVAS_WRAP_NONE,
  308. MESON_CANVAS_BLKMODE_LINEAR, 0);
  309. /* Enable OSD1 */
  310. if (meson_crtc->enable_osd1)
  311. meson_crtc->enable_osd1(priv);
  312. if (priv->viu.osd1_afbcd) {
  313. priv->afbcd.ops->reset(priv);
  314. priv->afbcd.ops->setup(priv);
  315. priv->afbcd.ops->enable(priv);
  316. meson_crtc->vsync_forced = true;
  317. }
  318. priv->viu.osd1_commit = false;
  319. }
  320. /* Update the VD1 registers */
  321. if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {
  322. if (priv->viu.vd1_afbc) {
  323. writel_relaxed(priv->viu.vd1_afbc_head_addr,
  324. priv->io_base +
  325. _REG(AFBC_HEAD_BADDR));
  326. writel_relaxed(priv->viu.vd1_afbc_body_addr,
  327. priv->io_base +
  328. _REG(AFBC_BODY_BADDR));
  329. writel_relaxed(priv->viu.vd1_afbc_en,
  330. priv->io_base +
  331. _REG(AFBC_ENABLE));
  332. writel_relaxed(priv->viu.vd1_afbc_mode,
  333. priv->io_base +
  334. _REG(AFBC_MODE));
  335. writel_relaxed(priv->viu.vd1_afbc_size_in,
  336. priv->io_base +
  337. _REG(AFBC_SIZE_IN));
  338. writel_relaxed(priv->viu.vd1_afbc_dec_def_color,
  339. priv->io_base +
  340. _REG(AFBC_DEC_DEF_COLOR));
  341. writel_relaxed(priv->viu.vd1_afbc_conv_ctrl,
  342. priv->io_base +
  343. _REG(AFBC_CONV_CTRL));
  344. writel_relaxed(priv->viu.vd1_afbc_size_out,
  345. priv->io_base +
  346. _REG(AFBC_SIZE_OUT));
  347. writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl,
  348. priv->io_base +
  349. _REG(AFBC_VD_CFMT_CTRL));
  350. writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w,
  351. priv->io_base +
  352. _REG(AFBC_VD_CFMT_W));
  353. writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope,
  354. priv->io_base +
  355. _REG(AFBC_MIF_HOR_SCOPE));
  356. writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope,
  357. priv->io_base +
  358. _REG(AFBC_MIF_VER_SCOPE));
  359. writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope,
  360. priv->io_base+
  361. _REG(AFBC_PIXEL_HOR_SCOPE));
  362. writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope,
  363. priv->io_base +
  364. _REG(AFBC_PIXEL_VER_SCOPE));
  365. writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h,
  366. priv->io_base +
  367. _REG(AFBC_VD_CFMT_H));
  368. } else {
  369. switch (priv->viu.vd1_planes) {
  370. case 3:
  371. meson_canvas_config(priv->canvas,
  372. priv->canvas_id_vd1_2,
  373. priv->viu.vd1_addr2,
  374. priv->viu.vd1_stride2,
  375. priv->viu.vd1_height2,
  376. MESON_CANVAS_WRAP_NONE,
  377. MESON_CANVAS_BLKMODE_LINEAR,
  378. MESON_CANVAS_ENDIAN_SWAP64);
  379. fallthrough;
  380. case 2:
  381. meson_canvas_config(priv->canvas,
  382. priv->canvas_id_vd1_1,
  383. priv->viu.vd1_addr1,
  384. priv->viu.vd1_stride1,
  385. priv->viu.vd1_height1,
  386. MESON_CANVAS_WRAP_NONE,
  387. MESON_CANVAS_BLKMODE_LINEAR,
  388. MESON_CANVAS_ENDIAN_SWAP64);
  389. fallthrough;
  390. case 1:
  391. meson_canvas_config(priv->canvas,
  392. priv->canvas_id_vd1_0,
  393. priv->viu.vd1_addr0,
  394. priv->viu.vd1_stride0,
  395. priv->viu.vd1_height0,
  396. MESON_CANVAS_WRAP_NONE,
  397. MESON_CANVAS_BLKMODE_LINEAR,
  398. MESON_CANVAS_ENDIAN_SWAP64);
  399. }
  400. writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
  401. }
  402. writel_relaxed(priv->viu.vd1_if0_gen_reg,
  403. priv->io_base + meson_crtc->viu_offset +
  404. _REG(VD1_IF0_GEN_REG));
  405. writel_relaxed(priv->viu.vd1_if0_gen_reg,
  406. priv->io_base + meson_crtc->viu_offset +
  407. _REG(VD2_IF0_GEN_REG));
  408. writel_relaxed(priv->viu.vd1_if0_gen_reg2,
  409. priv->io_base + meson_crtc->viu_offset +
  410. _REG(VD1_IF0_GEN_REG2));
  411. writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
  412. priv->io_base + meson_crtc->viu_offset +
  413. _REG(VIU_VD1_FMT_CTRL));
  414. writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
  415. priv->io_base + meson_crtc->viu_offset +
  416. _REG(VIU_VD2_FMT_CTRL));
  417. writel_relaxed(priv->viu.viu_vd1_fmt_w,
  418. priv->io_base + meson_crtc->viu_offset +
  419. _REG(VIU_VD1_FMT_W));
  420. writel_relaxed(priv->viu.viu_vd1_fmt_w,
  421. priv->io_base + meson_crtc->viu_offset +
  422. _REG(VIU_VD2_FMT_W));
  423. writel_relaxed(priv->viu.vd1_if0_canvas0,
  424. priv->io_base + meson_crtc->viu_offset +
  425. _REG(VD1_IF0_CANVAS0));
  426. writel_relaxed(priv->viu.vd1_if0_canvas0,
  427. priv->io_base + meson_crtc->viu_offset +
  428. _REG(VD1_IF0_CANVAS1));
  429. writel_relaxed(priv->viu.vd1_if0_canvas0,
  430. priv->io_base + meson_crtc->viu_offset +
  431. _REG(VD2_IF0_CANVAS0));
  432. writel_relaxed(priv->viu.vd1_if0_canvas0,
  433. priv->io_base + meson_crtc->viu_offset +
  434. _REG(VD2_IF0_CANVAS1));
  435. writel_relaxed(priv->viu.vd1_if0_luma_x0,
  436. priv->io_base + meson_crtc->viu_offset +
  437. _REG(VD1_IF0_LUMA_X0));
  438. writel_relaxed(priv->viu.vd1_if0_luma_x0,
  439. priv->io_base + meson_crtc->viu_offset +
  440. _REG(VD1_IF0_LUMA_X1));
  441. writel_relaxed(priv->viu.vd1_if0_luma_x0,
  442. priv->io_base + meson_crtc->viu_offset +
  443. _REG(VD2_IF0_LUMA_X0));
  444. writel_relaxed(priv->viu.vd1_if0_luma_x0,
  445. priv->io_base + meson_crtc->viu_offset +
  446. _REG(VD2_IF0_LUMA_X1));
  447. writel_relaxed(priv->viu.vd1_if0_luma_y0,
  448. priv->io_base + meson_crtc->viu_offset +
  449. _REG(VD1_IF0_LUMA_Y0));
  450. writel_relaxed(priv->viu.vd1_if0_luma_y0,
  451. priv->io_base + meson_crtc->viu_offset +
  452. _REG(VD1_IF0_LUMA_Y1));
  453. writel_relaxed(priv->viu.vd1_if0_luma_y0,
  454. priv->io_base + meson_crtc->viu_offset +
  455. _REG(VD2_IF0_LUMA_Y0));
  456. writel_relaxed(priv->viu.vd1_if0_luma_y0,
  457. priv->io_base + meson_crtc->viu_offset +
  458. _REG(VD2_IF0_LUMA_Y1));
  459. writel_relaxed(priv->viu.vd1_if0_chroma_x0,
  460. priv->io_base + meson_crtc->viu_offset +
  461. _REG(VD1_IF0_CHROMA_X0));
  462. writel_relaxed(priv->viu.vd1_if0_chroma_x0,
  463. priv->io_base + meson_crtc->viu_offset +
  464. _REG(VD1_IF0_CHROMA_X1));
  465. writel_relaxed(priv->viu.vd1_if0_chroma_x0,
  466. priv->io_base + meson_crtc->viu_offset +
  467. _REG(VD2_IF0_CHROMA_X0));
  468. writel_relaxed(priv->viu.vd1_if0_chroma_x0,
  469. priv->io_base + meson_crtc->viu_offset +
  470. _REG(VD2_IF0_CHROMA_X1));
  471. writel_relaxed(priv->viu.vd1_if0_chroma_y0,
  472. priv->io_base + meson_crtc->viu_offset +
  473. _REG(VD1_IF0_CHROMA_Y0));
  474. writel_relaxed(priv->viu.vd1_if0_chroma_y0,
  475. priv->io_base + meson_crtc->viu_offset +
  476. _REG(VD1_IF0_CHROMA_Y1));
  477. writel_relaxed(priv->viu.vd1_if0_chroma_y0,
  478. priv->io_base + meson_crtc->viu_offset +
  479. _REG(VD2_IF0_CHROMA_Y0));
  480. writel_relaxed(priv->viu.vd1_if0_chroma_y0,
  481. priv->io_base + meson_crtc->viu_offset +
  482. _REG(VD2_IF0_CHROMA_Y1));
  483. writel_relaxed(priv->viu.vd1_if0_repeat_loop,
  484. priv->io_base + meson_crtc->viu_offset +
  485. _REG(VD1_IF0_RPT_LOOP));
  486. writel_relaxed(priv->viu.vd1_if0_repeat_loop,
  487. priv->io_base + meson_crtc->viu_offset +
  488. _REG(VD2_IF0_RPT_LOOP));
  489. writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
  490. priv->io_base + meson_crtc->viu_offset +
  491. _REG(VD1_IF0_LUMA0_RPT_PAT));
  492. writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
  493. priv->io_base + meson_crtc->viu_offset +
  494. _REG(VD2_IF0_LUMA0_RPT_PAT));
  495. writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
  496. priv->io_base + meson_crtc->viu_offset +
  497. _REG(VD1_IF0_LUMA1_RPT_PAT));
  498. writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
  499. priv->io_base + meson_crtc->viu_offset +
  500. _REG(VD2_IF0_LUMA1_RPT_PAT));
  501. writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
  502. priv->io_base + meson_crtc->viu_offset +
  503. _REG(VD1_IF0_CHROMA0_RPT_PAT));
  504. writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
  505. priv->io_base + meson_crtc->viu_offset +
  506. _REG(VD2_IF0_CHROMA0_RPT_PAT));
  507. writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
  508. priv->io_base + meson_crtc->viu_offset +
  509. _REG(VD1_IF0_CHROMA1_RPT_PAT));
  510. writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
  511. priv->io_base + meson_crtc->viu_offset +
  512. _REG(VD2_IF0_CHROMA1_RPT_PAT));
  513. writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
  514. _REG(VD1_IF0_LUMA_PSEL));
  515. writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
  516. _REG(VD1_IF0_CHROMA_PSEL));
  517. writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
  518. _REG(VD2_IF0_LUMA_PSEL));
  519. writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
  520. _REG(VD2_IF0_CHROMA_PSEL));
  521. writel_relaxed(priv->viu.vd1_range_map_y,
  522. priv->io_base + meson_crtc->viu_offset +
  523. _REG(VD1_IF0_RANGE_MAP_Y));
  524. writel_relaxed(priv->viu.vd1_range_map_cb,
  525. priv->io_base + meson_crtc->viu_offset +
  526. _REG(VD1_IF0_RANGE_MAP_CB));
  527. writel_relaxed(priv->viu.vd1_range_map_cr,
  528. priv->io_base + meson_crtc->viu_offset +
  529. _REG(VD1_IF0_RANGE_MAP_CR));
  530. writel_relaxed(VPP_VSC_BANK_LENGTH(4) |
  531. VPP_HSC_BANK_LENGTH(4) |
  532. VPP_SC_VD_EN_ENABLE |
  533. VPP_SC_TOP_EN_ENABLE |
  534. VPP_SC_HSC_EN_ENABLE |
  535. VPP_SC_VSC_EN_ENABLE,
  536. priv->io_base + _REG(VPP_SC_MISC));
  537. writel_relaxed(priv->viu.vpp_pic_in_height,
  538. priv->io_base + _REG(VPP_PIC_IN_HEIGHT));
  539. writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end,
  540. priv->io_base + _REG(VPP_POSTBLEND_VD1_H_START_END));
  541. writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end,
  542. priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
  543. writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end,
  544. priv->io_base + _REG(VPP_POSTBLEND_VD1_V_START_END));
  545. writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end,
  546. priv->io_base + _REG(VPP_BLEND_VD2_V_START_END));
  547. writel_relaxed(priv->viu.vpp_hsc_region12_startp,
  548. priv->io_base + _REG(VPP_HSC_REGION12_STARTP));
  549. writel_relaxed(priv->viu.vpp_hsc_region34_startp,
  550. priv->io_base + _REG(VPP_HSC_REGION34_STARTP));
  551. writel_relaxed(priv->viu.vpp_hsc_region4_endp,
  552. priv->io_base + _REG(VPP_HSC_REGION4_ENDP));
  553. writel_relaxed(priv->viu.vpp_hsc_start_phase_step,
  554. priv->io_base + _REG(VPP_HSC_START_PHASE_STEP));
  555. writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope,
  556. priv->io_base + _REG(VPP_HSC_REGION1_PHASE_SLOPE));
  557. writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope,
  558. priv->io_base + _REG(VPP_HSC_REGION3_PHASE_SLOPE));
  559. writel_relaxed(priv->viu.vpp_line_in_length,
  560. priv->io_base + _REG(VPP_LINE_IN_LENGTH));
  561. writel_relaxed(priv->viu.vpp_preblend_h_size,
  562. priv->io_base + _REG(VPP_PREBLEND_H_SIZE));
  563. writel_relaxed(priv->viu.vpp_vsc_region12_startp,
  564. priv->io_base + _REG(VPP_VSC_REGION12_STARTP));
  565. writel_relaxed(priv->viu.vpp_vsc_region34_startp,
  566. priv->io_base + _REG(VPP_VSC_REGION34_STARTP));
  567. writel_relaxed(priv->viu.vpp_vsc_region4_endp,
  568. priv->io_base + _REG(VPP_VSC_REGION4_ENDP));
  569. writel_relaxed(priv->viu.vpp_vsc_start_phase_step,
  570. priv->io_base + _REG(VPP_VSC_START_PHASE_STEP));
  571. writel_relaxed(priv->viu.vpp_vsc_ini_phase,
  572. priv->io_base + _REG(VPP_VSC_INI_PHASE));
  573. writel_relaxed(priv->viu.vpp_vsc_phase_ctrl,
  574. priv->io_base + _REG(VPP_VSC_PHASE_CTRL));
  575. writel_relaxed(priv->viu.vpp_hsc_phase_ctrl,
  576. priv->io_base + _REG(VPP_HSC_PHASE_CTRL));
  577. writel_relaxed(0x42, priv->io_base + _REG(VPP_SCALE_COEF_IDX));
  578. /* Enable VD1 */
  579. if (meson_crtc->enable_vd1)
  580. meson_crtc->enable_vd1(priv);
  581. priv->viu.vd1_commit = false;
  582. }
  583. if (meson_crtc->vsync_disabled)
  584. return;
  585. drm_crtc_handle_vblank(priv->crtc);
  586. spin_lock_irqsave(&priv->drm->event_lock, flags);
  587. if (meson_crtc->event) {
  588. drm_crtc_send_vblank_event(priv->crtc, meson_crtc->event);
  589. drm_crtc_vblank_put(priv->crtc);
  590. meson_crtc->event = NULL;
  591. }
  592. spin_unlock_irqrestore(&priv->drm->event_lock, flags);
  593. }
  594. int meson_crtc_create(struct meson_drm *priv)
  595. {
  596. struct meson_crtc *meson_crtc;
  597. struct drm_crtc *crtc;
  598. int ret;
  599. meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc),
  600. GFP_KERNEL);
  601. if (!meson_crtc)
  602. return -ENOMEM;
  603. meson_crtc->priv = priv;
  604. crtc = &meson_crtc->base;
  605. ret = drm_crtc_init_with_planes(priv->drm, crtc,
  606. priv->primary_plane, NULL,
  607. &meson_crtc_funcs, "meson_crtc");
  608. if (ret) {
  609. dev_err(priv->drm->dev, "Failed to init CRTC\n");
  610. return ret;
  611. }
  612. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  613. meson_crtc->enable_osd1 = meson_g12a_crtc_enable_osd1;
  614. meson_crtc->enable_vd1 = meson_g12a_crtc_enable_vd1;
  615. meson_crtc->viu_offset = MESON_G12A_VIU_OFFSET;
  616. meson_crtc->enable_osd1_afbc =
  617. meson_crtc_g12a_enable_osd1_afbc;
  618. meson_crtc->disable_osd1_afbc =
  619. meson_viu_g12a_disable_osd1_afbc;
  620. drm_crtc_helper_add(crtc, &meson_g12a_crtc_helper_funcs);
  621. } else {
  622. meson_crtc->enable_osd1 = meson_crtc_enable_osd1;
  623. meson_crtc->enable_vd1 = meson_crtc_enable_vd1;
  624. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
  625. meson_crtc->enable_osd1_afbc =
  626. meson_viu_gxm_enable_osd1_afbc;
  627. meson_crtc->disable_osd1_afbc =
  628. meson_viu_gxm_disable_osd1_afbc;
  629. }
  630. drm_crtc_helper_add(crtc, &meson_crtc_helper_funcs);
  631. }
  632. priv->crtc = crtc;
  633. return 0;
  634. }