mtk_mt8183_mipi_tx.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 MediaTek Inc.
  4. * Author: jitao.shi <jitao.shi@mediatek.com>
  5. */
  6. #include "mtk_mipi_tx.h"
  7. #define MIPITX_LANE_CON 0x000c
  8. #define RG_DSI_CPHY_T1DRV_EN BIT(0)
  9. #define RG_DSI_ANA_CK_SEL BIT(1)
  10. #define RG_DSI_PHY_CK_SEL BIT(2)
  11. #define RG_DSI_CPHY_EN BIT(3)
  12. #define RG_DSI_PHYCK_INV_EN BIT(4)
  13. #define RG_DSI_PWR04_EN BIT(5)
  14. #define RG_DSI_BG_LPF_EN BIT(6)
  15. #define RG_DSI_BG_CORE_EN BIT(7)
  16. #define RG_DSI_PAD_TIEL_SEL BIT(8)
  17. #define MIPITX_VOLTAGE_SEL 0x0010
  18. #define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6)
  19. #define MIPITX_PLL_PWR 0x0028
  20. #define MIPITX_PLL_CON0 0x002c
  21. #define MIPITX_PLL_CON1 0x0030
  22. #define MIPITX_PLL_CON2 0x0034
  23. #define MIPITX_PLL_CON3 0x0038
  24. #define MIPITX_PLL_CON4 0x003c
  25. #define RG_DSI_PLL_IBIAS (3 << 10)
  26. #define MIPITX_D2P_RTCODE 0x0100
  27. #define MIPITX_D2_SW_CTL_EN 0x0144
  28. #define MIPITX_D0_SW_CTL_EN 0x0244
  29. #define MIPITX_CK_CKMODE_EN 0x0328
  30. #define DSI_CK_CKMODE_EN BIT(0)
  31. #define MIPITX_CK_SW_CTL_EN 0x0344
  32. #define MIPITX_D1_SW_CTL_EN 0x0444
  33. #define MIPITX_D3_SW_CTL_EN 0x0544
  34. #define DSI_SW_CTL_EN BIT(0)
  35. #define AD_DSI_PLL_SDM_PWR_ON BIT(0)
  36. #define AD_DSI_PLL_SDM_ISO_EN BIT(1)
  37. #define RG_DSI_PLL_EN BIT(4)
  38. #define RG_DSI_PLL_POSDIV (0x7 << 8)
  39. static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
  40. {
  41. struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
  42. unsigned int txdiv, txdiv0;
  43. u64 pcw;
  44. dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
  45. if (mipi_tx->data_rate >= 2000000000) {
  46. txdiv = 1;
  47. txdiv0 = 0;
  48. } else if (mipi_tx->data_rate >= 1000000000) {
  49. txdiv = 2;
  50. txdiv0 = 1;
  51. } else if (mipi_tx->data_rate >= 500000000) {
  52. txdiv = 4;
  53. txdiv0 = 2;
  54. } else if (mipi_tx->data_rate > 250000000) {
  55. txdiv = 8;
  56. txdiv0 = 3;
  57. } else if (mipi_tx->data_rate >= 125000000) {
  58. txdiv = 16;
  59. txdiv0 = 4;
  60. } else {
  61. return -EINVAL;
  62. }
  63. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
  64. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
  65. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
  66. udelay(1);
  67. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
  68. pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000);
  69. writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0);
  70. mtk_mipi_tx_update_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
  71. txdiv0 << 8);
  72. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
  73. return 0;
  74. }
  75. static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
  76. {
  77. struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
  78. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
  79. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
  80. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
  81. }
  82. static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  83. unsigned long *prate)
  84. {
  85. return clamp_val(rate, 50000000, 1600000000);
  86. }
  87. static const struct clk_ops mtk_mipi_tx_pll_ops = {
  88. .enable = mtk_mipi_tx_pll_enable,
  89. .disable = mtk_mipi_tx_pll_disable,
  90. .round_rate = mtk_mipi_tx_pll_round_rate,
  91. .set_rate = mtk_mipi_tx_pll_set_rate,
  92. .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
  93. };
  94. static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
  95. {
  96. int i, j;
  97. for (i = 0; i < 5; i++) {
  98. if ((mipi_tx->rt_code[i] & 0x1f) == 0)
  99. mipi_tx->rt_code[i] |= 0x10;
  100. if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0)
  101. mipi_tx->rt_code[i] |= 0x10 << 5;
  102. for (j = 0; j < 10; j++)
  103. mtk_mipi_tx_update_bits(mipi_tx,
  104. MIPITX_D2P_RTCODE * (i + 1) + j * 4,
  105. 1, mipi_tx->rt_code[i] >> j & 1);
  106. }
  107. }
  108. static void mtk_mipi_tx_power_on_signal(struct phy *phy)
  109. {
  110. struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
  111. /* BG_LPF_EN / BG_CORE_EN */
  112. writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
  113. mipi_tx->regs + MIPITX_LANE_CON);
  114. usleep_range(30, 100);
  115. writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN,
  116. mipi_tx->regs + MIPITX_LANE_CON);
  117. /* Switch OFF each Lane */
  118. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
  119. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
  120. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
  121. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
  122. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
  123. mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
  124. RG_DSI_HSTX_LDO_REF_SEL,
  125. (mipi_tx->mipitx_drive - 3000) / 200 << 6);
  126. mtk_mipi_tx_config_calibration_data(mipi_tx);
  127. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
  128. }
  129. static void mtk_mipi_tx_power_off_signal(struct phy *phy)
  130. {
  131. struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
  132. /* Switch ON each Lane */
  133. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
  134. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
  135. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
  136. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
  137. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
  138. writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
  139. mipi_tx->regs + MIPITX_LANE_CON);
  140. writel(RG_DSI_PAD_TIEL_SEL, mipi_tx->regs + MIPITX_LANE_CON);
  141. }
  142. const struct mtk_mipitx_data mt8183_mipitx_data = {
  143. .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
  144. .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
  145. .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
  146. };