mtk_mt8173_mipi_tx.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 MediaTek Inc.
  4. * Author: jitao.shi <jitao.shi@mediatek.com>
  5. */
  6. #include "mtk_mipi_tx.h"
  7. #define MIPITX_DSI_CON 0x00
  8. #define RG_DSI_LDOCORE_EN BIT(0)
  9. #define RG_DSI_CKG_LDOOUT_EN BIT(1)
  10. #define RG_DSI_BCLK_SEL (3 << 2)
  11. #define RG_DSI_LD_IDX_SEL (7 << 4)
  12. #define RG_DSI_PHYCLK_SEL (2 << 8)
  13. #define RG_DSI_DSICLK_FREQ_SEL BIT(10)
  14. #define RG_DSI_LPTX_CLMP_EN BIT(11)
  15. #define MIPITX_DSI_CLOCK_LANE 0x04
  16. #define MIPITX_DSI_DATA_LANE0 0x08
  17. #define MIPITX_DSI_DATA_LANE1 0x0c
  18. #define MIPITX_DSI_DATA_LANE2 0x10
  19. #define MIPITX_DSI_DATA_LANE3 0x14
  20. #define RG_DSI_LNTx_LDOOUT_EN BIT(0)
  21. #define RG_DSI_LNTx_CKLANE_EN BIT(1)
  22. #define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2)
  23. #define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3)
  24. #define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
  25. #define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
  26. #define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
  27. #define RG_DSI_LNTx_RT_CODE (0xf << 8)
  28. #define MIPITX_DSI_TOP_CON 0x40
  29. #define RG_DSI_LNT_INTR_EN BIT(0)
  30. #define RG_DSI_LNT_HS_BIAS_EN BIT(1)
  31. #define RG_DSI_LNT_IMP_CAL_EN BIT(2)
  32. #define RG_DSI_LNT_TESTMODE_EN BIT(3)
  33. #define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
  34. #define RG_DSI_LNT_AIO_SEL (7 << 8)
  35. #define RG_DSI_PAD_TIE_LOW_EN BIT(11)
  36. #define RG_DSI_DEBUG_INPUT_EN BIT(12)
  37. #define RG_DSI_PRESERVE (7 << 13)
  38. #define MIPITX_DSI_BG_CON 0x44
  39. #define RG_DSI_BG_CORE_EN BIT(0)
  40. #define RG_DSI_BG_CKEN BIT(1)
  41. #define RG_DSI_BG_DIV (0x3 << 2)
  42. #define RG_DSI_BG_FAST_CHARGE BIT(4)
  43. #define RG_DSI_VOUT_MSK (0x3ffff << 5)
  44. #define RG_DSI_V12_SEL (7 << 5)
  45. #define RG_DSI_V10_SEL (7 << 8)
  46. #define RG_DSI_V072_SEL (7 << 11)
  47. #define RG_DSI_V04_SEL (7 << 14)
  48. #define RG_DSI_V032_SEL (7 << 17)
  49. #define RG_DSI_V02_SEL (7 << 20)
  50. #define RG_DSI_BG_R1_TRIM (0xf << 24)
  51. #define RG_DSI_BG_R2_TRIM (0xf << 28)
  52. #define MIPITX_DSI_PLL_CON0 0x50
  53. #define RG_DSI_MPPLL_PLL_EN BIT(0)
  54. #define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
  55. #define RG_DSI_MPPLL_PREDIV (3 << 1)
  56. #define RG_DSI_MPPLL_TXDIV0 (3 << 3)
  57. #define RG_DSI_MPPLL_TXDIV1 (3 << 5)
  58. #define RG_DSI_MPPLL_POSDIV (7 << 7)
  59. #define RG_DSI_MPPLL_MONVC_EN BIT(10)
  60. #define RG_DSI_MPPLL_MONREF_EN BIT(11)
  61. #define RG_DSI_MPPLL_VOD_EN BIT(12)
  62. #define MIPITX_DSI_PLL_CON1 0x54
  63. #define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
  64. #define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
  65. #define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
  66. #define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
  67. #define MIPITX_DSI_PLL_CON2 0x58
  68. #define MIPITX_DSI_PLL_TOP 0x64
  69. #define RG_DSI_MPPLL_PRESERVE (0xff << 8)
  70. #define MIPITX_DSI_PLL_PWR 0x68
  71. #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
  72. #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1)
  73. #define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8)
  74. #define MIPITX_DSI_SW_CTRL 0x80
  75. #define SW_CTRL_EN BIT(0)
  76. #define MIPITX_DSI_SW_CTRL_CON0 0x84
  77. #define SW_LNTC_LPTX_PRE_OE BIT(0)
  78. #define SW_LNTC_LPTX_OE BIT(1)
  79. #define SW_LNTC_LPTX_P BIT(2)
  80. #define SW_LNTC_LPTX_N BIT(3)
  81. #define SW_LNTC_HSTX_PRE_OE BIT(4)
  82. #define SW_LNTC_HSTX_OE BIT(5)
  83. #define SW_LNTC_HSTX_ZEROCLK BIT(6)
  84. #define SW_LNT0_LPTX_PRE_OE BIT(7)
  85. #define SW_LNT0_LPTX_OE BIT(8)
  86. #define SW_LNT0_LPTX_P BIT(9)
  87. #define SW_LNT0_LPTX_N BIT(10)
  88. #define SW_LNT0_HSTX_PRE_OE BIT(11)
  89. #define SW_LNT0_HSTX_OE BIT(12)
  90. #define SW_LNT0_LPRX_EN BIT(13)
  91. #define SW_LNT1_LPTX_PRE_OE BIT(14)
  92. #define SW_LNT1_LPTX_OE BIT(15)
  93. #define SW_LNT1_LPTX_P BIT(16)
  94. #define SW_LNT1_LPTX_N BIT(17)
  95. #define SW_LNT1_HSTX_PRE_OE BIT(18)
  96. #define SW_LNT1_HSTX_OE BIT(19)
  97. #define SW_LNT2_LPTX_PRE_OE BIT(20)
  98. #define SW_LNT2_LPTX_OE BIT(21)
  99. #define SW_LNT2_LPTX_P BIT(22)
  100. #define SW_LNT2_LPTX_N BIT(23)
  101. #define SW_LNT2_HSTX_PRE_OE BIT(24)
  102. #define SW_LNT2_HSTX_OE BIT(25)
  103. static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
  104. {
  105. struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
  106. u8 txdiv, txdiv0, txdiv1;
  107. u64 pcw;
  108. dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate);
  109. if (mipi_tx->data_rate >= 500000000) {
  110. txdiv = 1;
  111. txdiv0 = 0;
  112. txdiv1 = 0;
  113. } else if (mipi_tx->data_rate >= 250000000) {
  114. txdiv = 2;
  115. txdiv0 = 1;
  116. txdiv1 = 0;
  117. } else if (mipi_tx->data_rate >= 125000000) {
  118. txdiv = 4;
  119. txdiv0 = 2;
  120. txdiv1 = 0;
  121. } else if (mipi_tx->data_rate > 62000000) {
  122. txdiv = 8;
  123. txdiv0 = 2;
  124. txdiv1 = 1;
  125. } else if (mipi_tx->data_rate >= 50000000) {
  126. txdiv = 16;
  127. txdiv0 = 2;
  128. txdiv1 = 2;
  129. } else {
  130. return -EINVAL;
  131. }
  132. mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
  133. RG_DSI_VOUT_MSK |
  134. RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
  135. (4 << 20) | (4 << 17) | (4 << 14) |
  136. (4 << 11) | (4 << 8) | (4 << 5) |
  137. RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
  138. usleep_range(30, 100);
  139. mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
  140. RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
  141. (8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
  142. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
  143. RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
  144. mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
  145. RG_DSI_MPPLL_SDM_PWR_ON |
  146. RG_DSI_MPPLL_SDM_ISO_EN,
  147. RG_DSI_MPPLL_SDM_PWR_ON);
  148. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
  149. RG_DSI_MPPLL_PLL_EN);
  150. mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
  151. RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
  152. RG_DSI_MPPLL_PREDIV,
  153. (txdiv0 << 3) | (txdiv1 << 5));
  154. /*
  155. * PLL PCW config
  156. * PCW bit 24~30 = integer part of pcw
  157. * PCW bit 0~23 = fractional part of pcw
  158. * pcw = data_Rate*4*txdiv/(Ref_clk*2);
  159. * Post DIV =4, so need data_Rate*4
  160. * Ref_clk is 26MHz
  161. */
  162. pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24,
  163. 26000000);
  164. writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);
  165. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
  166. RG_DSI_MPPLL_SDM_FRA_EN);
  167. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
  168. usleep_range(20, 100);
  169. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
  170. RG_DSI_MPPLL_SDM_SSC_EN);
  171. mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
  172. RG_DSI_MPPLL_PRESERVE,
  173. mipi_tx->driver_data->mppll_preserve);
  174. return 0;
  175. }
  176. static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
  177. {
  178. struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
  179. dev_dbg(mipi_tx->dev, "unprepare\n");
  180. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
  181. RG_DSI_MPPLL_PLL_EN);
  182. mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
  183. RG_DSI_MPPLL_PRESERVE, 0);
  184. mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
  185. RG_DSI_MPPLL_SDM_ISO_EN |
  186. RG_DSI_MPPLL_SDM_PWR_ON,
  187. RG_DSI_MPPLL_SDM_ISO_EN);
  188. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
  189. RG_DSI_LNT_HS_BIAS_EN);
  190. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON,
  191. RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
  192. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON,
  193. RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
  194. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
  195. RG_DSI_MPPLL_DIV_MSK);
  196. }
  197. static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  198. unsigned long *prate)
  199. {
  200. return clamp_val(rate, 50000000, 1250000000);
  201. }
  202. static const struct clk_ops mtk_mipi_tx_pll_ops = {
  203. .prepare = mtk_mipi_tx_pll_prepare,
  204. .unprepare = mtk_mipi_tx_pll_unprepare,
  205. .round_rate = mtk_mipi_tx_pll_round_rate,
  206. .set_rate = mtk_mipi_tx_pll_set_rate,
  207. .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
  208. };
  209. static void mtk_mipi_tx_power_on_signal(struct phy *phy)
  210. {
  211. struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
  212. u32 reg;
  213. for (reg = MIPITX_DSI_CLOCK_LANE;
  214. reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
  215. mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
  216. mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
  217. RG_DSI_PAD_TIE_LOW_EN);
  218. }
  219. static void mtk_mipi_tx_power_off_signal(struct phy *phy)
  220. {
  221. struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
  222. u32 reg;
  223. mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
  224. RG_DSI_PAD_TIE_LOW_EN);
  225. for (reg = MIPITX_DSI_CLOCK_LANE;
  226. reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
  227. mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
  228. }
  229. const struct mtk_mipitx_data mt2701_mipitx_data = {
  230. .mppll_preserve = (3 << 8),
  231. .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
  232. .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
  233. .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
  234. };
  235. const struct mtk_mipitx_data mt8173_mipitx_data = {
  236. .mppll_preserve = (0 << 8),
  237. .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
  238. .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
  239. .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
  240. };