mtk_mipi_tx.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015 MediaTek Inc.
  4. */
  5. #include "mtk_mipi_tx.h"
  6. inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
  7. {
  8. return container_of(hw, struct mtk_mipi_tx, pll_hw);
  9. }
  10. void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
  11. u32 bits)
  12. {
  13. u32 temp = readl(mipi_tx->regs + offset);
  14. writel(temp & ~bits, mipi_tx->regs + offset);
  15. }
  16. void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
  17. u32 bits)
  18. {
  19. u32 temp = readl(mipi_tx->regs + offset);
  20. writel(temp | bits, mipi_tx->regs + offset);
  21. }
  22. void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
  23. u32 mask, u32 data)
  24. {
  25. u32 temp = readl(mipi_tx->regs + offset);
  26. writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
  27. }
  28. int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  29. unsigned long parent_rate)
  30. {
  31. struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
  32. dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
  33. mipi_tx->data_rate = rate;
  34. return 0;
  35. }
  36. unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
  37. unsigned long parent_rate)
  38. {
  39. struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
  40. return mipi_tx->data_rate;
  41. }
  42. static int mtk_mipi_tx_power_on(struct phy *phy)
  43. {
  44. struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
  45. int ret;
  46. /* Power up core and enable PLL */
  47. ret = clk_prepare_enable(mipi_tx->pll);
  48. if (ret < 0)
  49. return ret;
  50. /* Enable DSI Lane LDO outputs, disable pad tie low */
  51. mipi_tx->driver_data->mipi_tx_enable_signal(phy);
  52. return 0;
  53. }
  54. static int mtk_mipi_tx_power_off(struct phy *phy)
  55. {
  56. struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
  57. /* Enable pad tie low, disable DSI Lane LDO outputs */
  58. mipi_tx->driver_data->mipi_tx_disable_signal(phy);
  59. /* Disable PLL and power down core */
  60. clk_disable_unprepare(mipi_tx->pll);
  61. return 0;
  62. }
  63. static const struct phy_ops mtk_mipi_tx_ops = {
  64. .power_on = mtk_mipi_tx_power_on,
  65. .power_off = mtk_mipi_tx_power_off,
  66. .owner = THIS_MODULE,
  67. };
  68. static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx)
  69. {
  70. struct nvmem_cell *cell;
  71. size_t len;
  72. u32 *buf;
  73. cell = nvmem_cell_get(mipi_tx->dev, "calibration-data");
  74. if (IS_ERR(cell)) {
  75. dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n");
  76. return;
  77. }
  78. buf = (u32 *)nvmem_cell_read(cell, &len);
  79. nvmem_cell_put(cell);
  80. if (IS_ERR(buf)) {
  81. dev_info(mipi_tx->dev, "can't get data, ignore it\n");
  82. return;
  83. }
  84. if (len < 3 * sizeof(u32)) {
  85. dev_info(mipi_tx->dev, "invalid calibration data\n");
  86. kfree(buf);
  87. return;
  88. }
  89. mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) |
  90. (buf[0] >> 11 & 0x1f);
  91. mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) |
  92. (buf[0] >> 1 & 0x1f);
  93. mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) |
  94. (buf[1] >> 22 & 0x1f);
  95. mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) |
  96. (buf[1] >> 12 & 0x1f);
  97. mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) |
  98. (buf[1] >> 2 & 0x1f);
  99. kfree(buf);
  100. }
  101. static int mtk_mipi_tx_probe(struct platform_device *pdev)
  102. {
  103. struct device *dev = &pdev->dev;
  104. struct mtk_mipi_tx *mipi_tx;
  105. struct resource *mem;
  106. const char *ref_clk_name;
  107. struct clk *ref_clk;
  108. struct clk_init_data clk_init = {
  109. .num_parents = 1,
  110. .parent_names = (const char * const *)&ref_clk_name,
  111. .flags = CLK_SET_RATE_GATE,
  112. };
  113. struct phy *phy;
  114. struct phy_provider *phy_provider;
  115. int ret;
  116. mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
  117. if (!mipi_tx)
  118. return -ENOMEM;
  119. mipi_tx->driver_data = of_device_get_match_data(dev);
  120. if (!mipi_tx->driver_data)
  121. return -ENODEV;
  122. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  123. mipi_tx->regs = devm_ioremap_resource(dev, mem);
  124. if (IS_ERR(mipi_tx->regs)) {
  125. ret = PTR_ERR(mipi_tx->regs);
  126. dev_err(dev, "Failed to get memory resource: %d\n", ret);
  127. return ret;
  128. }
  129. ref_clk = devm_clk_get(dev, NULL);
  130. if (IS_ERR(ref_clk)) {
  131. ret = PTR_ERR(ref_clk);
  132. dev_err(dev, "Failed to get reference clock: %d\n", ret);
  133. return ret;
  134. }
  135. ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
  136. &mipi_tx->mipitx_drive);
  137. /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
  138. if (ret < 0)
  139. mipi_tx->mipitx_drive = 4600;
  140. /* check the mipitx_drive valid */
  141. if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
  142. dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n",
  143. mipi_tx->mipitx_drive);
  144. mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
  145. 6000);
  146. }
  147. ref_clk_name = __clk_get_name(ref_clk);
  148. ret = of_property_read_string(dev->of_node, "clock-output-names",
  149. &clk_init.name);
  150. if (ret < 0) {
  151. dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
  152. return ret;
  153. }
  154. clk_init.ops = mipi_tx->driver_data->mipi_tx_clk_ops;
  155. mipi_tx->pll_hw.init = &clk_init;
  156. mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
  157. if (IS_ERR(mipi_tx->pll)) {
  158. ret = PTR_ERR(mipi_tx->pll);
  159. dev_err(dev, "Failed to register PLL: %d\n", ret);
  160. return ret;
  161. }
  162. phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
  163. if (IS_ERR(phy)) {
  164. ret = PTR_ERR(phy);
  165. dev_err(dev, "Failed to create MIPI D-PHY: %d\n", ret);
  166. return ret;
  167. }
  168. phy_set_drvdata(phy, mipi_tx);
  169. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  170. if (IS_ERR(phy_provider)) {
  171. ret = PTR_ERR(phy_provider);
  172. return ret;
  173. }
  174. mipi_tx->dev = dev;
  175. mtk_mipi_tx_get_calibration_datal(mipi_tx);
  176. return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
  177. mipi_tx->pll);
  178. }
  179. static int mtk_mipi_tx_remove(struct platform_device *pdev)
  180. {
  181. of_clk_del_provider(pdev->dev.of_node);
  182. return 0;
  183. }
  184. static const struct of_device_id mtk_mipi_tx_match[] = {
  185. { .compatible = "mediatek,mt2701-mipi-tx",
  186. .data = &mt2701_mipitx_data },
  187. { .compatible = "mediatek,mt8173-mipi-tx",
  188. .data = &mt8173_mipitx_data },
  189. { .compatible = "mediatek,mt8183-mipi-tx",
  190. .data = &mt8183_mipitx_data },
  191. { },
  192. };
  193. struct platform_driver mtk_mipi_tx_driver = {
  194. .probe = mtk_mipi_tx_probe,
  195. .remove = mtk_mipi_tx_remove,
  196. .driver = {
  197. .name = "mediatek-mipi-tx",
  198. .of_match_table = mtk_mipi_tx_match,
  199. },
  200. };