mtk_hdmi_ddc.c 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: Jie Qiu <jie.qiu@mediatek.com>
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/i2c.h>
  9. #include <linux/time.h>
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. #include <linux/err.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/clk.h>
  15. #include <linux/slab.h>
  16. #include <linux/io.h>
  17. #include <linux/iopoll.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/of_platform.h>
  21. #define SIF1_CLOK (288)
  22. #define DDC_DDCMCTL0 (0x0)
  23. #define DDCM_ODRAIN BIT(31)
  24. #define DDCM_CLK_DIV_OFFSET (16)
  25. #define DDCM_CLK_DIV_MASK (0xfff << 16)
  26. #define DDCM_CS_STATUS BIT(4)
  27. #define DDCM_SCL_STATE BIT(3)
  28. #define DDCM_SDA_STATE BIT(2)
  29. #define DDCM_SM0EN BIT(1)
  30. #define DDCM_SCL_STRECH BIT(0)
  31. #define DDC_DDCMCTL1 (0x4)
  32. #define DDCM_ACK_OFFSET (16)
  33. #define DDCM_ACK_MASK (0xff << 16)
  34. #define DDCM_PGLEN_OFFSET (8)
  35. #define DDCM_PGLEN_MASK (0x7 << 8)
  36. #define DDCM_SIF_MODE_OFFSET (4)
  37. #define DDCM_SIF_MODE_MASK (0x7 << 4)
  38. #define DDCM_START (0x1)
  39. #define DDCM_WRITE_DATA (0x2)
  40. #define DDCM_STOP (0x3)
  41. #define DDCM_READ_DATA_NO_ACK (0x4)
  42. #define DDCM_READ_DATA_ACK (0x5)
  43. #define DDCM_TRI BIT(0)
  44. #define DDC_DDCMD0 (0x8)
  45. #define DDCM_DATA3 (0xff << 24)
  46. #define DDCM_DATA2 (0xff << 16)
  47. #define DDCM_DATA1 (0xff << 8)
  48. #define DDCM_DATA0 (0xff << 0)
  49. #define DDC_DDCMD1 (0xc)
  50. #define DDCM_DATA7 (0xff << 24)
  51. #define DDCM_DATA6 (0xff << 16)
  52. #define DDCM_DATA5 (0xff << 8)
  53. #define DDCM_DATA4 (0xff << 0)
  54. struct mtk_hdmi_ddc {
  55. struct i2c_adapter adap;
  56. struct clk *clk;
  57. void __iomem *regs;
  58. };
  59. static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
  60. unsigned int val)
  61. {
  62. writel(readl(ddc->regs + offset) | val, ddc->regs + offset);
  63. }
  64. static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
  65. unsigned int val)
  66. {
  67. writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);
  68. }
  69. static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset,
  70. unsigned int val)
  71. {
  72. return (readl(ddc->regs + offset) & val) == val;
  73. }
  74. static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset,
  75. unsigned int mask, unsigned int shift,
  76. unsigned int val)
  77. {
  78. unsigned int tmp;
  79. tmp = readl(ddc->regs + offset);
  80. tmp &= ~mask;
  81. tmp |= (val << shift) & mask;
  82. writel(tmp, ddc->regs + offset);
  83. }
  84. static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc,
  85. unsigned int offset, unsigned int mask,
  86. unsigned int shift)
  87. {
  88. return (readl(ddc->regs + offset) & mask) >> shift;
  89. }
  90. static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode)
  91. {
  92. u32 val;
  93. sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,
  94. DDCM_SIF_MODE_OFFSET, mode);
  95. sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);
  96. readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,
  97. (val & DDCM_TRI) != DDCM_TRI, 4, 20000);
  98. }
  99. static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
  100. {
  101. struct device *dev = ddc->adap.dev.parent;
  102. u32 remain_count, ack_count, ack_final, read_count, temp_count;
  103. u32 index = 0;
  104. u32 ack;
  105. int i;
  106. ddcm_trigger_mode(ddc, DDCM_START);
  107. sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
  108. sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
  109. 0x00);
  110. ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
  111. ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
  112. dev_dbg(dev, "ack = 0x%x\n", ack);
  113. if (ack != 0x01) {
  114. dev_err(dev, "i2c ack err!\n");
  115. return -ENXIO;
  116. }
  117. remain_count = msg->len;
  118. ack_count = (msg->len - 1) / 8;
  119. ack_final = 0;
  120. while (remain_count > 0) {
  121. if (ack_count > 0) {
  122. read_count = 8;
  123. ack_final = 0;
  124. ack_count--;
  125. } else {
  126. read_count = remain_count;
  127. ack_final = 1;
  128. }
  129. sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,
  130. DDCM_PGLEN_OFFSET, read_count - 1);
  131. ddcm_trigger_mode(ddc, (ack_final == 1) ?
  132. DDCM_READ_DATA_NO_ACK :
  133. DDCM_READ_DATA_ACK);
  134. ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,
  135. DDCM_ACK_OFFSET);
  136. temp_count = 0;
  137. while (((ack & (1 << temp_count)) != 0) && (temp_count < 8))
  138. temp_count++;
  139. if (((ack_final == 1) && (temp_count != (read_count - 1))) ||
  140. ((ack_final == 0) && (temp_count != read_count))) {
  141. dev_err(dev, "Address NACK! ACK(0x%x)\n", ack);
  142. break;
  143. }
  144. for (i = read_count; i >= 1; i--) {
  145. int shift;
  146. int offset;
  147. if (i > 4) {
  148. offset = DDC_DDCMD1;
  149. shift = (i - 5) * 8;
  150. } else {
  151. offset = DDC_DDCMD0;
  152. shift = (i - 1) * 8;
  153. }
  154. msg->buf[index + i - 1] = sif_read_mask(ddc, offset,
  155. 0xff << shift,
  156. shift);
  157. }
  158. remain_count -= read_count;
  159. index += read_count;
  160. }
  161. return 0;
  162. }
  163. static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
  164. {
  165. struct device *dev = ddc->adap.dev.parent;
  166. u32 ack;
  167. ddcm_trigger_mode(ddc, DDCM_START);
  168. sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
  169. sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);
  170. sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
  171. 0x1);
  172. ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
  173. ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
  174. dev_dbg(dev, "ack = %d\n", ack);
  175. if (ack != 0x03) {
  176. dev_err(dev, "i2c ack err!\n");
  177. return -EIO;
  178. }
  179. return 0;
  180. }
  181. static int mtk_hdmi_ddc_xfer(struct i2c_adapter *adapter,
  182. struct i2c_msg *msgs, int num)
  183. {
  184. struct mtk_hdmi_ddc *ddc = adapter->algo_data;
  185. struct device *dev = adapter->dev.parent;
  186. int ret;
  187. int i;
  188. if (!ddc) {
  189. dev_err(dev, "invalid arguments\n");
  190. return -EINVAL;
  191. }
  192. sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);
  193. sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);
  194. sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);
  195. if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {
  196. dev_err(dev, "ddc line is busy!\n");
  197. return -EBUSY;
  198. }
  199. sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,
  200. DDCM_CLK_DIV_OFFSET, SIF1_CLOK);
  201. for (i = 0; i < num; i++) {
  202. struct i2c_msg *msg = &msgs[i];
  203. dev_dbg(dev, "i2c msg, adr:0x%x, flags:%d, len :0x%x\n",
  204. msg->addr, msg->flags, msg->len);
  205. if (msg->flags & I2C_M_RD)
  206. ret = mtk_hdmi_ddc_read_msg(ddc, msg);
  207. else
  208. ret = mtk_hdmi_ddc_write_msg(ddc, msg);
  209. if (ret < 0)
  210. goto xfer_end;
  211. }
  212. ddcm_trigger_mode(ddc, DDCM_STOP);
  213. return i;
  214. xfer_end:
  215. ddcm_trigger_mode(ddc, DDCM_STOP);
  216. dev_err(dev, "ddc failed!\n");
  217. return ret;
  218. }
  219. static u32 mtk_hdmi_ddc_func(struct i2c_adapter *adapter)
  220. {
  221. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  222. }
  223. static const struct i2c_algorithm mtk_hdmi_ddc_algorithm = {
  224. .master_xfer = mtk_hdmi_ddc_xfer,
  225. .functionality = mtk_hdmi_ddc_func,
  226. };
  227. static int mtk_hdmi_ddc_probe(struct platform_device *pdev)
  228. {
  229. struct device *dev = &pdev->dev;
  230. struct mtk_hdmi_ddc *ddc;
  231. struct resource *mem;
  232. int ret;
  233. ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL);
  234. if (!ddc)
  235. return -ENOMEM;
  236. ddc->clk = devm_clk_get(dev, "ddc-i2c");
  237. if (IS_ERR(ddc->clk)) {
  238. dev_err(dev, "get ddc_clk failed: %p ,\n", ddc->clk);
  239. return PTR_ERR(ddc->clk);
  240. }
  241. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  242. ddc->regs = devm_ioremap_resource(&pdev->dev, mem);
  243. if (IS_ERR(ddc->regs))
  244. return PTR_ERR(ddc->regs);
  245. ret = clk_prepare_enable(ddc->clk);
  246. if (ret) {
  247. dev_err(dev, "enable ddc clk failed!\n");
  248. return ret;
  249. }
  250. strlcpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name));
  251. ddc->adap.owner = THIS_MODULE;
  252. ddc->adap.class = I2C_CLASS_DDC;
  253. ddc->adap.algo = &mtk_hdmi_ddc_algorithm;
  254. ddc->adap.retries = 3;
  255. ddc->adap.dev.of_node = dev->of_node;
  256. ddc->adap.algo_data = ddc;
  257. ddc->adap.dev.parent = &pdev->dev;
  258. ret = i2c_add_adapter(&ddc->adap);
  259. if (ret < 0) {
  260. dev_err(dev, "failed to add bus to i2c core\n");
  261. goto err_clk_disable;
  262. }
  263. platform_set_drvdata(pdev, ddc);
  264. dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap);
  265. dev_dbg(dev, "ddc->clk: %p\n", ddc->clk);
  266. dev_dbg(dev, "physical adr: %pa, end: %pa\n", &mem->start,
  267. &mem->end);
  268. return 0;
  269. err_clk_disable:
  270. clk_disable_unprepare(ddc->clk);
  271. return ret;
  272. }
  273. static int mtk_hdmi_ddc_remove(struct platform_device *pdev)
  274. {
  275. struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev);
  276. i2c_del_adapter(&ddc->adap);
  277. clk_disable_unprepare(ddc->clk);
  278. return 0;
  279. }
  280. static const struct of_device_id mtk_hdmi_ddc_match[] = {
  281. { .compatible = "mediatek,mt8173-hdmi-ddc", },
  282. {},
  283. };
  284. struct platform_driver mtk_hdmi_ddc_driver = {
  285. .probe = mtk_hdmi_ddc_probe,
  286. .remove = mtk_hdmi_ddc_remove,
  287. .driver = {
  288. .name = "mediatek-hdmi-ddc",
  289. .of_match_table = mtk_hdmi_ddc_match,
  290. },
  291. };
  292. MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
  293. MODULE_DESCRIPTION("MediaTek HDMI DDC Driver");
  294. MODULE_LICENSE("GPL v2");