mtk_drm_drv.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015 MediaTek Inc.
  4. * Author: YT SHEN <yt.shen@mediatek.com>
  5. */
  6. #include <linux/component.h>
  7. #include <linux/iommu.h>
  8. #include <linux/module.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_platform.h>
  11. #include <linux/pm_runtime.h>
  12. #include <linux/soc/mediatek/mtk-mmsys.h>
  13. #include <linux/dma-mapping.h>
  14. #include <drm/drm_atomic.h>
  15. #include <drm/drm_atomic_helper.h>
  16. #include <drm/drm_drv.h>
  17. #include <drm/drm_fb_helper.h>
  18. #include <drm/drm_fourcc.h>
  19. #include <drm/drm_gem.h>
  20. #include <drm/drm_gem_cma_helper.h>
  21. #include <drm/drm_gem_framebuffer_helper.h>
  22. #include <drm/drm_of.h>
  23. #include <drm/drm_probe_helper.h>
  24. #include <drm/drm_vblank.h>
  25. #include "mtk_drm_crtc.h"
  26. #include "mtk_drm_ddp.h"
  27. #include "mtk_drm_ddp_comp.h"
  28. #include "mtk_drm_drv.h"
  29. #include "mtk_drm_gem.h"
  30. #define DRIVER_NAME "mediatek"
  31. #define DRIVER_DESC "Mediatek SoC DRM"
  32. #define DRIVER_DATE "20150513"
  33. #define DRIVER_MAJOR 1
  34. #define DRIVER_MINOR 0
  35. static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
  36. .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
  37. };
  38. static struct drm_framebuffer *
  39. mtk_drm_mode_fb_create(struct drm_device *dev,
  40. struct drm_file *file,
  41. const struct drm_mode_fb_cmd2 *cmd)
  42. {
  43. const struct drm_format_info *info = drm_get_format_info(dev, cmd);
  44. if (info->num_planes != 1)
  45. return ERR_PTR(-EINVAL);
  46. return drm_gem_fb_create(dev, file, cmd);
  47. }
  48. static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
  49. .fb_create = mtk_drm_mode_fb_create,
  50. .atomic_check = drm_atomic_helper_check,
  51. .atomic_commit = drm_atomic_helper_commit,
  52. };
  53. static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
  54. DDP_COMPONENT_OVL0,
  55. DDP_COMPONENT_RDMA0,
  56. DDP_COMPONENT_COLOR0,
  57. DDP_COMPONENT_BLS,
  58. DDP_COMPONENT_DSI0,
  59. };
  60. static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
  61. DDP_COMPONENT_RDMA1,
  62. DDP_COMPONENT_DPI0,
  63. };
  64. static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = {
  65. DDP_COMPONENT_OVL0,
  66. DDP_COMPONENT_RDMA0,
  67. DDP_COMPONENT_COLOR0,
  68. DDP_COMPONENT_BLS,
  69. DDP_COMPONENT_DPI0,
  70. };
  71. static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = {
  72. DDP_COMPONENT_RDMA1,
  73. DDP_COMPONENT_DSI0,
  74. };
  75. static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
  76. DDP_COMPONENT_OVL0,
  77. DDP_COMPONENT_COLOR0,
  78. DDP_COMPONENT_AAL0,
  79. DDP_COMPONENT_OD0,
  80. DDP_COMPONENT_RDMA0,
  81. DDP_COMPONENT_DPI0,
  82. DDP_COMPONENT_PWM0,
  83. };
  84. static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
  85. DDP_COMPONENT_OVL1,
  86. DDP_COMPONENT_COLOR1,
  87. DDP_COMPONENT_AAL1,
  88. DDP_COMPONENT_OD1,
  89. DDP_COMPONENT_RDMA1,
  90. DDP_COMPONENT_DPI1,
  91. DDP_COMPONENT_PWM1,
  92. };
  93. static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
  94. DDP_COMPONENT_RDMA2,
  95. DDP_COMPONENT_DSI3,
  96. DDP_COMPONENT_PWM2,
  97. };
  98. static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
  99. DDP_COMPONENT_OVL0,
  100. DDP_COMPONENT_COLOR0,
  101. DDP_COMPONENT_AAL0,
  102. DDP_COMPONENT_OD0,
  103. DDP_COMPONENT_RDMA0,
  104. DDP_COMPONENT_UFOE,
  105. DDP_COMPONENT_DSI0,
  106. DDP_COMPONENT_PWM0,
  107. };
  108. static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
  109. DDP_COMPONENT_OVL1,
  110. DDP_COMPONENT_COLOR1,
  111. DDP_COMPONENT_GAMMA,
  112. DDP_COMPONENT_RDMA1,
  113. DDP_COMPONENT_DPI0,
  114. };
  115. static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
  116. .main_path = mt2701_mtk_ddp_main,
  117. .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
  118. .ext_path = mt2701_mtk_ddp_ext,
  119. .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
  120. .shadow_register = true,
  121. };
  122. static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
  123. .main_path = mt7623_mtk_ddp_main,
  124. .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
  125. .ext_path = mt7623_mtk_ddp_ext,
  126. .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
  127. .shadow_register = true,
  128. };
  129. static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
  130. .main_path = mt2712_mtk_ddp_main,
  131. .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
  132. .ext_path = mt2712_mtk_ddp_ext,
  133. .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
  134. .third_path = mt2712_mtk_ddp_third,
  135. .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
  136. };
  137. static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
  138. .main_path = mt8173_mtk_ddp_main,
  139. .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
  140. .ext_path = mt8173_mtk_ddp_ext,
  141. .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
  142. };
  143. static int mtk_drm_kms_init(struct drm_device *drm)
  144. {
  145. struct mtk_drm_private *private = drm->dev_private;
  146. struct platform_device *pdev;
  147. struct device_node *np;
  148. struct device *dma_dev;
  149. int ret;
  150. if (!iommu_present(&platform_bus_type))
  151. return -EPROBE_DEFER;
  152. pdev = of_find_device_by_node(private->mutex_node);
  153. if (!pdev) {
  154. dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
  155. private->mutex_node);
  156. of_node_put(private->mutex_node);
  157. return -EPROBE_DEFER;
  158. }
  159. private->mutex_dev = &pdev->dev;
  160. ret = drmm_mode_config_init(drm);
  161. if (ret)
  162. goto put_mutex_dev;
  163. drm->mode_config.min_width = 64;
  164. drm->mode_config.min_height = 64;
  165. /*
  166. * set max width and height as default value(4096x4096).
  167. * this value would be used to check framebuffer size limitation
  168. * at drm_mode_addfb().
  169. */
  170. drm->mode_config.max_width = 4096;
  171. drm->mode_config.max_height = 4096;
  172. drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
  173. drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
  174. ret = component_bind_all(drm->dev, drm);
  175. if (ret)
  176. goto put_mutex_dev;
  177. /*
  178. * We currently support two fixed data streams, each optional,
  179. * and each statically assigned to a crtc:
  180. * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
  181. */
  182. ret = mtk_drm_crtc_create(drm, private->data->main_path,
  183. private->data->main_len);
  184. if (ret < 0)
  185. goto err_component_unbind;
  186. /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
  187. ret = mtk_drm_crtc_create(drm, private->data->ext_path,
  188. private->data->ext_len);
  189. if (ret < 0)
  190. goto err_component_unbind;
  191. ret = mtk_drm_crtc_create(drm, private->data->third_path,
  192. private->data->third_len);
  193. if (ret < 0)
  194. goto err_component_unbind;
  195. /* Use OVL device for all DMA memory allocations */
  196. np = private->comp_node[private->data->main_path[0]] ?:
  197. private->comp_node[private->data->ext_path[0]];
  198. pdev = of_find_device_by_node(np);
  199. if (!pdev) {
  200. ret = -ENODEV;
  201. dev_err(drm->dev, "Need at least one OVL device\n");
  202. goto err_component_unbind;
  203. }
  204. dma_dev = &pdev->dev;
  205. private->dma_dev = dma_dev;
  206. /*
  207. * Configure the DMA segment size to make sure we get contiguous IOVA
  208. * when importing PRIME buffers.
  209. */
  210. if (!dma_dev->dma_parms) {
  211. private->dma_parms_allocated = true;
  212. dma_dev->dma_parms =
  213. devm_kzalloc(drm->dev, sizeof(*dma_dev->dma_parms),
  214. GFP_KERNEL);
  215. }
  216. if (!dma_dev->dma_parms) {
  217. ret = -ENOMEM;
  218. goto put_dma_dev;
  219. }
  220. ret = dma_set_max_seg_size(dma_dev, (unsigned int)DMA_BIT_MASK(32));
  221. if (ret) {
  222. dev_err(dma_dev, "Failed to set DMA segment size\n");
  223. goto err_unset_dma_parms;
  224. }
  225. /*
  226. * We don't use the drm_irq_install() helpers provided by the DRM
  227. * core, so we need to set this manually in order to allow the
  228. * DRM_IOCTL_WAIT_VBLANK to operate correctly.
  229. */
  230. drm->irq_enabled = true;
  231. ret = drm_vblank_init(drm, MAX_CRTC);
  232. if (ret < 0)
  233. goto err_unset_dma_parms;
  234. drm_kms_helper_poll_init(drm);
  235. drm_mode_config_reset(drm);
  236. return 0;
  237. err_unset_dma_parms:
  238. if (private->dma_parms_allocated)
  239. dma_dev->dma_parms = NULL;
  240. put_dma_dev:
  241. put_device(private->dma_dev);
  242. err_component_unbind:
  243. component_unbind_all(drm->dev, drm);
  244. put_mutex_dev:
  245. put_device(private->mutex_dev);
  246. return ret;
  247. }
  248. static void mtk_drm_kms_deinit(struct drm_device *drm)
  249. {
  250. struct mtk_drm_private *private = drm->dev_private;
  251. drm_kms_helper_poll_fini(drm);
  252. drm_atomic_helper_shutdown(drm);
  253. if (private->dma_parms_allocated)
  254. private->dma_dev->dma_parms = NULL;
  255. component_unbind_all(drm->dev, drm);
  256. }
  257. static const struct file_operations mtk_drm_fops = {
  258. .owner = THIS_MODULE,
  259. .open = drm_open,
  260. .release = drm_release,
  261. .unlocked_ioctl = drm_ioctl,
  262. .mmap = mtk_drm_gem_mmap,
  263. .poll = drm_poll,
  264. .read = drm_read,
  265. .compat_ioctl = drm_compat_ioctl,
  266. };
  267. /*
  268. * We need to override this because the device used to import the memory is
  269. * not dev->dev, as drm_gem_prime_import() expects.
  270. */
  271. struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev,
  272. struct dma_buf *dma_buf)
  273. {
  274. struct mtk_drm_private *private = dev->dev_private;
  275. return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
  276. }
  277. static struct drm_driver mtk_drm_driver = {
  278. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
  279. .gem_free_object_unlocked = mtk_drm_gem_free_object,
  280. .gem_vm_ops = &drm_gem_cma_vm_ops,
  281. .dumb_create = mtk_drm_gem_dumb_create,
  282. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  283. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  284. .gem_prime_import = mtk_drm_gem_prime_import,
  285. .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table,
  286. .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
  287. .gem_prime_mmap = mtk_drm_gem_mmap_buf,
  288. .gem_prime_vmap = mtk_drm_gem_prime_vmap,
  289. .gem_prime_vunmap = mtk_drm_gem_prime_vunmap,
  290. .fops = &mtk_drm_fops,
  291. .name = DRIVER_NAME,
  292. .desc = DRIVER_DESC,
  293. .date = DRIVER_DATE,
  294. .major = DRIVER_MAJOR,
  295. .minor = DRIVER_MINOR,
  296. };
  297. static int compare_of(struct device *dev, void *data)
  298. {
  299. return dev->of_node == data;
  300. }
  301. static int mtk_drm_bind(struct device *dev)
  302. {
  303. struct mtk_drm_private *private = dev_get_drvdata(dev);
  304. struct drm_device *drm;
  305. int ret;
  306. drm = drm_dev_alloc(&mtk_drm_driver, dev);
  307. if (IS_ERR(drm))
  308. return PTR_ERR(drm);
  309. drm->dev_private = private;
  310. private->drm = drm;
  311. ret = mtk_drm_kms_init(drm);
  312. if (ret < 0)
  313. goto err_free;
  314. ret = drm_dev_register(drm, 0);
  315. if (ret < 0)
  316. goto err_deinit;
  317. drm_fbdev_generic_setup(drm, 32);
  318. return 0;
  319. err_deinit:
  320. mtk_drm_kms_deinit(drm);
  321. err_free:
  322. drm_dev_put(drm);
  323. return ret;
  324. }
  325. static void mtk_drm_unbind(struct device *dev)
  326. {
  327. struct mtk_drm_private *private = dev_get_drvdata(dev);
  328. drm_dev_unregister(private->drm);
  329. mtk_drm_kms_deinit(private->drm);
  330. drm_dev_put(private->drm);
  331. private->num_pipes = 0;
  332. private->drm = NULL;
  333. }
  334. static const struct component_master_ops mtk_drm_ops = {
  335. .bind = mtk_drm_bind,
  336. .unbind = mtk_drm_unbind,
  337. };
  338. static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
  339. { .compatible = "mediatek,mt2701-disp-ovl",
  340. .data = (void *)MTK_DISP_OVL },
  341. { .compatible = "mediatek,mt8173-disp-ovl",
  342. .data = (void *)MTK_DISP_OVL },
  343. { .compatible = "mediatek,mt2701-disp-rdma",
  344. .data = (void *)MTK_DISP_RDMA },
  345. { .compatible = "mediatek,mt8173-disp-rdma",
  346. .data = (void *)MTK_DISP_RDMA },
  347. { .compatible = "mediatek,mt8173-disp-wdma",
  348. .data = (void *)MTK_DISP_WDMA },
  349. { .compatible = "mediatek,mt2701-disp-color",
  350. .data = (void *)MTK_DISP_COLOR },
  351. { .compatible = "mediatek,mt8173-disp-color",
  352. .data = (void *)MTK_DISP_COLOR },
  353. { .compatible = "mediatek,mt8173-disp-aal",
  354. .data = (void *)MTK_DISP_AAL},
  355. { .compatible = "mediatek,mt8173-disp-gamma",
  356. .data = (void *)MTK_DISP_GAMMA, },
  357. { .compatible = "mediatek,mt8173-disp-ufoe",
  358. .data = (void *)MTK_DISP_UFOE },
  359. { .compatible = "mediatek,mt2701-dsi",
  360. .data = (void *)MTK_DSI },
  361. { .compatible = "mediatek,mt8173-dsi",
  362. .data = (void *)MTK_DSI },
  363. { .compatible = "mediatek,mt2701-dpi",
  364. .data = (void *)MTK_DPI },
  365. { .compatible = "mediatek,mt8173-dpi",
  366. .data = (void *)MTK_DPI },
  367. { .compatible = "mediatek,mt2701-disp-mutex",
  368. .data = (void *)MTK_DISP_MUTEX },
  369. { .compatible = "mediatek,mt2712-disp-mutex",
  370. .data = (void *)MTK_DISP_MUTEX },
  371. { .compatible = "mediatek,mt8173-disp-mutex",
  372. .data = (void *)MTK_DISP_MUTEX },
  373. { .compatible = "mediatek,mt2701-disp-pwm",
  374. .data = (void *)MTK_DISP_BLS },
  375. { .compatible = "mediatek,mt8173-disp-pwm",
  376. .data = (void *)MTK_DISP_PWM },
  377. { .compatible = "mediatek,mt8173-disp-od",
  378. .data = (void *)MTK_DISP_OD },
  379. { }
  380. };
  381. static const struct of_device_id mtk_drm_of_ids[] = {
  382. { .compatible = "mediatek,mt2701-mmsys",
  383. .data = &mt2701_mmsys_driver_data},
  384. { .compatible = "mediatek,mt7623-mmsys",
  385. .data = &mt7623_mmsys_driver_data},
  386. { .compatible = "mediatek,mt2712-mmsys",
  387. .data = &mt2712_mmsys_driver_data},
  388. { .compatible = "mediatek,mt8173-mmsys",
  389. .data = &mt8173_mmsys_driver_data},
  390. { }
  391. };
  392. static int mtk_drm_probe(struct platform_device *pdev)
  393. {
  394. struct device *dev = &pdev->dev;
  395. struct device_node *phandle = dev->parent->of_node;
  396. const struct of_device_id *of_id;
  397. struct mtk_drm_private *private;
  398. struct device_node *node;
  399. struct component_match *match = NULL;
  400. int ret;
  401. int i;
  402. private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
  403. if (!private)
  404. return -ENOMEM;
  405. private->mmsys_dev = dev->parent;
  406. if (!private->mmsys_dev) {
  407. dev_err(dev, "Failed to get MMSYS device\n");
  408. return -ENODEV;
  409. }
  410. of_id = of_match_node(mtk_drm_of_ids, phandle);
  411. if (!of_id)
  412. return -ENODEV;
  413. private->data = of_id->data;
  414. /* Iterate over sibling DISP function blocks */
  415. for_each_child_of_node(phandle->parent, node) {
  416. const struct of_device_id *of_id;
  417. enum mtk_ddp_comp_type comp_type;
  418. int comp_id;
  419. of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
  420. if (!of_id)
  421. continue;
  422. if (!of_device_is_available(node)) {
  423. dev_dbg(dev, "Skipping disabled component %pOF\n",
  424. node);
  425. continue;
  426. }
  427. comp_type = (enum mtk_ddp_comp_type)of_id->data;
  428. if (comp_type == MTK_DISP_MUTEX) {
  429. private->mutex_node = of_node_get(node);
  430. continue;
  431. }
  432. comp_id = mtk_ddp_comp_get_id(node, comp_type);
  433. if (comp_id < 0) {
  434. dev_warn(dev, "Skipping unknown component %pOF\n",
  435. node);
  436. continue;
  437. }
  438. private->comp_node[comp_id] = of_node_get(node);
  439. /*
  440. * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have
  441. * separate component platform drivers and initialize their own
  442. * DDP component structure. The others are initialized here.
  443. */
  444. if (comp_type == MTK_DISP_COLOR ||
  445. comp_type == MTK_DISP_OVL ||
  446. comp_type == MTK_DISP_OVL_2L ||
  447. comp_type == MTK_DISP_RDMA ||
  448. comp_type == MTK_DSI ||
  449. comp_type == MTK_DPI) {
  450. dev_info(dev, "Adding component match for %pOF\n",
  451. node);
  452. drm_of_component_match_add(dev, &match, compare_of,
  453. node);
  454. } else {
  455. struct mtk_ddp_comp *comp;
  456. comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
  457. if (!comp) {
  458. ret = -ENOMEM;
  459. of_node_put(node);
  460. goto err_node;
  461. }
  462. ret = mtk_ddp_comp_init(dev->parent, node, comp,
  463. comp_id, NULL);
  464. if (ret) {
  465. of_node_put(node);
  466. goto err_node;
  467. }
  468. private->ddp_comp[comp_id] = comp;
  469. }
  470. }
  471. if (!private->mutex_node) {
  472. dev_err(dev, "Failed to find disp-mutex node\n");
  473. ret = -ENODEV;
  474. goto err_node;
  475. }
  476. pm_runtime_enable(dev);
  477. platform_set_drvdata(pdev, private);
  478. ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
  479. if (ret)
  480. goto err_pm;
  481. return 0;
  482. err_pm:
  483. pm_runtime_disable(dev);
  484. err_node:
  485. of_node_put(private->mutex_node);
  486. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) {
  487. of_node_put(private->comp_node[i]);
  488. if (private->ddp_comp[i]) {
  489. put_device(private->ddp_comp[i]->larb_dev);
  490. private->ddp_comp[i] = NULL;
  491. }
  492. }
  493. return ret;
  494. }
  495. static int mtk_drm_remove(struct platform_device *pdev)
  496. {
  497. struct mtk_drm_private *private = platform_get_drvdata(pdev);
  498. int i;
  499. component_master_del(&pdev->dev, &mtk_drm_ops);
  500. pm_runtime_disable(&pdev->dev);
  501. of_node_put(private->mutex_node);
  502. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  503. of_node_put(private->comp_node[i]);
  504. return 0;
  505. }
  506. #ifdef CONFIG_PM_SLEEP
  507. static int mtk_drm_sys_suspend(struct device *dev)
  508. {
  509. struct mtk_drm_private *private = dev_get_drvdata(dev);
  510. struct drm_device *drm = private->drm;
  511. int ret;
  512. ret = drm_mode_config_helper_suspend(drm);
  513. return ret;
  514. }
  515. static int mtk_drm_sys_resume(struct device *dev)
  516. {
  517. struct mtk_drm_private *private = dev_get_drvdata(dev);
  518. struct drm_device *drm = private->drm;
  519. int ret;
  520. ret = drm_mode_config_helper_resume(drm);
  521. return ret;
  522. }
  523. #endif
  524. static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
  525. mtk_drm_sys_resume);
  526. static struct platform_driver mtk_drm_platform_driver = {
  527. .probe = mtk_drm_probe,
  528. .remove = mtk_drm_remove,
  529. .driver = {
  530. .name = "mediatek-drm",
  531. .pm = &mtk_drm_pm_ops,
  532. },
  533. };
  534. static struct platform_driver * const mtk_drm_drivers[] = {
  535. &mtk_ddp_driver,
  536. &mtk_disp_color_driver,
  537. &mtk_disp_ovl_driver,
  538. &mtk_disp_rdma_driver,
  539. &mtk_dpi_driver,
  540. &mtk_drm_platform_driver,
  541. &mtk_mipi_tx_driver,
  542. &mtk_dsi_driver,
  543. };
  544. static int __init mtk_drm_init(void)
  545. {
  546. return platform_register_drivers(mtk_drm_drivers,
  547. ARRAY_SIZE(mtk_drm_drivers));
  548. }
  549. static void __exit mtk_drm_exit(void)
  550. {
  551. platform_unregister_drivers(mtk_drm_drivers,
  552. ARRAY_SIZE(mtk_drm_drivers));
  553. }
  554. module_init(mtk_drm_init);
  555. module_exit(mtk_drm_exit);
  556. MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
  557. MODULE_DESCRIPTION("Mediatek SoC DRM driver");
  558. MODULE_LICENSE("GPL v2");