mtk_drm_ddp_comp.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015 MediaTek Inc.
  4. * Authors:
  5. * YT Shen <yt.shen@mediatek.com>
  6. * CK Hu <ck.hu@mediatek.com>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_irq.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/soc/mediatek/mtk-cmdq.h>
  15. #include <drm/drm_print.h>
  16. #include "mtk_drm_drv.h"
  17. #include "mtk_drm_plane.h"
  18. #include "mtk_drm_ddp_comp.h"
  19. #include "mtk_drm_crtc.h"
  20. #define DISP_OD_EN 0x0000
  21. #define DISP_OD_INTEN 0x0008
  22. #define DISP_OD_INTSTA 0x000c
  23. #define DISP_OD_CFG 0x0020
  24. #define DISP_OD_SIZE 0x0030
  25. #define DISP_DITHER_5 0x0114
  26. #define DISP_DITHER_7 0x011c
  27. #define DISP_DITHER_15 0x013c
  28. #define DISP_DITHER_16 0x0140
  29. #define DISP_REG_UFO_START 0x0000
  30. #define DISP_AAL_EN 0x0000
  31. #define DISP_AAL_SIZE 0x0030
  32. #define DISP_AAL_OUTPUT_SIZE 0x04d8
  33. #define DISP_CCORR_EN 0x0000
  34. #define CCORR_EN BIT(0)
  35. #define DISP_CCORR_CFG 0x0020
  36. #define CCORR_RELAY_MODE BIT(0)
  37. #define CCORR_ENGINE_EN BIT(1)
  38. #define CCORR_GAMMA_OFF BIT(2)
  39. #define CCORR_WGAMUT_SRC_CLIP BIT(3)
  40. #define DISP_CCORR_SIZE 0x0030
  41. #define DISP_CCORR_COEF_0 0x0080
  42. #define DISP_CCORR_COEF_1 0x0084
  43. #define DISP_CCORR_COEF_2 0x0088
  44. #define DISP_CCORR_COEF_3 0x008C
  45. #define DISP_CCORR_COEF_4 0x0090
  46. #define DISP_DITHER_EN 0x0000
  47. #define DITHER_EN BIT(0)
  48. #define DISP_DITHER_CFG 0x0020
  49. #define DITHER_RELAY_MODE BIT(0)
  50. #define DISP_DITHER_SIZE 0x0030
  51. #define DISP_GAMMA_EN 0x0000
  52. #define DISP_GAMMA_CFG 0x0020
  53. #define DISP_GAMMA_SIZE 0x0030
  54. #define DISP_GAMMA_LUT 0x0700
  55. #define LUT_10BIT_MASK 0x03ff
  56. #define OD_RELAYMODE BIT(0)
  57. #define UFO_BYPASS BIT(2)
  58. #define AAL_EN BIT(0)
  59. #define GAMMA_EN BIT(0)
  60. #define GAMMA_LUT_EN BIT(1)
  61. #define DISP_DITHERING BIT(2)
  62. #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
  63. #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
  64. #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
  65. #define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16)
  66. #define DITHER_NEW_BIT_MODE BIT(0)
  67. #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
  68. #define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24)
  69. #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
  70. #define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16)
  71. #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
  72. #define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8)
  73. #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
  74. #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
  75. void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
  76. struct mtk_ddp_comp *comp, unsigned int offset)
  77. {
  78. #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  79. if (cmdq_pkt)
  80. cmdq_pkt_write(cmdq_pkt, comp->subsys,
  81. comp->regs_pa + offset, value);
  82. else
  83. #endif
  84. writel(value, comp->regs + offset);
  85. }
  86. void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
  87. struct mtk_ddp_comp *comp,
  88. unsigned int offset)
  89. {
  90. #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  91. if (cmdq_pkt)
  92. cmdq_pkt_write(cmdq_pkt, comp->subsys,
  93. comp->regs_pa + offset, value);
  94. else
  95. #endif
  96. writel_relaxed(value, comp->regs + offset);
  97. }
  98. void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt,
  99. unsigned int value,
  100. struct mtk_ddp_comp *comp,
  101. unsigned int offset,
  102. unsigned int mask)
  103. {
  104. #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  105. if (cmdq_pkt) {
  106. cmdq_pkt_write_mask(cmdq_pkt, comp->subsys,
  107. comp->regs_pa + offset, value, mask);
  108. } else {
  109. #endif
  110. u32 tmp = readl(comp->regs + offset);
  111. tmp = (tmp & ~mask) | (value & mask);
  112. writel(tmp, comp->regs + offset);
  113. #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  114. }
  115. #endif
  116. }
  117. void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
  118. unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
  119. {
  120. /* If bpc equal to 0, the dithering function didn't be enabled */
  121. if (bpc == 0)
  122. return;
  123. if (bpc >= MTK_MIN_BPC) {
  124. mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
  125. mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
  126. mtk_ddp_write(cmdq_pkt,
  127. DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
  128. DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
  129. DITHER_NEW_BIT_MODE,
  130. comp, DISP_DITHER_15);
  131. mtk_ddp_write(cmdq_pkt,
  132. DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
  133. DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
  134. DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
  135. DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
  136. comp, DISP_DITHER_16);
  137. mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
  138. }
  139. }
  140. static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
  141. unsigned int h, unsigned int vrefresh,
  142. unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
  143. {
  144. mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
  145. mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
  146. mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
  147. }
  148. static void mtk_od_start(struct mtk_ddp_comp *comp)
  149. {
  150. writel(1, comp->regs + DISP_OD_EN);
  151. }
  152. static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
  153. {
  154. writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
  155. }
  156. static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
  157. unsigned int h, unsigned int vrefresh,
  158. unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
  159. {
  160. mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
  161. mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_OUTPUT_SIZE);
  162. }
  163. static void mtk_aal_start(struct mtk_ddp_comp *comp)
  164. {
  165. writel(AAL_EN, comp->regs + DISP_AAL_EN);
  166. }
  167. static void mtk_aal_stop(struct mtk_ddp_comp *comp)
  168. {
  169. writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
  170. }
  171. static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
  172. unsigned int h, unsigned int vrefresh,
  173. unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
  174. {
  175. mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
  176. mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
  177. }
  178. static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
  179. {
  180. writel(CCORR_EN, comp->regs + DISP_CCORR_EN);
  181. }
  182. static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
  183. {
  184. writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
  185. }
  186. /* Converts a DRM S31.32 value to the HW S1.10 format. */
  187. static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
  188. {
  189. u16 r;
  190. /* Sign bit. */
  191. r = in & BIT_ULL(63) ? BIT(11) : 0;
  192. if ((in & GENMASK_ULL(62, 33)) > 0) {
  193. /* identity value 0x100000000 -> 0x400, */
  194. /* if bigger this, set it to max 0x7ff. */
  195. r |= GENMASK(10, 0);
  196. } else {
  197. /* take the 11 most important bits. */
  198. r |= (in >> 22) & GENMASK(10, 0);
  199. }
  200. return r;
  201. }
  202. static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
  203. struct drm_crtc_state *state)
  204. {
  205. struct drm_property_blob *blob = state->ctm;
  206. struct drm_color_ctm *ctm;
  207. const u64 *input;
  208. uint16_t coeffs[9] = { 0 };
  209. int i;
  210. struct cmdq_pkt *cmdq_pkt = NULL;
  211. if (!blob)
  212. return;
  213. ctm = (struct drm_color_ctm *)blob->data;
  214. input = ctm->matrix;
  215. for (i = 0; i < ARRAY_SIZE(coeffs); i++)
  216. coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
  217. mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
  218. comp, DISP_CCORR_COEF_0);
  219. mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
  220. comp, DISP_CCORR_COEF_1);
  221. mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
  222. comp, DISP_CCORR_COEF_2);
  223. mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
  224. comp, DISP_CCORR_COEF_3);
  225. mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
  226. comp, DISP_CCORR_COEF_4);
  227. }
  228. static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
  229. unsigned int h, unsigned int vrefresh,
  230. unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
  231. {
  232. mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE);
  233. mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG);
  234. }
  235. static void mtk_dither_start(struct mtk_ddp_comp *comp)
  236. {
  237. writel(DITHER_EN, comp->regs + DISP_DITHER_EN);
  238. }
  239. static void mtk_dither_stop(struct mtk_ddp_comp *comp)
  240. {
  241. writel_relaxed(0x0, comp->regs + DISP_DITHER_EN);
  242. }
  243. static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
  244. unsigned int h, unsigned int vrefresh,
  245. unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
  246. {
  247. mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
  248. mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
  249. }
  250. static void mtk_gamma_start(struct mtk_ddp_comp *comp)
  251. {
  252. writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN);
  253. }
  254. static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
  255. {
  256. writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN);
  257. }
  258. static void mtk_gamma_set(struct mtk_ddp_comp *comp,
  259. struct drm_crtc_state *state)
  260. {
  261. unsigned int i, reg;
  262. struct drm_color_lut *lut;
  263. void __iomem *lut_base;
  264. u32 word;
  265. if (state->gamma_lut) {
  266. reg = readl(comp->regs + DISP_GAMMA_CFG);
  267. reg = reg | GAMMA_LUT_EN;
  268. writel(reg, comp->regs + DISP_GAMMA_CFG);
  269. lut_base = comp->regs + DISP_GAMMA_LUT;
  270. lut = (struct drm_color_lut *)state->gamma_lut->data;
  271. for (i = 0; i < MTK_LUT_SIZE; i++) {
  272. word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
  273. (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
  274. ((lut[i].blue >> 6) & LUT_10BIT_MASK);
  275. writel(word, (lut_base + i * 4));
  276. }
  277. }
  278. }
  279. static const struct mtk_ddp_comp_funcs ddp_aal = {
  280. .gamma_set = mtk_gamma_set,
  281. .config = mtk_aal_config,
  282. .start = mtk_aal_start,
  283. .stop = mtk_aal_stop,
  284. };
  285. static const struct mtk_ddp_comp_funcs ddp_ccorr = {
  286. .config = mtk_ccorr_config,
  287. .start = mtk_ccorr_start,
  288. .stop = mtk_ccorr_stop,
  289. .ctm_set = mtk_ccorr_ctm_set,
  290. };
  291. static const struct mtk_ddp_comp_funcs ddp_dither = {
  292. .config = mtk_dither_config,
  293. .start = mtk_dither_start,
  294. .stop = mtk_dither_stop,
  295. };
  296. static const struct mtk_ddp_comp_funcs ddp_gamma = {
  297. .gamma_set = mtk_gamma_set,
  298. .config = mtk_gamma_config,
  299. .start = mtk_gamma_start,
  300. .stop = mtk_gamma_stop,
  301. };
  302. static const struct mtk_ddp_comp_funcs ddp_od = {
  303. .config = mtk_od_config,
  304. .start = mtk_od_start,
  305. };
  306. static const struct mtk_ddp_comp_funcs ddp_ufoe = {
  307. .start = mtk_ufoe_start,
  308. };
  309. static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
  310. [MTK_DISP_OVL] = "ovl",
  311. [MTK_DISP_OVL_2L] = "ovl-2l",
  312. [MTK_DISP_RDMA] = "rdma",
  313. [MTK_DISP_WDMA] = "wdma",
  314. [MTK_DISP_COLOR] = "color",
  315. [MTK_DISP_CCORR] = "ccorr",
  316. [MTK_DISP_AAL] = "aal",
  317. [MTK_DISP_GAMMA] = "gamma",
  318. [MTK_DISP_DITHER] = "dither",
  319. [MTK_DISP_UFOE] = "ufoe",
  320. [MTK_DSI] = "dsi",
  321. [MTK_DPI] = "dpi",
  322. [MTK_DISP_PWM] = "pwm",
  323. [MTK_DISP_MUTEX] = "mutex",
  324. [MTK_DISP_OD] = "od",
  325. [MTK_DISP_BLS] = "bls",
  326. };
  327. struct mtk_ddp_comp_match {
  328. enum mtk_ddp_comp_type type;
  329. int alias_id;
  330. const struct mtk_ddp_comp_funcs *funcs;
  331. };
  332. static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
  333. [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
  334. [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
  335. [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
  336. [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
  337. [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
  338. [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
  339. [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
  340. [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
  341. [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL },
  342. [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
  343. [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
  344. [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL },
  345. [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL },
  346. [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
  347. [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
  348. [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
  349. [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
  350. [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
  351. [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL },
  352. [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL },
  353. [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
  354. [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
  355. [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
  356. [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
  357. [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
  358. [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
  359. [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
  360. [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
  361. [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
  362. };
  363. static bool mtk_drm_find_comp_in_ddp(struct mtk_ddp_comp ddp_comp,
  364. const enum mtk_ddp_comp_id *path,
  365. unsigned int path_len)
  366. {
  367. unsigned int i;
  368. if (path == NULL)
  369. return false;
  370. for (i = 0U; i < path_len; i++)
  371. if (ddp_comp.id == path[i])
  372. return true;
  373. return false;
  374. }
  375. int mtk_ddp_comp_get_id(struct device_node *node,
  376. enum mtk_ddp_comp_type comp_type)
  377. {
  378. int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
  379. int i;
  380. for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
  381. if (comp_type == mtk_ddp_matches[i].type &&
  382. (id < 0 || id == mtk_ddp_matches[i].alias_id))
  383. return i;
  384. }
  385. return -EINVAL;
  386. }
  387. unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
  388. struct mtk_ddp_comp ddp_comp)
  389. {
  390. struct mtk_drm_private *private = drm->dev_private;
  391. unsigned int ret = 0;
  392. if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->main_path, private->data->main_len))
  393. ret = BIT(0);
  394. else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->ext_path,
  395. private->data->ext_len))
  396. ret = BIT(1);
  397. else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->third_path,
  398. private->data->third_len))
  399. ret = BIT(2);
  400. else
  401. DRM_INFO("Failed to find comp in ddp table\n");
  402. return ret;
  403. }
  404. int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
  405. struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
  406. const struct mtk_ddp_comp_funcs *funcs)
  407. {
  408. enum mtk_ddp_comp_type type;
  409. struct device_node *larb_node;
  410. struct platform_device *larb_pdev;
  411. #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  412. struct resource res;
  413. struct cmdq_client_reg cmdq_reg;
  414. int ret;
  415. #endif
  416. if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
  417. return -EINVAL;
  418. type = mtk_ddp_matches[comp_id].type;
  419. comp->id = comp_id;
  420. comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;
  421. if (comp_id == DDP_COMPONENT_BLS ||
  422. comp_id == DDP_COMPONENT_DPI0 ||
  423. comp_id == DDP_COMPONENT_DPI1 ||
  424. comp_id == DDP_COMPONENT_DSI0 ||
  425. comp_id == DDP_COMPONENT_DSI1 ||
  426. comp_id == DDP_COMPONENT_DSI2 ||
  427. comp_id == DDP_COMPONENT_DSI3 ||
  428. comp_id == DDP_COMPONENT_PWM0) {
  429. comp->regs = NULL;
  430. comp->clk = NULL;
  431. comp->irq = 0;
  432. return 0;
  433. }
  434. comp->regs = of_iomap(node, 0);
  435. comp->irq = of_irq_get(node, 0);
  436. comp->clk = of_clk_get(node, 0);
  437. if (IS_ERR(comp->clk))
  438. return PTR_ERR(comp->clk);
  439. /* Only DMA capable components need the LARB property */
  440. comp->larb_dev = NULL;
  441. if (type != MTK_DISP_OVL &&
  442. type != MTK_DISP_OVL_2L &&
  443. type != MTK_DISP_RDMA &&
  444. type != MTK_DISP_WDMA)
  445. return 0;
  446. larb_node = of_parse_phandle(node, "mediatek,larb", 0);
  447. if (!larb_node) {
  448. dev_err(dev,
  449. "Missing mediadek,larb phandle in %pOF node\n", node);
  450. return -EINVAL;
  451. }
  452. larb_pdev = of_find_device_by_node(larb_node);
  453. if (!larb_pdev) {
  454. dev_warn(dev, "Waiting for larb device %pOF\n", larb_node);
  455. of_node_put(larb_node);
  456. return -EPROBE_DEFER;
  457. }
  458. of_node_put(larb_node);
  459. comp->larb_dev = &larb_pdev->dev;
  460. #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  461. if (of_address_to_resource(node, 0, &res) != 0) {
  462. dev_err(dev, "Missing reg in %s node\n", node->full_name);
  463. put_device(&larb_pdev->dev);
  464. return -EINVAL;
  465. }
  466. comp->regs_pa = res.start;
  467. ret = cmdq_dev_get_client_reg(dev, &cmdq_reg, 0);
  468. if (ret)
  469. dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
  470. else
  471. comp->subsys = cmdq_reg.subsys;
  472. #endif
  473. return 0;
  474. }
  475. int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp)
  476. {
  477. struct mtk_drm_private *private = drm->dev_private;
  478. if (private->ddp_comp[comp->id])
  479. return -EBUSY;
  480. private->ddp_comp[comp->id] = comp;
  481. return 0;
  482. }
  483. void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp)
  484. {
  485. struct mtk_drm_private *private = drm->dev_private;
  486. private->ddp_comp[comp->id] = NULL;
  487. }