ingenic-ipu.h 4.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. //
  3. // Ingenic JZ47xx IPU - Register definitions and private API
  4. //
  5. // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
  6. #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H
  7. #define DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H
  8. #include <linux/bitops.h>
  9. #define JZ_REG_IPU_CTRL 0x00
  10. #define JZ_REG_IPU_STATUS 0x04
  11. #define JZ_REG_IPU_D_FMT 0x08
  12. #define JZ_REG_IPU_Y_ADDR 0x0c
  13. #define JZ_REG_IPU_U_ADDR 0x10
  14. #define JZ_REG_IPU_V_ADDR 0x14
  15. #define JZ_REG_IPU_IN_GS 0x18
  16. #define JZ_REG_IPU_Y_STRIDE 0x1c
  17. #define JZ_REG_IPU_UV_STRIDE 0x20
  18. #define JZ_REG_IPU_OUT_ADDR 0x24
  19. #define JZ_REG_IPU_OUT_GS 0x28
  20. #define JZ_REG_IPU_OUT_STRIDE 0x2c
  21. #define JZ_REG_IPU_RSZ_COEF_INDEX 0x30
  22. #define JZ_REG_IPU_CSC_C0_COEF 0x34
  23. #define JZ_REG_IPU_CSC_C1_COEF 0x38
  24. #define JZ_REG_IPU_CSC_C2_COEF 0x3c
  25. #define JZ_REG_IPU_CSC_C3_COEF 0x40
  26. #define JZ_REG_IPU_CSC_C4_COEF 0x44
  27. #define JZ_REG_IPU_HRSZ_COEF_LUT 0x48
  28. #define JZ_REG_IPU_VRSZ_COEF_LUT 0x4c
  29. #define JZ_REG_IPU_CSC_OFFSET 0x50
  30. #define JZ_REG_IPU_Y_PHY_T_ADDR 0x54
  31. #define JZ_REG_IPU_U_PHY_T_ADDR 0x58
  32. #define JZ_REG_IPU_V_PHY_T_ADDR 0x5c
  33. #define JZ_REG_IPU_OUT_PHY_T_ADDR 0x60
  34. #define JZ_IPU_CTRL_ADDR_SEL BIT(20)
  35. #define JZ_IPU_CTRL_ZOOM_SEL BIT(18)
  36. #define JZ_IPU_CTRL_DFIX_SEL BIT(17)
  37. #define JZ_IPU_CTRL_LCDC_SEL BIT(11)
  38. #define JZ_IPU_CTRL_SPKG_SEL BIT(10)
  39. #define JZ_IPU_CTRL_VSCALE BIT(9)
  40. #define JZ_IPU_CTRL_HSCALE BIT(8)
  41. #define JZ_IPU_CTRL_STOP BIT(7)
  42. #define JZ_IPU_CTRL_RST BIT(6)
  43. #define JZ_IPU_CTRL_FM_IRQ_EN BIT(5)
  44. #define JZ_IPU_CTRL_CSC_EN BIT(4)
  45. #define JZ_IPU_CTRL_VRSZ_EN BIT(3)
  46. #define JZ_IPU_CTRL_HRSZ_EN BIT(2)
  47. #define JZ_IPU_CTRL_RUN BIT(1)
  48. #define JZ_IPU_CTRL_CHIP_EN BIT(0)
  49. #define JZ_IPU_STATUS_OUT_END BIT(0)
  50. #define JZ_IPU_IN_GS_H_LSB 0x0
  51. #define JZ_IPU_IN_GS_W_LSB 0x10
  52. #define JZ_IPU_OUT_GS_H_LSB 0x0
  53. #define JZ_IPU_OUT_GS_W_LSB 0x10
  54. #define JZ_IPU_Y_STRIDE_Y_LSB 0
  55. #define JZ_IPU_UV_STRIDE_U_LSB 16
  56. #define JZ_IPU_UV_STRIDE_V_LSB 0
  57. #define JZ_IPU_D_FMT_IN_FMT_LSB 0
  58. #define JZ_IPU_D_FMT_IN_FMT_RGB555 (0x0 << JZ_IPU_D_FMT_IN_FMT_LSB)
  59. #define JZ_IPU_D_FMT_IN_FMT_YUV420 (0x0 << JZ_IPU_D_FMT_IN_FMT_LSB)
  60. #define JZ_IPU_D_FMT_IN_FMT_YUV422 (0x1 << JZ_IPU_D_FMT_IN_FMT_LSB)
  61. #define JZ_IPU_D_FMT_IN_FMT_RGB888 (0x2 << JZ_IPU_D_FMT_IN_FMT_LSB)
  62. #define JZ_IPU_D_FMT_IN_FMT_YUV444 (0x2 << JZ_IPU_D_FMT_IN_FMT_LSB)
  63. #define JZ_IPU_D_FMT_IN_FMT_RGB565 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
  64. #define JZ_IPU_D_FMT_YUV_FMT_LSB 2
  65. #define JZ_IPU_D_FMT_YUV_Y1UY0V (0x0 << JZ_IPU_D_FMT_YUV_FMT_LSB)
  66. #define JZ_IPU_D_FMT_YUV_Y1VY0U (0x1 << JZ_IPU_D_FMT_YUV_FMT_LSB)
  67. #define JZ_IPU_D_FMT_YUV_UY1VY0 (0x2 << JZ_IPU_D_FMT_YUV_FMT_LSB)
  68. #define JZ_IPU_D_FMT_YUV_VY1UY0 (0x3 << JZ_IPU_D_FMT_YUV_FMT_LSB)
  69. #define JZ_IPU_D_FMT_IN_FMT_YUV411 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
  70. #define JZ_IPU_D_FMT_OUT_FMT_LSB 19
  71. #define JZ_IPU_D_FMT_OUT_FMT_RGB555 (0x0 << JZ_IPU_D_FMT_OUT_FMT_LSB)
  72. #define JZ_IPU_D_FMT_OUT_FMT_RGB565 (0x1 << JZ_IPU_D_FMT_OUT_FMT_LSB)
  73. #define JZ_IPU_D_FMT_OUT_FMT_RGB888 (0x2 << JZ_IPU_D_FMT_OUT_FMT_LSB)
  74. #define JZ_IPU_D_FMT_OUT_FMT_YUV422 (0x3 << JZ_IPU_D_FMT_OUT_FMT_LSB)
  75. #define JZ_IPU_D_FMT_OUT_FMT_RGBAAA (0x4 << JZ_IPU_D_FMT_OUT_FMT_LSB)
  76. #define JZ_IPU_D_FMT_RGB_OUT_OFT_LSB 22
  77. #define JZ_IPU_D_FMT_RGB_OUT_OFT_RGB (0x0 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
  78. #define JZ_IPU_D_FMT_RGB_OUT_OFT_RBG (0x1 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
  79. #define JZ_IPU_D_FMT_RGB_OUT_OFT_GBR (0x2 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
  80. #define JZ_IPU_D_FMT_RGB_OUT_OFT_GRB (0x3 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
  81. #define JZ_IPU_D_FMT_RGB_OUT_OFT_BRG (0x4 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
  82. #define JZ_IPU_D_FMT_RGB_OUT_OFT_BGR (0x5 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
  83. #define JZ4725B_IPU_RSZ_LUT_COEF_LSB 2
  84. #define JZ4725B_IPU_RSZ_LUT_COEF_MASK 0x7ff
  85. #define JZ4725B_IPU_RSZ_LUT_IN_EN BIT(1)
  86. #define JZ4725B_IPU_RSZ_LUT_OUT_EN BIT(0)
  87. #define JZ4760_IPU_RSZ_COEF20_LSB 6
  88. #define JZ4760_IPU_RSZ_COEF31_LSB 17
  89. #define JZ4760_IPU_RSZ_COEF_MASK 0x7ff
  90. #define JZ4760_IPU_RSZ_OFFSET_LSB 1
  91. #define JZ4760_IPU_RSZ_OFFSET_MASK 0x1f
  92. #define JZ_IPU_CSC_OFFSET_CHROMA_LSB 16
  93. #define JZ_IPU_CSC_OFFSET_LUMA_LSB 16
  94. #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H */