ingenic-drm.h 5.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. //
  3. // Ingenic JZ47xx KMS driver - Register definitions and private API
  4. //
  5. // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
  6. #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
  7. #define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
  8. #include <linux/bitops.h>
  9. #include <linux/types.h>
  10. #define JZ_REG_LCD_CFG 0x00
  11. #define JZ_REG_LCD_VSYNC 0x04
  12. #define JZ_REG_LCD_HSYNC 0x08
  13. #define JZ_REG_LCD_VAT 0x0C
  14. #define JZ_REG_LCD_DAH 0x10
  15. #define JZ_REG_LCD_DAV 0x14
  16. #define JZ_REG_LCD_PS 0x18
  17. #define JZ_REG_LCD_CLS 0x1C
  18. #define JZ_REG_LCD_SPL 0x20
  19. #define JZ_REG_LCD_REV 0x24
  20. #define JZ_REG_LCD_CTRL 0x30
  21. #define JZ_REG_LCD_STATE 0x34
  22. #define JZ_REG_LCD_IID 0x38
  23. #define JZ_REG_LCD_DA0 0x40
  24. #define JZ_REG_LCD_SA0 0x44
  25. #define JZ_REG_LCD_FID0 0x48
  26. #define JZ_REG_LCD_CMD0 0x4C
  27. #define JZ_REG_LCD_DA1 0x50
  28. #define JZ_REG_LCD_SA1 0x54
  29. #define JZ_REG_LCD_FID1 0x58
  30. #define JZ_REG_LCD_CMD1 0x5C
  31. #define JZ_REG_LCD_OSDC 0x100
  32. #define JZ_REG_LCD_OSDCTRL 0x104
  33. #define JZ_REG_LCD_OSDS 0x108
  34. #define JZ_REG_LCD_BGC 0x10c
  35. #define JZ_REG_LCD_KEY0 0x110
  36. #define JZ_REG_LCD_KEY1 0x114
  37. #define JZ_REG_LCD_ALPHA 0x118
  38. #define JZ_REG_LCD_IPUR 0x11c
  39. #define JZ_REG_LCD_XYP0 0x120
  40. #define JZ_REG_LCD_XYP1 0x124
  41. #define JZ_REG_LCD_SIZE0 0x128
  42. #define JZ_REG_LCD_SIZE1 0x12c
  43. #define JZ_LCD_CFG_SLCD BIT(31)
  44. #define JZ_LCD_CFG_PS_DISABLE BIT(23)
  45. #define JZ_LCD_CFG_CLS_DISABLE BIT(22)
  46. #define JZ_LCD_CFG_SPL_DISABLE BIT(21)
  47. #define JZ_LCD_CFG_REV_DISABLE BIT(20)
  48. #define JZ_LCD_CFG_HSYNCM BIT(19)
  49. #define JZ_LCD_CFG_PCLKM BIT(18)
  50. #define JZ_LCD_CFG_INV BIT(17)
  51. #define JZ_LCD_CFG_SYNC_DIR BIT(16)
  52. #define JZ_LCD_CFG_PS_POLARITY BIT(15)
  53. #define JZ_LCD_CFG_CLS_POLARITY BIT(14)
  54. #define JZ_LCD_CFG_SPL_POLARITY BIT(13)
  55. #define JZ_LCD_CFG_REV_POLARITY BIT(12)
  56. #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
  57. #define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
  58. #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
  59. #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
  60. #define JZ_LCD_CFG_18_BIT BIT(7)
  61. #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
  62. #define JZ_LCD_CFG_MODE_GENERIC_16BIT 0
  63. #define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7)
  64. #define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6)
  65. #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1
  66. #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2
  67. #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3
  68. #define JZ_LCD_CFG_MODE_TV_OUT_P 4
  69. #define JZ_LCD_CFG_MODE_TV_OUT_I 6
  70. #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8
  71. #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9
  72. #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10
  73. #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11
  74. #define JZ_LCD_CFG_MODE_8BIT_SERIAL 12
  75. #define JZ_LCD_CFG_MODE_LCM 13
  76. #define JZ_LCD_VSYNC_VPS_OFFSET 16
  77. #define JZ_LCD_VSYNC_VPE_OFFSET 0
  78. #define JZ_LCD_HSYNC_HPS_OFFSET 16
  79. #define JZ_LCD_HSYNC_HPE_OFFSET 0
  80. #define JZ_LCD_VAT_HT_OFFSET 16
  81. #define JZ_LCD_VAT_VT_OFFSET 0
  82. #define JZ_LCD_DAH_HDS_OFFSET 16
  83. #define JZ_LCD_DAH_HDE_OFFSET 0
  84. #define JZ_LCD_DAV_VDS_OFFSET 16
  85. #define JZ_LCD_DAV_VDE_OFFSET 0
  86. #define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
  87. #define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
  88. #define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
  89. #define JZ_LCD_CTRL_RGB555 BIT(27)
  90. #define JZ_LCD_CTRL_OFUP BIT(26)
  91. #define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
  92. #define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
  93. #define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
  94. #define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
  95. #define JZ_LCD_CTRL_EOF_IRQ BIT(13)
  96. #define JZ_LCD_CTRL_SOF_IRQ BIT(12)
  97. #define JZ_LCD_CTRL_OFU_IRQ BIT(11)
  98. #define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
  99. #define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
  100. #define JZ_LCD_CTRL_DD_IRQ BIT(8)
  101. #define JZ_LCD_CTRL_QDD_IRQ BIT(7)
  102. #define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
  103. #define JZ_LCD_CTRL_LSB_FISRT BIT(5)
  104. #define JZ_LCD_CTRL_DISABLE BIT(4)
  105. #define JZ_LCD_CTRL_ENABLE BIT(3)
  106. #define JZ_LCD_CTRL_BPP_1 0x0
  107. #define JZ_LCD_CTRL_BPP_2 0x1
  108. #define JZ_LCD_CTRL_BPP_4 0x2
  109. #define JZ_LCD_CTRL_BPP_8 0x3
  110. #define JZ_LCD_CTRL_BPP_15_16 0x4
  111. #define JZ_LCD_CTRL_BPP_18_24 0x5
  112. #define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7)
  113. #define JZ_LCD_CMD_SOF_IRQ BIT(31)
  114. #define JZ_LCD_CMD_EOF_IRQ BIT(30)
  115. #define JZ_LCD_CMD_ENABLE_PAL BIT(28)
  116. #define JZ_LCD_SYNC_MASK 0x3ff
  117. #define JZ_LCD_STATE_EOF_IRQ BIT(5)
  118. #define JZ_LCD_STATE_SOF_IRQ BIT(4)
  119. #define JZ_LCD_STATE_DISABLED BIT(0)
  120. #define JZ_LCD_OSDC_OSDEN BIT(0)
  121. #define JZ_LCD_OSDC_F0EN BIT(3)
  122. #define JZ_LCD_OSDC_F1EN BIT(4)
  123. #define JZ_LCD_OSDCTRL_IPU BIT(15)
  124. #define JZ_LCD_OSDCTRL_RGB555 BIT(4)
  125. #define JZ_LCD_OSDCTRL_CHANGE BIT(3)
  126. #define JZ_LCD_OSDCTRL_BPP_15_16 0x4
  127. #define JZ_LCD_OSDCTRL_BPP_18_24 0x5
  128. #define JZ_LCD_OSDCTRL_BPP_30 0x7
  129. #define JZ_LCD_OSDCTRL_BPP_MASK (JZ_LCD_OSDCTRL_RGB555 | 0x7)
  130. #define JZ_LCD_OSDS_READY BIT(0)
  131. #define JZ_LCD_IPUR_IPUREN BIT(31)
  132. #define JZ_LCD_IPUR_IPUR_LSB 0
  133. #define JZ_LCD_XYP01_XPOS_LSB 0
  134. #define JZ_LCD_XYP01_YPOS_LSB 16
  135. #define JZ_LCD_SIZE01_WIDTH_LSB 0
  136. #define JZ_LCD_SIZE01_HEIGHT_LSB 16
  137. struct device;
  138. struct drm_plane;
  139. struct drm_plane_state;
  140. struct platform_driver;
  141. void ingenic_drm_plane_config(struct device *dev,
  142. struct drm_plane *plane, u32 fourcc);
  143. void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane);
  144. extern struct platform_driver *ingenic_ipu_driver_ptr;
  145. #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */