psb_intel_sdvo_regs.h 24 KB

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  1. /*
  2. * Copyright ? 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. /**
  27. * @file SDVO command definitions and structures.
  28. */
  29. #define SDVO_OUTPUT_FIRST (0)
  30. #define SDVO_OUTPUT_TMDS0 (1 << 0)
  31. #define SDVO_OUTPUT_RGB0 (1 << 1)
  32. #define SDVO_OUTPUT_CVBS0 (1 << 2)
  33. #define SDVO_OUTPUT_SVID0 (1 << 3)
  34. #define SDVO_OUTPUT_YPRPB0 (1 << 4)
  35. #define SDVO_OUTPUT_SCART0 (1 << 5)
  36. #define SDVO_OUTPUT_LVDS0 (1 << 6)
  37. #define SDVO_OUTPUT_TMDS1 (1 << 8)
  38. #define SDVO_OUTPUT_RGB1 (1 << 9)
  39. #define SDVO_OUTPUT_CVBS1 (1 << 10)
  40. #define SDVO_OUTPUT_SVID1 (1 << 11)
  41. #define SDVO_OUTPUT_YPRPB1 (1 << 12)
  42. #define SDVO_OUTPUT_SCART1 (1 << 13)
  43. #define SDVO_OUTPUT_LVDS1 (1 << 14)
  44. #define SDVO_OUTPUT_LAST (14)
  45. struct psb_intel_sdvo_caps {
  46. u8 vendor_id;
  47. u8 device_id;
  48. u8 device_rev_id;
  49. u8 sdvo_version_major;
  50. u8 sdvo_version_minor;
  51. unsigned int sdvo_inputs_mask:2;
  52. unsigned int smooth_scaling:1;
  53. unsigned int sharp_scaling:1;
  54. unsigned int up_scaling:1;
  55. unsigned int down_scaling:1;
  56. unsigned int stall_support:1;
  57. unsigned int pad:1;
  58. u16 output_flags;
  59. } __attribute__((packed));
  60. /** This matches the EDID DTD structure, more or less */
  61. struct psb_intel_sdvo_dtd {
  62. struct {
  63. u16 clock; /**< pixel clock, in 10kHz units */
  64. u8 h_active; /**< lower 8 bits (pixels) */
  65. u8 h_blank; /**< lower 8 bits (pixels) */
  66. u8 h_high; /**< upper 4 bits each h_active, h_blank */
  67. u8 v_active; /**< lower 8 bits (lines) */
  68. u8 v_blank; /**< lower 8 bits (lines) */
  69. u8 v_high; /**< upper 4 bits each v_active, v_blank */
  70. } part1;
  71. struct {
  72. u8 h_sync_off; /**< lower 8 bits, from hblank start */
  73. u8 h_sync_width; /**< lower 8 bits (pixels) */
  74. /** lower 4 bits each vsync offset, vsync width */
  75. u8 v_sync_off_width;
  76. /**
  77. * 2 high bits of hsync offset, 2 high bits of hsync width,
  78. * bits 4-5 of vsync offset, and 2 high bits of vsync width.
  79. */
  80. u8 sync_off_width_high;
  81. u8 dtd_flags;
  82. u8 sdvo_flags;
  83. /** bits 6-7 of vsync offset at bits 6-7 */
  84. u8 v_sync_off_high;
  85. u8 reserved;
  86. } part2;
  87. } __attribute__((packed));
  88. struct psb_intel_sdvo_pixel_clock_range {
  89. u16 min; /**< pixel clock, in 10kHz units */
  90. u16 max; /**< pixel clock, in 10kHz units */
  91. } __attribute__((packed));
  92. struct psb_intel_sdvo_preferred_input_timing_args {
  93. u16 clock;
  94. u16 width;
  95. u16 height;
  96. u8 interlace:1;
  97. u8 scaled:1;
  98. u8 pad:6;
  99. } __attribute__((packed));
  100. /* I2C registers for SDVO */
  101. #define SDVO_I2C_ARG_0 0x07
  102. #define SDVO_I2C_ARG_1 0x06
  103. #define SDVO_I2C_ARG_2 0x05
  104. #define SDVO_I2C_ARG_3 0x04
  105. #define SDVO_I2C_ARG_4 0x03
  106. #define SDVO_I2C_ARG_5 0x02
  107. #define SDVO_I2C_ARG_6 0x01
  108. #define SDVO_I2C_ARG_7 0x00
  109. #define SDVO_I2C_OPCODE 0x08
  110. #define SDVO_I2C_CMD_STATUS 0x09
  111. #define SDVO_I2C_RETURN_0 0x0a
  112. #define SDVO_I2C_RETURN_1 0x0b
  113. #define SDVO_I2C_RETURN_2 0x0c
  114. #define SDVO_I2C_RETURN_3 0x0d
  115. #define SDVO_I2C_RETURN_4 0x0e
  116. #define SDVO_I2C_RETURN_5 0x0f
  117. #define SDVO_I2C_RETURN_6 0x10
  118. #define SDVO_I2C_RETURN_7 0x11
  119. #define SDVO_I2C_VENDOR_BEGIN 0x20
  120. /* Status results */
  121. #define SDVO_CMD_STATUS_POWER_ON 0x0
  122. #define SDVO_CMD_STATUS_SUCCESS 0x1
  123. #define SDVO_CMD_STATUS_NOTSUPP 0x2
  124. #define SDVO_CMD_STATUS_INVALID_ARG 0x3
  125. #define SDVO_CMD_STATUS_PENDING 0x4
  126. #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5
  127. #define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6
  128. /* SDVO commands, argument/result registers */
  129. #define SDVO_CMD_RESET 0x01
  130. /** Returns a struct intel_sdvo_caps */
  131. #define SDVO_CMD_GET_DEVICE_CAPS 0x02
  132. #define SDVO_CMD_GET_FIRMWARE_REV 0x86
  133. # define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0
  134. # define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1
  135. # define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2
  136. /**
  137. * Reports which inputs are trained (managed to sync).
  138. *
  139. * Devices must have trained within 2 vsyncs of a mode change.
  140. */
  141. #define SDVO_CMD_GET_TRAINED_INPUTS 0x03
  142. struct psb_intel_sdvo_get_trained_inputs_response {
  143. unsigned int input0_trained:1;
  144. unsigned int input1_trained:1;
  145. unsigned int pad:6;
  146. } __attribute__((packed));
  147. /** Returns a struct intel_sdvo_output_flags of active outputs. */
  148. #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
  149. /**
  150. * Sets the current set of active outputs.
  151. *
  152. * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP
  153. * on multi-output devices.
  154. */
  155. #define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05
  156. /**
  157. * Returns the current mapping of SDVO inputs to outputs on the device.
  158. *
  159. * Returns two struct intel_sdvo_output_flags structures.
  160. */
  161. #define SDVO_CMD_GET_IN_OUT_MAP 0x06
  162. struct psb_intel_sdvo_in_out_map {
  163. u16 in0, in1;
  164. };
  165. /**
  166. * Sets the current mapping of SDVO inputs to outputs on the device.
  167. *
  168. * Takes two struct i380_sdvo_output_flags structures.
  169. */
  170. #define SDVO_CMD_SET_IN_OUT_MAP 0x07
  171. /**
  172. * Returns a struct intel_sdvo_output_flags of attached displays.
  173. */
  174. #define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b
  175. /**
  176. * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.
  177. */
  178. #define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c
  179. /**
  180. * Takes a struct intel_sdvo_output_flags.
  181. */
  182. #define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d
  183. /**
  184. * Returns a struct intel_sdvo_output_flags of displays with hot plug
  185. * interrupts enabled.
  186. */
  187. #define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e
  188. #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
  189. struct intel_sdvo_get_interrupt_event_source_response {
  190. u16 interrupt_status;
  191. unsigned int ambient_light_interrupt:1;
  192. unsigned int hdmi_audio_encrypt_change:1;
  193. unsigned int pad:6;
  194. } __attribute__((packed));
  195. /**
  196. * Selects which input is affected by future input commands.
  197. *
  198. * Commands affected include SET_INPUT_TIMINGS_PART[12],
  199. * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
  200. * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
  201. */
  202. #define SDVO_CMD_SET_TARGET_INPUT 0x10
  203. struct psb_intel_sdvo_set_target_input_args {
  204. unsigned int target_1:1;
  205. unsigned int pad:7;
  206. } __attribute__((packed));
  207. /**
  208. * Takes a struct intel_sdvo_output_flags of which outputs are targeted by
  209. * future output commands.
  210. *
  211. * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
  212. * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
  213. */
  214. #define SDVO_CMD_SET_TARGET_OUTPUT 0x11
  215. #define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12
  216. #define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13
  217. #define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14
  218. #define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15
  219. #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16
  220. #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17
  221. #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18
  222. #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19
  223. /* Part 1 */
  224. # define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0
  225. # define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1
  226. # define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2
  227. # define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3
  228. # define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4
  229. # define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5
  230. # define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6
  231. # define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7
  232. /* Part 2 */
  233. # define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0
  234. # define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1
  235. # define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2
  236. # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3
  237. # define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4
  238. # define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7)
  239. # define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5)
  240. # define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3)
  241. # define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1)
  242. # define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5
  243. # define SDVO_DTD_SDVO_FLAG_STALL (1 << 7)
  244. # define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6)
  245. # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6)
  246. # define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4)
  247. # define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4)
  248. # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4)
  249. # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4)
  250. # define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6
  251. /**
  252. * Generates a DTD based on the given width, height, and flags.
  253. *
  254. * This will be supported by any device supporting scaling or interlaced
  255. * modes.
  256. */
  257. #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a
  258. # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0
  259. # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1
  260. # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2
  261. # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3
  262. # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4
  263. # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5
  264. # define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6
  265. # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0)
  266. # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1)
  267. #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b
  268. #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c
  269. /** Returns a struct intel_sdvo_pixel_clock_range */
  270. #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d
  271. /** Returns a struct intel_sdvo_pixel_clock_range */
  272. #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e
  273. /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
  274. #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f
  275. /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
  276. #define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20
  277. /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
  278. #define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21
  279. # define SDVO_CLOCK_RATE_MULT_1X (1 << 0)
  280. # define SDVO_CLOCK_RATE_MULT_2X (1 << 1)
  281. # define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
  282. #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
  283. /** 6 bytes of bit flags for TV formats shared by all TV format functions */
  284. struct psb_intel_sdvo_tv_format {
  285. unsigned int ntsc_m:1;
  286. unsigned int ntsc_j:1;
  287. unsigned int ntsc_443:1;
  288. unsigned int pal_b:1;
  289. unsigned int pal_d:1;
  290. unsigned int pal_g:1;
  291. unsigned int pal_h:1;
  292. unsigned int pal_i:1;
  293. unsigned int pal_m:1;
  294. unsigned int pal_n:1;
  295. unsigned int pal_nc:1;
  296. unsigned int pal_60:1;
  297. unsigned int secam_b:1;
  298. unsigned int secam_d:1;
  299. unsigned int secam_g:1;
  300. unsigned int secam_k:1;
  301. unsigned int secam_k1:1;
  302. unsigned int secam_l:1;
  303. unsigned int secam_60:1;
  304. unsigned int hdtv_std_smpte_240m_1080i_59:1;
  305. unsigned int hdtv_std_smpte_240m_1080i_60:1;
  306. unsigned int hdtv_std_smpte_260m_1080i_59:1;
  307. unsigned int hdtv_std_smpte_260m_1080i_60:1;
  308. unsigned int hdtv_std_smpte_274m_1080i_50:1;
  309. unsigned int hdtv_std_smpte_274m_1080i_59:1;
  310. unsigned int hdtv_std_smpte_274m_1080i_60:1;
  311. unsigned int hdtv_std_smpte_274m_1080p_23:1;
  312. unsigned int hdtv_std_smpte_274m_1080p_24:1;
  313. unsigned int hdtv_std_smpte_274m_1080p_25:1;
  314. unsigned int hdtv_std_smpte_274m_1080p_29:1;
  315. unsigned int hdtv_std_smpte_274m_1080p_30:1;
  316. unsigned int hdtv_std_smpte_274m_1080p_50:1;
  317. unsigned int hdtv_std_smpte_274m_1080p_59:1;
  318. unsigned int hdtv_std_smpte_274m_1080p_60:1;
  319. unsigned int hdtv_std_smpte_295m_1080i_50:1;
  320. unsigned int hdtv_std_smpte_295m_1080p_50:1;
  321. unsigned int hdtv_std_smpte_296m_720p_59:1;
  322. unsigned int hdtv_std_smpte_296m_720p_60:1;
  323. unsigned int hdtv_std_smpte_296m_720p_50:1;
  324. unsigned int hdtv_std_smpte_293m_480p_59:1;
  325. unsigned int hdtv_std_smpte_170m_480i_59:1;
  326. unsigned int hdtv_std_iturbt601_576i_50:1;
  327. unsigned int hdtv_std_iturbt601_576p_50:1;
  328. unsigned int hdtv_std_eia_7702a_480i_60:1;
  329. unsigned int hdtv_std_eia_7702a_480p_60:1;
  330. unsigned int pad:3;
  331. } __attribute__((packed));
  332. #define SDVO_CMD_GET_TV_FORMAT 0x28
  333. #define SDVO_CMD_SET_TV_FORMAT 0x29
  334. /** Returns the resolutiosn that can be used with the given TV format */
  335. #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83
  336. struct psb_intel_sdvo_sdtv_resolution_request {
  337. unsigned int ntsc_m:1;
  338. unsigned int ntsc_j:1;
  339. unsigned int ntsc_443:1;
  340. unsigned int pal_b:1;
  341. unsigned int pal_d:1;
  342. unsigned int pal_g:1;
  343. unsigned int pal_h:1;
  344. unsigned int pal_i:1;
  345. unsigned int pal_m:1;
  346. unsigned int pal_n:1;
  347. unsigned int pal_nc:1;
  348. unsigned int pal_60:1;
  349. unsigned int secam_b:1;
  350. unsigned int secam_d:1;
  351. unsigned int secam_g:1;
  352. unsigned int secam_k:1;
  353. unsigned int secam_k1:1;
  354. unsigned int secam_l:1;
  355. unsigned int secam_60:1;
  356. unsigned int pad:5;
  357. } __attribute__((packed));
  358. struct psb_intel_sdvo_sdtv_resolution_reply {
  359. unsigned int res_320x200:1;
  360. unsigned int res_320x240:1;
  361. unsigned int res_400x300:1;
  362. unsigned int res_640x350:1;
  363. unsigned int res_640x400:1;
  364. unsigned int res_640x480:1;
  365. unsigned int res_704x480:1;
  366. unsigned int res_704x576:1;
  367. unsigned int res_720x350:1;
  368. unsigned int res_720x400:1;
  369. unsigned int res_720x480:1;
  370. unsigned int res_720x540:1;
  371. unsigned int res_720x576:1;
  372. unsigned int res_768x576:1;
  373. unsigned int res_800x600:1;
  374. unsigned int res_832x624:1;
  375. unsigned int res_920x766:1;
  376. unsigned int res_1024x768:1;
  377. unsigned int res_1280x1024:1;
  378. unsigned int pad:5;
  379. } __attribute__((packed));
  380. /* Get supported resolution with squire pixel aspect ratio that can be
  381. scaled for the requested HDTV format */
  382. #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
  383. struct psb_intel_sdvo_hdtv_resolution_request {
  384. unsigned int hdtv_std_smpte_240m_1080i_59:1;
  385. unsigned int hdtv_std_smpte_240m_1080i_60:1;
  386. unsigned int hdtv_std_smpte_260m_1080i_59:1;
  387. unsigned int hdtv_std_smpte_260m_1080i_60:1;
  388. unsigned int hdtv_std_smpte_274m_1080i_50:1;
  389. unsigned int hdtv_std_smpte_274m_1080i_59:1;
  390. unsigned int hdtv_std_smpte_274m_1080i_60:1;
  391. unsigned int hdtv_std_smpte_274m_1080p_23:1;
  392. unsigned int hdtv_std_smpte_274m_1080p_24:1;
  393. unsigned int hdtv_std_smpte_274m_1080p_25:1;
  394. unsigned int hdtv_std_smpte_274m_1080p_29:1;
  395. unsigned int hdtv_std_smpte_274m_1080p_30:1;
  396. unsigned int hdtv_std_smpte_274m_1080p_50:1;
  397. unsigned int hdtv_std_smpte_274m_1080p_59:1;
  398. unsigned int hdtv_std_smpte_274m_1080p_60:1;
  399. unsigned int hdtv_std_smpte_295m_1080i_50:1;
  400. unsigned int hdtv_std_smpte_295m_1080p_50:1;
  401. unsigned int hdtv_std_smpte_296m_720p_59:1;
  402. unsigned int hdtv_std_smpte_296m_720p_60:1;
  403. unsigned int hdtv_std_smpte_296m_720p_50:1;
  404. unsigned int hdtv_std_smpte_293m_480p_59:1;
  405. unsigned int hdtv_std_smpte_170m_480i_59:1;
  406. unsigned int hdtv_std_iturbt601_576i_50:1;
  407. unsigned int hdtv_std_iturbt601_576p_50:1;
  408. unsigned int hdtv_std_eia_7702a_480i_60:1;
  409. unsigned int hdtv_std_eia_7702a_480p_60:1;
  410. unsigned int pad:6;
  411. } __attribute__((packed));
  412. struct psb_intel_sdvo_hdtv_resolution_reply {
  413. unsigned int res_640x480:1;
  414. unsigned int res_800x600:1;
  415. unsigned int res_1024x768:1;
  416. unsigned int res_1280x960:1;
  417. unsigned int res_1400x1050:1;
  418. unsigned int res_1600x1200:1;
  419. unsigned int res_1920x1440:1;
  420. unsigned int res_2048x1536:1;
  421. unsigned int res_2560x1920:1;
  422. unsigned int res_3200x2400:1;
  423. unsigned int res_3840x2880:1;
  424. unsigned int pad1:5;
  425. unsigned int res_848x480:1;
  426. unsigned int res_1064x600:1;
  427. unsigned int res_1280x720:1;
  428. unsigned int res_1360x768:1;
  429. unsigned int res_1704x960:1;
  430. unsigned int res_1864x1050:1;
  431. unsigned int res_1920x1080:1;
  432. unsigned int res_2128x1200:1;
  433. unsigned int res_2560x1400:1;
  434. unsigned int res_2728x1536:1;
  435. unsigned int res_3408x1920:1;
  436. unsigned int res_4264x2400:1;
  437. unsigned int res_5120x2880:1;
  438. unsigned int pad2:3;
  439. unsigned int res_768x480:1;
  440. unsigned int res_960x600:1;
  441. unsigned int res_1152x720:1;
  442. unsigned int res_1124x768:1;
  443. unsigned int res_1536x960:1;
  444. unsigned int res_1680x1050:1;
  445. unsigned int res_1728x1080:1;
  446. unsigned int res_1920x1200:1;
  447. unsigned int res_2304x1440:1;
  448. unsigned int res_2456x1536:1;
  449. unsigned int res_3072x1920:1;
  450. unsigned int res_3840x2400:1;
  451. unsigned int res_4608x2880:1;
  452. unsigned int pad3:3;
  453. unsigned int res_1280x1024:1;
  454. unsigned int pad4:7;
  455. unsigned int res_1280x768:1;
  456. unsigned int pad5:7;
  457. } __attribute__((packed));
  458. /* Get supported power state returns info for encoder and monitor, rely on
  459. last SetTargetInput and SetTargetOutput calls */
  460. #define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
  461. /* Get power state returns info for encoder and monitor, rely on last
  462. SetTargetInput and SetTargetOutput calls */
  463. #define SDVO_CMD_GET_POWER_STATE 0x2b
  464. #define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
  465. #define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
  466. # define SDVO_ENCODER_STATE_ON (1 << 0)
  467. # define SDVO_ENCODER_STATE_STANDBY (1 << 1)
  468. # define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
  469. # define SDVO_ENCODER_STATE_OFF (1 << 3)
  470. # define SDVO_MONITOR_STATE_ON (1 << 4)
  471. # define SDVO_MONITOR_STATE_STANDBY (1 << 5)
  472. # define SDVO_MONITOR_STATE_SUSPEND (1 << 6)
  473. # define SDVO_MONITOR_STATE_OFF (1 << 7)
  474. #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d
  475. #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e
  476. #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f
  477. /**
  478. * The panel power sequencing parameters are in units of milliseconds.
  479. * The high fields are bits 8:9 of the 10-bit values.
  480. */
  481. struct psb_sdvo_panel_power_sequencing {
  482. u8 t0;
  483. u8 t1;
  484. u8 t2;
  485. u8 t3;
  486. u8 t4;
  487. unsigned int t0_high:2;
  488. unsigned int t1_high:2;
  489. unsigned int t2_high:2;
  490. unsigned int t3_high:2;
  491. unsigned int t4_high:2;
  492. unsigned int pad:6;
  493. } __attribute__((packed));
  494. #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30
  495. struct sdvo_max_backlight_reply {
  496. u8 max_value;
  497. u8 default_value;
  498. } __attribute__((packed));
  499. #define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31
  500. #define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32
  501. #define SDVO_CMD_GET_AMBIENT_LIGHT 0x33
  502. struct sdvo_get_ambient_light_reply {
  503. u16 trip_low;
  504. u16 trip_high;
  505. u16 value;
  506. } __attribute__((packed));
  507. #define SDVO_CMD_SET_AMBIENT_LIGHT 0x34
  508. struct sdvo_set_ambient_light_reply {
  509. u16 trip_low;
  510. u16 trip_high;
  511. unsigned int enable:1;
  512. unsigned int pad:7;
  513. } __attribute__((packed));
  514. /* Set display power state */
  515. #define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d
  516. # define SDVO_DISPLAY_STATE_ON (1 << 0)
  517. # define SDVO_DISPLAY_STATE_STANDBY (1 << 1)
  518. # define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)
  519. # define SDVO_DISPLAY_STATE_OFF (1 << 3)
  520. #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
  521. struct psb_intel_sdvo_enhancements_reply {
  522. unsigned int flicker_filter:1;
  523. unsigned int flicker_filter_adaptive:1;
  524. unsigned int flicker_filter_2d:1;
  525. unsigned int saturation:1;
  526. unsigned int hue:1;
  527. unsigned int brightness:1;
  528. unsigned int contrast:1;
  529. unsigned int overscan_h:1;
  530. unsigned int overscan_v:1;
  531. unsigned int hpos:1;
  532. unsigned int vpos:1;
  533. unsigned int sharpness:1;
  534. unsigned int dot_crawl:1;
  535. unsigned int dither:1;
  536. unsigned int tv_chroma_filter:1;
  537. unsigned int tv_luma_filter:1;
  538. } __attribute__((packed));
  539. /* Picture enhancement limits below are dependent on the current TV format,
  540. * and thus need to be queried and set after it.
  541. */
  542. #define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d
  543. #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b
  544. #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52
  545. #define SDVO_CMD_GET_MAX_SATURATION 0x55
  546. #define SDVO_CMD_GET_MAX_HUE 0x58
  547. #define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
  548. #define SDVO_CMD_GET_MAX_CONTRAST 0x5e
  549. #define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
  550. #define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
  551. #define SDVO_CMD_GET_MAX_HPOS 0x67
  552. #define SDVO_CMD_GET_MAX_VPOS 0x6a
  553. #define SDVO_CMD_GET_MAX_SHARPNESS 0x6d
  554. #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74
  555. #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77
  556. struct psb_intel_sdvo_enhancement_limits_reply {
  557. u16 max_value;
  558. u16 default_value;
  559. } __attribute__((packed));
  560. #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f
  561. #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80
  562. # define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0)
  563. # define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0)
  564. # define SDVO_LVDS_CONNECTOR_SPWG (0 << 2)
  565. # define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2)
  566. # define SDVO_LVDS_SINGLE_CHANNEL (0 << 4)
  567. # define SDVO_LVDS_DUAL_CHANNEL (1 << 4)
  568. #define SDVO_CMD_GET_FLICKER_FILTER 0x4e
  569. #define SDVO_CMD_SET_FLICKER_FILTER 0x4f
  570. #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50
  571. #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51
  572. #define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53
  573. #define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54
  574. #define SDVO_CMD_GET_SATURATION 0x56
  575. #define SDVO_CMD_SET_SATURATION 0x57
  576. #define SDVO_CMD_GET_HUE 0x59
  577. #define SDVO_CMD_SET_HUE 0x5a
  578. #define SDVO_CMD_GET_BRIGHTNESS 0x5c
  579. #define SDVO_CMD_SET_BRIGHTNESS 0x5d
  580. #define SDVO_CMD_GET_CONTRAST 0x5f
  581. #define SDVO_CMD_SET_CONTRAST 0x60
  582. #define SDVO_CMD_GET_OVERSCAN_H 0x62
  583. #define SDVO_CMD_SET_OVERSCAN_H 0x63
  584. #define SDVO_CMD_GET_OVERSCAN_V 0x65
  585. #define SDVO_CMD_SET_OVERSCAN_V 0x66
  586. #define SDVO_CMD_GET_HPOS 0x68
  587. #define SDVO_CMD_SET_HPOS 0x69
  588. #define SDVO_CMD_GET_VPOS 0x6b
  589. #define SDVO_CMD_SET_VPOS 0x6c
  590. #define SDVO_CMD_GET_SHARPNESS 0x6e
  591. #define SDVO_CMD_SET_SHARPNESS 0x6f
  592. #define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75
  593. #define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76
  594. #define SDVO_CMD_GET_TV_LUMA_FILTER 0x78
  595. #define SDVO_CMD_SET_TV_LUMA_FILTER 0x79
  596. struct psb_intel_sdvo_enhancements_arg {
  597. u16 value;
  598. }__attribute__((packed));
  599. #define SDVO_CMD_GET_DOT_CRAWL 0x70
  600. #define SDVO_CMD_SET_DOT_CRAWL 0x71
  601. # define SDVO_DOT_CRAWL_ON (1 << 0)
  602. # define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1)
  603. #define SDVO_CMD_GET_DITHER 0x72
  604. #define SDVO_CMD_SET_DITHER 0x73
  605. # define SDVO_DITHER_ON (1 << 0)
  606. # define SDVO_DITHER_DEFAULT_ON (1 << 1)
  607. #define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
  608. # define SDVO_CONTROL_BUS_PROM (1 << 0)
  609. # define SDVO_CONTROL_BUS_DDC1 (1 << 1)
  610. # define SDVO_CONTROL_BUS_DDC2 (1 << 2)
  611. # define SDVO_CONTROL_BUS_DDC3 (1 << 3)
  612. /* HDMI op codes */
  613. #define SDVO_CMD_GET_SUPP_ENCODE 0x9d
  614. #define SDVO_CMD_GET_ENCODE 0x9e
  615. #define SDVO_CMD_SET_ENCODE 0x9f
  616. #define SDVO_ENCODE_DVI 0x0
  617. #define SDVO_ENCODE_HDMI 0x1
  618. #define SDVO_CMD_SET_PIXEL_REPLI 0x8b
  619. #define SDVO_CMD_GET_PIXEL_REPLI 0x8c
  620. #define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d
  621. #define SDVO_CMD_SET_COLORIMETRY 0x8e
  622. #define SDVO_COLORIMETRY_RGB256 0x0
  623. #define SDVO_COLORIMETRY_RGB220 0x1
  624. #define SDVO_COLORIMETRY_YCrCb422 0x3
  625. #define SDVO_COLORIMETRY_YCrCb444 0x4
  626. #define SDVO_CMD_GET_COLORIMETRY 0x8f
  627. #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
  628. #define SDVO_CMD_SET_AUDIO_STAT 0x91
  629. #define SDVO_CMD_GET_AUDIO_STAT 0x92
  630. #define SDVO_CMD_SET_HBUF_INDEX 0x93
  631. #define SDVO_CMD_GET_HBUF_INDEX 0x94
  632. #define SDVO_CMD_GET_HBUF_INFO 0x95
  633. #define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
  634. #define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97
  635. #define SDVO_CMD_SET_HBUF_DATA 0x98
  636. #define SDVO_CMD_GET_HBUF_DATA 0x99
  637. #define SDVO_CMD_SET_HBUF_TXRATE 0x9a
  638. #define SDVO_CMD_GET_HBUF_TXRATE 0x9b
  639. #define SDVO_HBUF_TX_DISABLED (0 << 6)
  640. #define SDVO_HBUF_TX_ONCE (2 << 6)
  641. #define SDVO_HBUF_TX_VSYNC (3 << 6)
  642. #define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c
  643. #define SDVO_NEED_TO_STALL (1 << 7)
  644. struct psb_intel_sdvo_encode {
  645. u8 dvi_rev;
  646. u8 hdmi_rev;
  647. } __attribute__ ((packed));