psb_intel_reg.h 49 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2009, Intel Corporation.
  4. */
  5. #ifndef __PSB_INTEL_REG_H__
  6. #define __PSB_INTEL_REG_H__
  7. /*
  8. * GPIO regs
  9. */
  10. #define GPIOA 0x5010
  11. #define GPIOB 0x5014
  12. #define GPIOC 0x5018
  13. #define GPIOD 0x501c
  14. #define GPIOE 0x5020
  15. #define GPIOF 0x5024
  16. #define GPIOG 0x5028
  17. #define GPIOH 0x502c
  18. # define GPIO_CLOCK_DIR_MASK (1 << 0)
  19. # define GPIO_CLOCK_DIR_IN (0 << 1)
  20. # define GPIO_CLOCK_DIR_OUT (1 << 1)
  21. # define GPIO_CLOCK_VAL_MASK (1 << 2)
  22. # define GPIO_CLOCK_VAL_OUT (1 << 3)
  23. # define GPIO_CLOCK_VAL_IN (1 << 4)
  24. # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
  25. # define GPIO_DATA_DIR_MASK (1 << 8)
  26. # define GPIO_DATA_DIR_IN (0 << 9)
  27. # define GPIO_DATA_DIR_OUT (1 << 9)
  28. # define GPIO_DATA_VAL_MASK (1 << 10)
  29. # define GPIO_DATA_VAL_OUT (1 << 11)
  30. # define GPIO_DATA_VAL_IN (1 << 12)
  31. # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
  32. #define GMBUS0 0x5100 /* clock/port select */
  33. #define GMBUS_RATE_100KHZ (0<<8)
  34. #define GMBUS_RATE_50KHZ (1<<8)
  35. #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
  36. #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
  37. #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
  38. #define GMBUS_PORT_DISABLED 0
  39. #define GMBUS_PORT_SSC 1
  40. #define GMBUS_PORT_VGADDC 2
  41. #define GMBUS_PORT_PANEL 3
  42. #define GMBUS_PORT_DPC 4 /* HDMIC */
  43. #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
  44. /* 6 reserved */
  45. #define GMBUS_PORT_DPD 7 /* HDMID */
  46. #define GMBUS_NUM_PORTS 8
  47. #define GMBUS1 0x5104 /* command/status */
  48. #define GMBUS_SW_CLR_INT (1<<31)
  49. #define GMBUS_SW_RDY (1<<30)
  50. #define GMBUS_ENT (1<<29) /* enable timeout */
  51. #define GMBUS_CYCLE_NONE (0<<25)
  52. #define GMBUS_CYCLE_WAIT (1<<25)
  53. #define GMBUS_CYCLE_INDEX (2<<25)
  54. #define GMBUS_CYCLE_STOP (4<<25)
  55. #define GMBUS_BYTE_COUNT_SHIFT 16
  56. #define GMBUS_SLAVE_INDEX_SHIFT 8
  57. #define GMBUS_SLAVE_ADDR_SHIFT 1
  58. #define GMBUS_SLAVE_READ (1<<0)
  59. #define GMBUS_SLAVE_WRITE (0<<0)
  60. #define GMBUS2 0x5108 /* status */
  61. #define GMBUS_INUSE (1<<15)
  62. #define GMBUS_HW_WAIT_PHASE (1<<14)
  63. #define GMBUS_STALL_TIMEOUT (1<<13)
  64. #define GMBUS_INT (1<<12)
  65. #define GMBUS_HW_RDY (1<<11)
  66. #define GMBUS_SATOER (1<<10)
  67. #define GMBUS_ACTIVE (1<<9)
  68. #define GMBUS3 0x510c /* data buffer bytes 3-0 */
  69. #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
  70. #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
  71. #define GMBUS_NAK_EN (1<<3)
  72. #define GMBUS_IDLE_EN (1<<2)
  73. #define GMBUS_HW_WAIT_EN (1<<1)
  74. #define GMBUS_HW_RDY_EN (1<<0)
  75. #define GMBUS5 0x5120 /* byte index */
  76. #define GMBUS_2BYTE_INDEX_EN (1<<31)
  77. #define BLC_PWM_CTL 0x61254
  78. #define BLC_PWM_CTL2 0x61250
  79. #define PWM_ENABLE (1 << 31)
  80. #define PWM_LEGACY_MODE (1 << 30)
  81. #define PWM_PIPE_B (1 << 29)
  82. #define BLC_PWM_CTL_C 0x62254
  83. #define BLC_PWM_CTL2_C 0x62250
  84. #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
  85. /*
  86. * This is the most significant 15 bits of the number of backlight cycles in a
  87. * complete cycle of the modulated backlight control.
  88. *
  89. * The actual value is this field multiplied by two.
  90. */
  91. #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
  92. #define BLM_LEGACY_MODE (1 << 16)
  93. /*
  94. * This is the number of cycles out of the backlight modulation cycle for which
  95. * the backlight is on.
  96. *
  97. * This field must be no greater than the number of cycles in the complete
  98. * backlight modulation cycle.
  99. */
  100. #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
  101. #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
  102. #define I915_GCFGC 0xf0
  103. #define I915_LOW_FREQUENCY_ENABLE (1 << 7)
  104. #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
  105. #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
  106. #define I915_DISPLAY_CLOCK_MASK (7 << 4)
  107. #define I855_HPLLCC 0xc0
  108. #define I855_CLOCK_CONTROL_MASK (3 << 0)
  109. #define I855_CLOCK_133_200 (0 << 0)
  110. #define I855_CLOCK_100_200 (1 << 0)
  111. #define I855_CLOCK_100_133 (2 << 0)
  112. #define I855_CLOCK_166_250 (3 << 0)
  113. /* I830 CRTC registers */
  114. #define HTOTAL_A 0x60000
  115. #define HBLANK_A 0x60004
  116. #define HSYNC_A 0x60008
  117. #define VTOTAL_A 0x6000c
  118. #define VBLANK_A 0x60010
  119. #define VSYNC_A 0x60014
  120. #define PIPEASRC 0x6001c
  121. #define BCLRPAT_A 0x60020
  122. #define VSYNCSHIFT_A 0x60028
  123. #define HTOTAL_B 0x61000
  124. #define HBLANK_B 0x61004
  125. #define HSYNC_B 0x61008
  126. #define VTOTAL_B 0x6100c
  127. #define VBLANK_B 0x61010
  128. #define VSYNC_B 0x61014
  129. #define PIPEBSRC 0x6101c
  130. #define BCLRPAT_B 0x61020
  131. #define VSYNCSHIFT_B 0x61028
  132. #define HTOTAL_C 0x62000
  133. #define HBLANK_C 0x62004
  134. #define HSYNC_C 0x62008
  135. #define VTOTAL_C 0x6200c
  136. #define VBLANK_C 0x62010
  137. #define VSYNC_C 0x62014
  138. #define PIPECSRC 0x6201c
  139. #define BCLRPAT_C 0x62020
  140. #define VSYNCSHIFT_C 0x62028
  141. #define PP_STATUS 0x61200
  142. # define PP_ON (1 << 31)
  143. /*
  144. * Indicates that all dependencies of the panel are on:
  145. *
  146. * - PLL enabled
  147. * - pipe enabled
  148. * - LVDS/DVOB/DVOC on
  149. */
  150. #define PP_READY (1 << 30)
  151. #define PP_SEQUENCE_NONE (0 << 28)
  152. #define PP_SEQUENCE_ON (1 << 28)
  153. #define PP_SEQUENCE_OFF (2 << 28)
  154. #define PP_SEQUENCE_MASK 0x30000000
  155. #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
  156. #define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
  157. #define PP_SEQUENCE_STATE_MASK 0x0000000f
  158. #define PP_CONTROL 0x61204
  159. #define POWER_TARGET_ON (1 << 0)
  160. #define PANEL_UNLOCK_REGS (0xabcd << 16)
  161. #define PANEL_UNLOCK_MASK (0xffff << 16)
  162. #define EDP_FORCE_VDD (1 << 3)
  163. #define EDP_BLC_ENABLE (1 << 2)
  164. #define PANEL_POWER_RESET (1 << 1)
  165. #define PANEL_POWER_OFF (0 << 0)
  166. #define PANEL_POWER_ON (1 << 0)
  167. /* Poulsbo/Oaktrail */
  168. #define LVDSPP_ON 0x61208
  169. #define LVDSPP_OFF 0x6120c
  170. #define PP_CYCLE 0x61210
  171. /* Cedartrail */
  172. #define PP_ON_DELAYS 0x61208 /* Cedartrail */
  173. #define PANEL_PORT_SELECT_MASK (3 << 30)
  174. #define PANEL_PORT_SELECT_LVDS (0 << 30)
  175. #define PANEL_PORT_SELECT_EDP (1 << 30)
  176. #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
  177. #define PANEL_POWER_UP_DELAY_SHIFT 16
  178. #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
  179. #define PANEL_LIGHT_ON_DELAY_SHIFT 0
  180. #define PP_OFF_DELAYS 0x6120c /* Cedartrail */
  181. #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
  182. #define PANEL_POWER_DOWN_DELAY_SHIFT 16
  183. #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
  184. #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
  185. #define PP_DIVISOR 0x61210 /* Cedartrail */
  186. #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
  187. #define PP_REFERENCE_DIVIDER_SHIFT 8
  188. #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
  189. #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
  190. #define PFIT_CONTROL 0x61230
  191. #define PFIT_ENABLE (1 << 31)
  192. #define PFIT_PIPE_MASK (3 << 29)
  193. #define PFIT_PIPE_SHIFT 29
  194. #define PFIT_SCALING_MODE_PILLARBOX (1 << 27)
  195. #define PFIT_SCALING_MODE_LETTERBOX (3 << 26)
  196. #define VERT_INTERP_DISABLE (0 << 10)
  197. #define VERT_INTERP_BILINEAR (1 << 10)
  198. #define VERT_INTERP_MASK (3 << 10)
  199. #define VERT_AUTO_SCALE (1 << 9)
  200. #define HORIZ_INTERP_DISABLE (0 << 6)
  201. #define HORIZ_INTERP_BILINEAR (1 << 6)
  202. #define HORIZ_INTERP_MASK (3 << 6)
  203. #define HORIZ_AUTO_SCALE (1 << 5)
  204. #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
  205. #define PFIT_PGM_RATIOS 0x61234
  206. #define PFIT_VERT_SCALE_MASK 0xfff00000
  207. #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
  208. #define PFIT_AUTO_RATIOS 0x61238
  209. #define DPLL_A 0x06014
  210. #define DPLL_B 0x06018
  211. #define DPLL_VCO_ENABLE (1 << 31)
  212. #define DPLL_DVO_HIGH_SPEED (1 << 30)
  213. #define DPLL_SYNCLOCK_ENABLE (1 << 29)
  214. #define DPLL_VGA_MODE_DIS (1 << 28)
  215. #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
  216. #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
  217. #define DPLL_MODE_MASK (3 << 26)
  218. #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
  219. #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
  220. #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
  221. #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
  222. #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
  223. #define DPLL_FPA0h1_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
  224. #define DPLL_LOCK (1 << 15) /* CDV */
  225. /*
  226. * The i830 generation, in DAC/serial mode, defines p1 as two plus this
  227. * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
  228. */
  229. # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
  230. /*
  231. * The i830 generation, in LVDS mode, defines P1 as the bit number set within
  232. * this field (only one bit may be set).
  233. */
  234. #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
  235. #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
  236. #define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required
  237. * in DVO non-gang */
  238. # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
  239. #define PLL_REF_INPUT_DREFCLK (0 << 13)
  240. #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
  241. #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO
  242. * TVCLKIN */
  243. #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
  244. #define PLL_REF_INPUT_MASK (3 << 13)
  245. #define PLL_LOAD_PULSE_PHASE_SHIFT 9
  246. /*
  247. * Parallel to Serial Load Pulse phase selection.
  248. * Selects the phase for the 10X DPLL clock for the PCIe
  249. * digital display port. The range is 4 to 13; 10 or more
  250. * is just a flip delay. The default is 6
  251. */
  252. #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
  253. #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
  254. /*
  255. * SDVO multiplier for 945G/GM. Not used on 965.
  256. *
  257. * DPLL_MD_UDI_MULTIPLIER_MASK
  258. */
  259. #define SDVO_MULTIPLIER_MASK 0x000000ff
  260. #define SDVO_MULTIPLIER_SHIFT_HIRES 4
  261. #define SDVO_MULTIPLIER_SHIFT_VGA 0
  262. /*
  263. * PLL_MD
  264. */
  265. /* Pipe A SDVO/UDI clock multiplier/divider register for G965. */
  266. #define DPLL_A_MD 0x0601c
  267. /* Pipe B SDVO/UDI clock multiplier/divider register for G965. */
  268. #define DPLL_B_MD 0x06020
  269. /*
  270. * UDI pixel divider, controlling how many pixels are stuffed into a packet.
  271. *
  272. * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
  273. */
  274. #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
  275. #define DPLL_MD_UDI_DIVIDER_SHIFT 24
  276. /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
  277. #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
  278. #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
  279. /*
  280. * SDVO/UDI pixel multiplier.
  281. *
  282. * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
  283. * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
  284. * modes, the bus rate would be below the limits, so SDVO allows for stuffing
  285. * dummy bytes in the datastream at an increased clock rate, with both sides of
  286. * the link knowing how many bytes are fill.
  287. *
  288. * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
  289. * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
  290. * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
  291. * through an SDVO command.
  292. *
  293. * This register field has values of multiplication factor minus 1, with
  294. * a maximum multiplier of 5 for SDVO.
  295. */
  296. #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
  297. #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
  298. /*
  299. * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
  300. * This best be set to the default value (3) or the CRT won't work. No,
  301. * I don't entirely understand what this does...
  302. */
  303. #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
  304. #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
  305. #define DPLL_TEST 0x606c
  306. #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
  307. #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
  308. #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
  309. #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
  310. #define DPLLB_TEST_N_BYPASS (1 << 19)
  311. #define DPLLB_TEST_M_BYPASS (1 << 18)
  312. #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
  313. #define DPLLA_TEST_N_BYPASS (1 << 3)
  314. #define DPLLA_TEST_M_BYPASS (1 << 2)
  315. #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
  316. #define ADPA 0x61100
  317. #define ADPA_DAC_ENABLE (1 << 31)
  318. #define ADPA_DAC_DISABLE 0
  319. #define ADPA_PIPE_SELECT_MASK (1 << 30)
  320. #define ADPA_PIPE_A_SELECT 0
  321. #define ADPA_PIPE_B_SELECT (1 << 30)
  322. #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
  323. #define ADPA_SETS_HVPOLARITY 0
  324. #define ADPA_VSYNC_CNTL_DISABLE (1 << 11)
  325. #define ADPA_VSYNC_CNTL_ENABLE 0
  326. #define ADPA_HSYNC_CNTL_DISABLE (1 << 10)
  327. #define ADPA_HSYNC_CNTL_ENABLE 0
  328. #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
  329. #define ADPA_VSYNC_ACTIVE_LOW 0
  330. #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
  331. #define ADPA_HSYNC_ACTIVE_LOW 0
  332. #define FPA0 0x06040
  333. #define FPA1 0x06044
  334. #define FPB0 0x06048
  335. #define FPB1 0x0604c
  336. #define FP_N_DIV_MASK 0x003f0000
  337. #define FP_N_DIV_SHIFT 16
  338. #define FP_M1_DIV_MASK 0x00003f00
  339. #define FP_M1_DIV_SHIFT 8
  340. #define FP_M2_DIV_MASK 0x0000003f
  341. #define FP_M2_DIV_SHIFT 0
  342. #define PORT_HOTPLUG_EN 0x61110
  343. #define HDMIB_HOTPLUG_INT_EN (1 << 29)
  344. #define HDMIC_HOTPLUG_INT_EN (1 << 28)
  345. #define HDMID_HOTPLUG_INT_EN (1 << 27)
  346. #define SDVOB_HOTPLUG_INT_EN (1 << 26)
  347. #define SDVOC_HOTPLUG_INT_EN (1 << 25)
  348. #define TV_HOTPLUG_INT_EN (1 << 18)
  349. #define CRT_HOTPLUG_INT_EN (1 << 9)
  350. #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
  351. /* CDV.. */
  352. #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
  353. #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
  354. #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
  355. #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
  356. #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
  357. #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
  358. #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
  359. #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
  360. #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
  361. #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
  362. #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
  363. #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
  364. #define CRT_HOTPLUG_DETECT_MASK 0x000000F8
  365. #define PORT_HOTPLUG_STAT 0x61114
  366. #define CRT_HOTPLUG_INT_STATUS (1 << 11)
  367. #define TV_HOTPLUG_INT_STATUS (1 << 10)
  368. #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
  369. #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
  370. #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
  371. #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
  372. #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
  373. #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
  374. #define SDVOB 0x61140
  375. #define SDVOC 0x61160
  376. #define SDVO_ENABLE (1 << 31)
  377. #define SDVO_PIPE_B_SELECT (1 << 30)
  378. #define SDVO_STALL_SELECT (1 << 29)
  379. #define SDVO_INTERRUPT_ENABLE (1 << 26)
  380. #define SDVO_COLOR_RANGE_16_235 (1 << 8)
  381. #define SDVO_AUDIO_ENABLE (1 << 6)
  382. /**
  383. * 915G/GM SDVO pixel multiplier.
  384. *
  385. * Programmed value is multiplier - 1, up to 5x.
  386. *
  387. * DPLL_MD_UDI_MULTIPLIER_MASK
  388. */
  389. #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
  390. #define SDVO_PORT_MULTIPLY_SHIFT 23
  391. #define SDVO_PHASE_SELECT_MASK (15 << 19)
  392. #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
  393. #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
  394. #define SDVOC_GANG_MODE (1 << 16)
  395. #define SDVO_BORDER_ENABLE (1 << 7)
  396. #define SDVOB_PCIE_CONCURRENCY (1 << 3)
  397. #define SDVO_DETECTED (1 << 2)
  398. /* Bits to be preserved when writing */
  399. #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
  400. #define SDVOC_PRESERVE_MASK (1 << 17)
  401. /*
  402. * This register controls the LVDS output enable, pipe selection, and data
  403. * format selection.
  404. *
  405. * All of the clock/data pairs are force powered down by power sequencing.
  406. */
  407. #define LVDS 0x61180
  408. /*
  409. * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
  410. * the DPLL semantics change when the LVDS is assigned to that pipe.
  411. */
  412. #define LVDS_PORT_EN (1 << 31)
  413. /* Selects pipe B for LVDS data. Must be set on pre-965. */
  414. #define LVDS_PIPEB_SELECT (1 << 30)
  415. /* Turns on border drawing to allow centered display. */
  416. #define LVDS_BORDER_EN (1 << 15)
  417. /*
  418. * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
  419. * pixel.
  420. */
  421. #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
  422. #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
  423. #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
  424. /*
  425. * Controls the A3 data pair, which contains the additional LSBs for 24 bit
  426. * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
  427. * on.
  428. */
  429. #define LVDS_A3_POWER_MASK (3 << 6)
  430. #define LVDS_A3_POWER_DOWN (0 << 6)
  431. #define LVDS_A3_POWER_UP (3 << 6)
  432. /*
  433. * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
  434. * is set.
  435. */
  436. #define LVDS_CLKB_POWER_MASK (3 << 4)
  437. #define LVDS_CLKB_POWER_DOWN (0 << 4)
  438. #define LVDS_CLKB_POWER_UP (3 << 4)
  439. /*
  440. * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
  441. * setting for whether we are in dual-channel mode. The B3 pair will
  442. * additionally only be powered up when LVDS_A3_POWER_UP is set.
  443. */
  444. #define LVDS_B0B3_POWER_MASK (3 << 2)
  445. #define LVDS_B0B3_POWER_DOWN (0 << 2)
  446. #define LVDS_B0B3_POWER_UP (3 << 2)
  447. #define PIPEACONF 0x70008
  448. #define PIPEACONF_ENABLE (1 << 31)
  449. #define PIPEACONF_DISABLE 0
  450. #define PIPEACONF_DOUBLE_WIDE (1 << 30)
  451. #define PIPECONF_ACTIVE (1 << 30)
  452. #define PIPECONF_DSIPLL_LOCK (1 << 29)
  453. #define PIPEACONF_SINGLE_WIDE 0
  454. #define PIPEACONF_PIPE_UNLOCKED 0
  455. #define PIPEACONF_DSR (1 << 26)
  456. #define PIPEACONF_PIPE_LOCKED (1 << 25)
  457. #define PIPEACONF_PALETTE 0
  458. #define PIPECONF_FORCE_BORDER (1 << 25)
  459. #define PIPEACONF_GAMMA (1 << 24)
  460. #define PIPECONF_PROGRESSIVE (0 << 21)
  461. #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
  462. #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
  463. #define PIPECONF_PLANE_OFF (1 << 19)
  464. #define PIPECONF_CURSOR_OFF (1 << 18)
  465. #define PIPEBCONF 0x71008
  466. #define PIPEBCONF_ENABLE (1 << 31)
  467. #define PIPEBCONF_DISABLE 0
  468. #define PIPEBCONF_DOUBLE_WIDE (1 << 30)
  469. #define PIPEBCONF_DISABLE 0
  470. #define PIPEBCONF_GAMMA (1 << 24)
  471. #define PIPEBCONF_PALETTE 0
  472. #define PIPECCONF 0x72008
  473. #define PIPEBGCMAXRED 0x71010
  474. #define PIPEBGCMAXGREEN 0x71014
  475. #define PIPEBGCMAXBLUE 0x71018
  476. #define PIPEASTAT 0x70024
  477. #define PIPEBSTAT 0x71024
  478. #define PIPECSTAT 0x72024
  479. #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
  480. #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2)
  481. #define PIPE_VBLANK_CLEAR (1 << 1)
  482. #define PIPE_VBLANK_STATUS (1 << 1)
  483. #define PIPE_TE_STATUS (1UL << 6)
  484. #define PIPE_DPST_EVENT_STATUS (1UL << 7)
  485. #define PIPE_VSYNC_CLEAR (1UL << 9)
  486. #define PIPE_VSYNC_STATUS (1UL << 9)
  487. #define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10)
  488. #define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11)
  489. #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
  490. #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18)
  491. #define PIPE_TE_ENABLE (1UL << 22)
  492. #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
  493. #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
  494. #define PIPE_VSYNC_ENABL (1UL << 25)
  495. #define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26)
  496. #define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27)
  497. #define PIPE_FIFO_UNDERRUN (1UL << 31)
  498. #define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | \
  499. PIPE_HDMI_AUDIO_BUFFER_DONE)
  500. #define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16))
  501. #define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17))
  502. #define HISTOGRAM_INT_CONTROL 0x61268
  503. #define HISTOGRAM_BIN_DATA 0X61264
  504. #define HISTOGRAM_LOGIC_CONTROL 0x61260
  505. #define PWM_CONTROL_LOGIC 0x61250
  506. #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
  507. #define HISTOGRAM_INTERRUPT_ENABLE (1UL << 31)
  508. #define HISTOGRAM_LOGIC_ENABLE (1UL << 31)
  509. #define PWM_LOGIC_ENABLE (1UL << 31)
  510. #define PWM_PHASEIN_ENABLE (1UL << 25)
  511. #define PWM_PHASEIN_INT_ENABLE (1UL << 24)
  512. #define PWM_PHASEIN_VB_COUNT 0x00001f00
  513. #define PWM_PHASEIN_INC 0x0000001f
  514. #define HISTOGRAM_INT_CTRL_CLEAR (1UL << 30)
  515. #define DPST_YUV_LUMA_MODE 0
  516. struct dpst_ie_histogram_control {
  517. union {
  518. uint32_t data;
  519. struct {
  520. uint32_t bin_reg_index:7;
  521. uint32_t reserved:4;
  522. uint32_t bin_reg_func_select:1;
  523. uint32_t sync_to_phase_in:1;
  524. uint32_t alt_enhancement_mode:2;
  525. uint32_t reserved1:1;
  526. uint32_t sync_to_phase_in_count:8;
  527. uint32_t histogram_mode_select:1;
  528. uint32_t reserved2:4;
  529. uint32_t ie_pipe_assignment:1;
  530. uint32_t ie_mode_table_enabled:1;
  531. uint32_t ie_histogram_enable:1;
  532. };
  533. };
  534. };
  535. struct dpst_guardband {
  536. union {
  537. uint32_t data;
  538. struct {
  539. uint32_t guardband:22;
  540. uint32_t guardband_interrupt_delay:8;
  541. uint32_t interrupt_status:1;
  542. uint32_t interrupt_enable:1;
  543. };
  544. };
  545. };
  546. #define PIPEAFRAMEHIGH 0x70040
  547. #define PIPEAFRAMEPIXEL 0x70044
  548. #define PIPEBFRAMEHIGH 0x71040
  549. #define PIPEBFRAMEPIXEL 0x71044
  550. #define PIPECFRAMEHIGH 0x72040
  551. #define PIPECFRAMEPIXEL 0x72044
  552. #define PIPE_FRAME_HIGH_MASK 0x0000ffff
  553. #define PIPE_FRAME_HIGH_SHIFT 0
  554. #define PIPE_FRAME_LOW_MASK 0xff000000
  555. #define PIPE_FRAME_LOW_SHIFT 24
  556. #define PIPE_PIXEL_MASK 0x00ffffff
  557. #define PIPE_PIXEL_SHIFT 0
  558. #define FW_BLC_SELF 0x20e0
  559. #define FW_BLC_SELF_EN (1<<15)
  560. #define DSPARB 0x70030
  561. #define DSPFW1 0x70034
  562. #define DSP_FIFO_SR_WM_MASK 0xFF800000
  563. #define DSP_FIFO_SR_WM_SHIFT 23
  564. #define CURSOR_B_FIFO_WM_MASK 0x003F0000
  565. #define CURSOR_B_FIFO_WM_SHIFT 16
  566. #define DSPFW2 0x70038
  567. #define CURSOR_A_FIFO_WM_MASK 0x3F00
  568. #define CURSOR_A_FIFO_WM_SHIFT 8
  569. #define DSP_PLANE_C_FIFO_WM_MASK 0x7F
  570. #define DSP_PLANE_C_FIFO_WM_SHIFT 0
  571. #define DSPFW3 0x7003c
  572. #define DSPFW4 0x70050
  573. #define DSPFW5 0x70054
  574. #define DSP_PLANE_B_FIFO_WM1_SHIFT 24
  575. #define DSP_PLANE_A_FIFO_WM1_SHIFT 16
  576. #define CURSOR_B_FIFO_WM1_SHIFT 8
  577. #define CURSOR_FIFO_SR_WM1_SHIFT 0
  578. #define DSPFW6 0x70058
  579. #define DSPCHICKENBIT 0x70400
  580. #define DSPACNTR 0x70180
  581. #define DSPBCNTR 0x71180
  582. #define DSPCCNTR 0x72180
  583. #define DISPLAY_PLANE_ENABLE (1 << 31)
  584. #define DISPLAY_PLANE_DISABLE 0
  585. #define DISPPLANE_GAMMA_ENABLE (1 << 30)
  586. #define DISPPLANE_GAMMA_DISABLE 0
  587. #define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
  588. #define DISPPLANE_8BPP (0x2 << 26)
  589. #define DISPPLANE_15_16BPP (0x4 << 26)
  590. #define DISPPLANE_16BPP (0x5 << 26)
  591. #define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26)
  592. #define DISPPLANE_32BPP (0x7 << 26)
  593. #define DISPPLANE_STEREO_ENABLE (1 << 25)
  594. #define DISPPLANE_STEREO_DISABLE 0
  595. #define DISPPLANE_SEL_PIPE_MASK (1 << 24)
  596. #define DISPPLANE_SEL_PIPE_POS 24
  597. #define DISPPLANE_SEL_PIPE_A 0
  598. #define DISPPLANE_SEL_PIPE_B (1 << 24)
  599. #define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
  600. #define DISPPLANE_SRC_KEY_DISABLE 0
  601. #define DISPPLANE_LINE_DOUBLE (1 << 20)
  602. #define DISPPLANE_NO_LINE_DOUBLE 0
  603. #define DISPPLANE_STEREO_POLARITY_FIRST 0
  604. #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
  605. /* plane B only */
  606. #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
  607. #define DISPPLANE_ALPHA_TRANS_DISABLE 0
  608. #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
  609. #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
  610. #define DISPPLANE_BOTTOM (4)
  611. #define DSPABASE 0x70184
  612. #define DSPALINOFF 0x70184
  613. #define DSPASTRIDE 0x70188
  614. #define DSPBBASE 0x71184
  615. #define DSPBLINOFF 0X71184
  616. #define DSPBADDR DSPBBASE
  617. #define DSPBSTRIDE 0x71188
  618. #define DSPCBASE 0x72184
  619. #define DSPCLINOFF 0x72184
  620. #define DSPCSTRIDE 0x72188
  621. #define DSPAKEYVAL 0x70194
  622. #define DSPAKEYMASK 0x70198
  623. #define DSPAPOS 0x7018C /* reserved */
  624. #define DSPASIZE 0x70190
  625. #define DSPBPOS 0x7118C
  626. #define DSPBSIZE 0x71190
  627. #define DSPCPOS 0x7218C
  628. #define DSPCSIZE 0x72190
  629. #define DSPASURF 0x7019C
  630. #define DSPATILEOFF 0x701A4
  631. #define DSPBSURF 0x7119C
  632. #define DSPBTILEOFF 0x711A4
  633. #define DSPCSURF 0x7219C
  634. #define DSPCTILEOFF 0x721A4
  635. #define DSPCKEYMAXVAL 0x721A0
  636. #define DSPCKEYMINVAL 0x72194
  637. #define DSPCKEYMSK 0x72198
  638. #define VGACNTRL 0x71400
  639. #define VGA_DISP_DISABLE (1 << 31)
  640. #define VGA_2X_MODE (1 << 30)
  641. #define VGA_PIPE_B_SELECT (1 << 29)
  642. /*
  643. * Overlay registers
  644. */
  645. #define OV_C_OFFSET 0x08000
  646. #define OV_OVADD 0x30000
  647. #define OV_DOVASTA 0x30008
  648. # define OV_PIPE_SELECT ((1 << 6)|(1 << 7))
  649. # define OV_PIPE_SELECT_POS 6
  650. # define OV_PIPE_A 0
  651. # define OV_PIPE_C 1
  652. #define OV_OGAMC5 0x30010
  653. #define OV_OGAMC4 0x30014
  654. #define OV_OGAMC3 0x30018
  655. #define OV_OGAMC2 0x3001C
  656. #define OV_OGAMC1 0x30020
  657. #define OV_OGAMC0 0x30024
  658. #define OVC_OVADD 0x38000
  659. #define OVC_DOVCSTA 0x38008
  660. #define OVC_OGAMC5 0x38010
  661. #define OVC_OGAMC4 0x38014
  662. #define OVC_OGAMC3 0x38018
  663. #define OVC_OGAMC2 0x3801C
  664. #define OVC_OGAMC1 0x38020
  665. #define OVC_OGAMC0 0x38024
  666. /*
  667. * Some BIOS scratch area registers. The 845 (and 830?) store the amount
  668. * of video memory available to the BIOS in SWF1.
  669. */
  670. #define SWF0 0x71410
  671. #define SWF1 0x71414
  672. #define SWF2 0x71418
  673. #define SWF3 0x7141c
  674. #define SWF4 0x71420
  675. #define SWF5 0x71424
  676. #define SWF6 0x71428
  677. /*
  678. * 855 scratch registers.
  679. */
  680. #define SWF00 0x70410
  681. #define SWF01 0x70414
  682. #define SWF02 0x70418
  683. #define SWF03 0x7041c
  684. #define SWF04 0x70420
  685. #define SWF05 0x70424
  686. #define SWF06 0x70428
  687. #define SWF10 SWF0
  688. #define SWF11 SWF1
  689. #define SWF12 SWF2
  690. #define SWF13 SWF3
  691. #define SWF14 SWF4
  692. #define SWF15 SWF5
  693. #define SWF16 SWF6
  694. #define SWF30 0x72414
  695. #define SWF31 0x72418
  696. #define SWF32 0x7241c
  697. /*
  698. * Palette registers
  699. */
  700. #define PALETTE_A 0x0a000
  701. #define PALETTE_B 0x0a800
  702. #define PALETTE_C 0x0ac00
  703. /* Cursor A & B regs */
  704. #define CURACNTR 0x70080
  705. #define CURSOR_MODE_DISABLE 0x00
  706. #define CURSOR_MODE_64_32B_AX 0x07
  707. #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
  708. #define MCURSOR_GAMMA_ENABLE (1 << 26)
  709. #define CURABASE 0x70084
  710. #define CURAPOS 0x70088
  711. #define CURSOR_POS_MASK 0x007FF
  712. #define CURSOR_POS_SIGN 0x8000
  713. #define CURSOR_X_SHIFT 0
  714. #define CURSOR_Y_SHIFT 16
  715. #define CURBCNTR 0x700c0
  716. #define CURBBASE 0x700c4
  717. #define CURBPOS 0x700c8
  718. #define CURCCNTR 0x700e0
  719. #define CURCBASE 0x700e4
  720. #define CURCPOS 0x700e8
  721. /*
  722. * Interrupt Registers
  723. */
  724. #define IER 0x020a0
  725. #define IIR 0x020a4
  726. #define IMR 0x020a8
  727. #define ISR 0x020ac
  728. /*
  729. * MOORESTOWN delta registers
  730. */
  731. #define MRST_DPLL_A 0x0f014
  732. #define MDFLD_DPLL_B 0x0f018
  733. #define MDFLD_INPUT_REF_SEL (1 << 14)
  734. #define MDFLD_VCO_SEL (1 << 16)
  735. #define DPLLA_MODE_LVDS (2 << 26) /* mrst */
  736. #define MDFLD_PLL_LATCHEN (1 << 28)
  737. #define MDFLD_PWR_GATE_EN (1 << 30)
  738. #define MDFLD_P1_MASK (0x1FF << 17)
  739. #define MRST_FPA0 0x0f040
  740. #define MRST_FPA1 0x0f044
  741. #define MDFLD_DPLL_DIV0 0x0f048
  742. #define MDFLD_DPLL_DIV1 0x0f04c
  743. #define MRST_PERF_MODE 0x020f4
  744. /*
  745. * MEDFIELD HDMI registers
  746. */
  747. #define HDMIPHYMISCCTL 0x61134
  748. #define HDMI_PHY_POWER_DOWN 0x7f
  749. #define HDMIB_CONTROL 0x61140
  750. #define HDMIB_PORT_EN (1 << 31)
  751. #define HDMIB_PIPE_B_SELECT (1 << 30)
  752. #define HDMIB_NULL_PACKET (1 << 9)
  753. #define HDMIB_HDCP_PORT (1 << 5)
  754. /* #define LVDS 0x61180 */
  755. #define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25)
  756. #define MRST_PANEL_24_DOT_1_FORMAT (1 << 24)
  757. #define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6)
  758. #define MIPI 0x61190
  759. #define MIPI_C 0x62190
  760. #define MIPI_PORT_EN (1 << 31)
  761. /* Turns on border drawing to allow centered display. */
  762. #define SEL_FLOPPED_HSTX (1 << 23)
  763. #define PASS_FROM_SPHY_TO_AFE (1 << 16)
  764. #define MIPI_BORDER_EN (1 << 15)
  765. #define MIPIA_3LANE_MIPIC_1LANE 0x1
  766. #define MIPIA_2LANE_MIPIC_2LANE 0x2
  767. #define TE_TRIGGER_DSI_PROTOCOL (1 << 2)
  768. #define TE_TRIGGER_GPIO_PIN (1 << 3)
  769. #define MIPI_TE_COUNT 0x61194
  770. /* #define PP_CONTROL 0x61204 */
  771. #define POWER_DOWN_ON_RESET (1 << 1)
  772. /* #define PFIT_CONTROL 0x61230 */
  773. #define PFIT_PIPE_SELECT (3 << 29)
  774. #define PFIT_PIPE_SELECT_SHIFT (29)
  775. /* #define BLC_PWM_CTL 0x61254 */
  776. #define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16)
  777. #define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16)
  778. /* #define PIPEACONF 0x70008 */
  779. #define PIPEACONF_PIPE_STATE (1 << 30)
  780. /* #define DSPACNTR 0x70180 */
  781. #define MRST_DSPABASE 0x7019c
  782. #define MRST_DSPBBASE 0x7119c
  783. #define MDFLD_DSPCBASE 0x7219c
  784. /*
  785. * Moorestown registers.
  786. */
  787. /*
  788. * MIPI IP registers
  789. */
  790. #define MIPIC_REG_OFFSET 0x800
  791. #define DEVICE_READY_REG 0xb000
  792. #define LP_OUTPUT_HOLD (1 << 16)
  793. #define EXIT_ULPS_DEV_READY 0x3
  794. #define LP_OUTPUT_HOLD_RELEASE 0x810000
  795. # define ENTERING_ULPS (2 << 1)
  796. # define EXITING_ULPS (1 << 1)
  797. # define ULPS_MASK (3 << 1)
  798. # define BUS_POSSESSION (1 << 3)
  799. #define INTR_STAT_REG 0xb004
  800. #define RX_SOT_ERROR (1 << 0)
  801. #define RX_SOT_SYNC_ERROR (1 << 1)
  802. #define RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3)
  803. #define RX_LP_TX_SYNC_ERROR (1 << 4)
  804. #define RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5)
  805. #define RX_FALSE_CONTROL_ERROR (1 << 6)
  806. #define RX_ECC_SINGLE_BIT_ERROR (1 << 7)
  807. #define RX_ECC_MULTI_BIT_ERROR (1 << 8)
  808. #define RX_CHECKSUM_ERROR (1 << 9)
  809. #define RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10)
  810. #define RX_DSI_VC_ID_INVALID (1 << 11)
  811. #define TX_FALSE_CONTROL_ERROR (1 << 12)
  812. #define TX_ECC_SINGLE_BIT_ERROR (1 << 13)
  813. #define TX_ECC_MULTI_BIT_ERROR (1 << 14)
  814. #define TX_CHECKSUM_ERROR (1 << 15)
  815. #define TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16)
  816. #define TX_DSI_VC_ID_INVALID (1 << 17)
  817. #define HIGH_CONTENTION (1 << 18)
  818. #define LOW_CONTENTION (1 << 19)
  819. #define DPI_FIFO_UNDER_RUN (1 << 20)
  820. #define HS_TX_TIMEOUT (1 << 21)
  821. #define LP_RX_TIMEOUT (1 << 22)
  822. #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
  823. #define ACK_WITH_NO_ERROR (1 << 24)
  824. #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
  825. #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
  826. #define SPL_PKT_SENT (1 << 30)
  827. #define INTR_EN_REG 0xb008
  828. #define DSI_FUNC_PRG_REG 0xb00c
  829. #define DPI_CHANNEL_NUMBER_POS 0x03
  830. #define DBI_CHANNEL_NUMBER_POS 0x05
  831. #define FMT_DPI_POS 0x07
  832. #define FMT_DBI_POS 0x0A
  833. #define DBI_DATA_WIDTH_POS 0x0D
  834. /* DPI PIXEL FORMATS */
  835. #define RGB_565_FMT 0x01 /* RGB 565 FORMAT */
  836. #define RGB_666_FMT 0x02 /* RGB 666 FORMAT */
  837. #define LRGB_666_FMT 0x03 /* RGB LOOSELY PACKED
  838. * 666 FORMAT
  839. */
  840. #define RGB_888_FMT 0x04 /* RGB 888 FORMAT */
  841. #define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */
  842. #define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */
  843. #define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */
  844. #define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */
  845. #define DBI_NOT_SUPPORTED 0x00 /* command mode
  846. * is not supported
  847. */
  848. #define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */
  849. #define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */
  850. #define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */
  851. #define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */
  852. #define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */
  853. #define HS_TX_TIMEOUT_REG 0xb010
  854. #define LP_RX_TIMEOUT_REG 0xb014
  855. #define TURN_AROUND_TIMEOUT_REG 0xb018
  856. #define DEVICE_RESET_REG 0xb01C
  857. #define DPI_RESOLUTION_REG 0xb020
  858. #define RES_V_POS 0x10
  859. #define DBI_RESOLUTION_REG 0xb024 /* Reserved for MDFLD */
  860. #define HORIZ_SYNC_PAD_COUNT_REG 0xb028
  861. #define HORIZ_BACK_PORCH_COUNT_REG 0xb02C
  862. #define HORIZ_FRONT_PORCH_COUNT_REG 0xb030
  863. #define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034
  864. #define VERT_SYNC_PAD_COUNT_REG 0xb038
  865. #define VERT_BACK_PORCH_COUNT_REG 0xb03c
  866. #define VERT_FRONT_PORCH_COUNT_REG 0xb040
  867. #define HIGH_LOW_SWITCH_COUNT_REG 0xb044
  868. #define DPI_CONTROL_REG 0xb048
  869. #define DPI_SHUT_DOWN (1 << 0)
  870. #define DPI_TURN_ON (1 << 1)
  871. #define DPI_COLOR_MODE_ON (1 << 2)
  872. #define DPI_COLOR_MODE_OFF (1 << 3)
  873. #define DPI_BACK_LIGHT_ON (1 << 4)
  874. #define DPI_BACK_LIGHT_OFF (1 << 5)
  875. #define DPI_LP (1 << 6)
  876. #define DPI_DATA_REG 0xb04c
  877. #define DPI_BACK_LIGHT_ON_DATA 0x07
  878. #define DPI_BACK_LIGHT_OFF_DATA 0x17
  879. #define INIT_COUNT_REG 0xb050
  880. #define MAX_RET_PAK_REG 0xb054
  881. #define VIDEO_FMT_REG 0xb058
  882. #define COMPLETE_LAST_PCKT (1 << 2)
  883. #define EOT_DISABLE_REG 0xb05c
  884. #define ENABLE_CLOCK_STOPPING (1 << 1)
  885. #define LP_BYTECLK_REG 0xb060
  886. #define LP_GEN_DATA_REG 0xb064
  887. #define HS_GEN_DATA_REG 0xb068
  888. #define LP_GEN_CTRL_REG 0xb06C
  889. #define HS_GEN_CTRL_REG 0xb070
  890. #define DCS_CHANNEL_NUMBER_POS 0x6
  891. #define MCS_COMMANDS_POS 0x8
  892. #define WORD_COUNTS_POS 0x8
  893. #define MCS_PARAMETER_POS 0x10
  894. #define GEN_FIFO_STAT_REG 0xb074
  895. #define HS_DATA_FIFO_FULL (1 << 0)
  896. #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
  897. #define HS_DATA_FIFO_EMPTY (1 << 2)
  898. #define LP_DATA_FIFO_FULL (1 << 8)
  899. #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
  900. #define LP_DATA_FIFO_EMPTY (1 << 10)
  901. #define HS_CTRL_FIFO_FULL (1 << 16)
  902. #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
  903. #define HS_CTRL_FIFO_EMPTY (1 << 18)
  904. #define LP_CTRL_FIFO_FULL (1 << 24)
  905. #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
  906. #define LP_CTRL_FIFO_EMPTY (1 << 26)
  907. #define DBI_FIFO_EMPTY (1 << 27)
  908. #define DPI_FIFO_EMPTY (1 << 28)
  909. #define HS_LS_DBI_ENABLE_REG 0xb078
  910. #define TXCLKESC_REG 0xb07c
  911. #define DPHY_PARAM_REG 0xb080
  912. #define DBI_BW_CTRL_REG 0xb084
  913. #define CLK_LANE_SWT_REG 0xb088
  914. /*
  915. * MIPI Adapter registers
  916. */
  917. #define MIPI_CONTROL_REG 0xb104
  918. #define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1))
  919. #define MIPI_DATA_ADDRESS_REG 0xb108
  920. #define MIPI_DATA_LENGTH_REG 0xb10C
  921. #define MIPI_COMMAND_ADDRESS_REG 0xb110
  922. #define MIPI_COMMAND_LENGTH_REG 0xb114
  923. #define MIPI_READ_DATA_RETURN_REG0 0xb118
  924. #define MIPI_READ_DATA_RETURN_REG1 0xb11C
  925. #define MIPI_READ_DATA_RETURN_REG2 0xb120
  926. #define MIPI_READ_DATA_RETURN_REG3 0xb124
  927. #define MIPI_READ_DATA_RETURN_REG4 0xb128
  928. #define MIPI_READ_DATA_RETURN_REG5 0xb12C
  929. #define MIPI_READ_DATA_RETURN_REG6 0xb130
  930. #define MIPI_READ_DATA_RETURN_REG7 0xb134
  931. #define MIPI_READ_DATA_VALID_REG 0xb138
  932. /* DBI COMMANDS */
  933. #define soft_reset 0x01
  934. /*
  935. * The display module performs a software reset.
  936. * Registers are written with their SW Reset default values.
  937. */
  938. #define get_power_mode 0x0a
  939. /*
  940. * The display module returns the current power mode
  941. */
  942. #define get_address_mode 0x0b
  943. /*
  944. * The display module returns the current status.
  945. */
  946. #define get_pixel_format 0x0c
  947. /*
  948. * This command gets the pixel format for the RGB image data
  949. * used by the interface.
  950. */
  951. #define get_display_mode 0x0d
  952. /*
  953. * The display module returns the Display Image Mode status.
  954. */
  955. #define get_signal_mode 0x0e
  956. /*
  957. * The display module returns the Display Signal Mode.
  958. */
  959. #define get_diagnostic_result 0x0f
  960. /*
  961. * The display module returns the self-diagnostic results following
  962. * a Sleep Out command.
  963. */
  964. #define enter_sleep_mode 0x10
  965. /*
  966. * This command causes the display module to enter the Sleep mode.
  967. * In this mode, all unnecessary blocks inside the display module are
  968. * disabled except interface communication. This is the lowest power
  969. * mode the display module supports.
  970. */
  971. #define exit_sleep_mode 0x11
  972. /*
  973. * This command causes the display module to exit Sleep mode.
  974. * All blocks inside the display module are enabled.
  975. */
  976. #define enter_partial_mode 0x12
  977. /*
  978. * This command causes the display module to enter the Partial Display
  979. * Mode. The Partial Display Mode window is described by the
  980. * set_partial_area command.
  981. */
  982. #define enter_normal_mode 0x13
  983. /*
  984. * This command causes the display module to enter the Normal mode.
  985. * Normal Mode is defined as Partial Display mode and Scroll mode are off
  986. */
  987. #define exit_invert_mode 0x20
  988. /*
  989. * This command causes the display module to stop inverting the image
  990. * data on the display device. The frame memory contents remain unchanged.
  991. * No status bits are changed.
  992. */
  993. #define enter_invert_mode 0x21
  994. /*
  995. * This command causes the display module to invert the image data only on
  996. * the display device. The frame memory contents remain unchanged.
  997. * No status bits are changed.
  998. */
  999. #define set_gamma_curve 0x26
  1000. /*
  1001. * This command selects the desired gamma curve for the display device.
  1002. * Four fixed gamma curves are defined in section DCS spec.
  1003. */
  1004. #define set_display_off 0x28
  1005. /* ************************************************************************* *\
  1006. This command causes the display module to stop displaying the image data
  1007. on the display device. The frame memory contents remain unchanged.
  1008. No status bits are changed.
  1009. \* ************************************************************************* */
  1010. #define set_display_on 0x29
  1011. /* ************************************************************************* *\
  1012. This command causes the display module to start displaying the image data
  1013. on the display device. The frame memory contents remain unchanged.
  1014. No status bits are changed.
  1015. \* ************************************************************************* */
  1016. #define set_column_address 0x2a
  1017. /*
  1018. * This command defines the column extent of the frame memory accessed by
  1019. * the hostprocessor with the read_memory_continue and
  1020. * write_memory_continue commands.
  1021. * No status bits are changed.
  1022. */
  1023. #define set_page_addr 0x2b
  1024. /*
  1025. * This command defines the page extent of the frame memory accessed by
  1026. * the host processor with the write_memory_continue and
  1027. * read_memory_continue command.
  1028. * No status bits are changed.
  1029. */
  1030. #define write_mem_start 0x2c
  1031. /*
  1032. * This command transfers image data from the host processor to the
  1033. * display modules frame memory starting at the pixel location specified
  1034. * by preceding set_column_address and set_page_address commands.
  1035. */
  1036. #define set_partial_area 0x30
  1037. /*
  1038. * This command defines the Partial Display mode s display area.
  1039. * There are two parameters associated with this command, the first
  1040. * defines the Start Row (SR) and the second the End Row (ER). SR and ER
  1041. * refer to the Frame Memory Line Pointer.
  1042. */
  1043. #define set_scroll_area 0x33
  1044. /*
  1045. * This command defines the display modules Vertical Scrolling Area.
  1046. */
  1047. #define set_tear_off 0x34
  1048. /*
  1049. * This command turns off the display modules Tearing Effect output
  1050. * signal on the TE signal line.
  1051. */
  1052. #define set_tear_on 0x35
  1053. /*
  1054. * This command turns on the display modules Tearing Effect output signal
  1055. * on the TE signal line.
  1056. */
  1057. #define set_address_mode 0x36
  1058. /*
  1059. * This command sets the data order for transfers from the host processor
  1060. * to display modules frame memory,bits B[7:5] and B3, and from the
  1061. * display modules frame memory to the display device, bits B[2:0] and B4.
  1062. */
  1063. #define set_scroll_start 0x37
  1064. /*
  1065. * This command sets the start of the vertical scrolling area in the frame
  1066. * memory. The vertical scrolling area is fully defined when this command
  1067. * is used with the set_scroll_area command The set_scroll_start command
  1068. * has one parameter, the Vertical Scroll Pointer. The VSP defines the
  1069. * line in the frame memory that is written to the display device as the
  1070. * first line of the vertical scroll area.
  1071. */
  1072. #define exit_idle_mode 0x38
  1073. /*
  1074. * This command causes the display module to exit Idle mode.
  1075. */
  1076. #define enter_idle_mode 0x39
  1077. /*
  1078. * This command causes the display module to enter Idle Mode.
  1079. * In Idle Mode, color expression is reduced. Colors are shown on the
  1080. * display device using the MSB of each of the R, G and B color
  1081. * components in the frame memory
  1082. */
  1083. #define set_pixel_format 0x3a
  1084. /*
  1085. * This command sets the pixel format for the RGB image data used by the
  1086. * interface.
  1087. * Bits D[6:4] DPI Pixel Format Definition
  1088. * Bits D[2:0] DBI Pixel Format Definition
  1089. * Bits D7 and D3 are not used.
  1090. */
  1091. #define DCS_PIXEL_FORMAT_3bpp 0x1
  1092. #define DCS_PIXEL_FORMAT_8bpp 0x2
  1093. #define DCS_PIXEL_FORMAT_12bpp 0x3
  1094. #define DCS_PIXEL_FORMAT_16bpp 0x5
  1095. #define DCS_PIXEL_FORMAT_18bpp 0x6
  1096. #define DCS_PIXEL_FORMAT_24bpp 0x7
  1097. #define write_mem_cont 0x3c
  1098. /*
  1099. * This command transfers image data from the host processor to the
  1100. * display module's frame memory continuing from the pixel location
  1101. * following the previous write_memory_continue or write_memory_start
  1102. * command.
  1103. */
  1104. #define set_tear_scanline 0x44
  1105. /*
  1106. * This command turns on the display modules Tearing Effect output signal
  1107. * on the TE signal line when the display module reaches line N.
  1108. */
  1109. #define get_scanline 0x45
  1110. /*
  1111. * The display module returns the current scanline, N, used to update the
  1112. * display device. The total number of scanlines on a display device is
  1113. * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as
  1114. * the first line of V Sync and is denoted as Line 0.
  1115. * When in Sleep Mode, the value returned by get_scanline is undefined.
  1116. */
  1117. /* MCS or Generic COMMANDS */
  1118. /* MCS/generic data type */
  1119. #define GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */
  1120. #define GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */
  1121. #define GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */
  1122. #define GEN_READ_0 0x04 /* generic read, no parameters */
  1123. #define GEN_READ_1 0x14 /* generic read, 1 parameters */
  1124. #define GEN_READ_2 0x24 /* generic read, 2 parameters */
  1125. #define GEN_LONG_WRITE 0x29 /* generic long write */
  1126. #define MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */
  1127. #define MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */
  1128. #define MCS_READ 0x06 /* MCS read, no parameters */
  1129. #define MCS_LONG_WRITE 0x39 /* MCS long write */
  1130. /* MCS/generic commands */
  1131. /* TPO MCS */
  1132. #define write_display_profile 0x50
  1133. #define write_display_brightness 0x51
  1134. #define write_ctrl_display 0x53
  1135. #define write_ctrl_cabc 0x55
  1136. #define UI_IMAGE 0x01
  1137. #define STILL_IMAGE 0x02
  1138. #define MOVING_IMAGE 0x03
  1139. #define write_hysteresis 0x57
  1140. #define write_gamma_setting 0x58
  1141. #define write_cabc_min_bright 0x5e
  1142. #define write_kbbc_profile 0x60
  1143. /* TMD MCS */
  1144. #define tmd_write_display_brightness 0x8c
  1145. /*
  1146. * This command is used to control ambient light, panel backlight
  1147. * brightness and gamma settings.
  1148. */
  1149. #define BRIGHT_CNTL_BLOCK_ON (1 << 5)
  1150. #define AMBIENT_LIGHT_SENSE_ON (1 << 4)
  1151. #define DISPLAY_DIMMING_ON (1 << 3)
  1152. #define BACKLIGHT_ON (1 << 2)
  1153. #define DISPLAY_BRIGHTNESS_AUTO (1 << 1)
  1154. #define GAMMA_AUTO (1 << 0)
  1155. /* DCS Interface Pixel Formats */
  1156. #define DCS_PIXEL_FORMAT_3BPP 0x1
  1157. #define DCS_PIXEL_FORMAT_8BPP 0x2
  1158. #define DCS_PIXEL_FORMAT_12BPP 0x3
  1159. #define DCS_PIXEL_FORMAT_16BPP 0x5
  1160. #define DCS_PIXEL_FORMAT_18BPP 0x6
  1161. #define DCS_PIXEL_FORMAT_24BPP 0x7
  1162. /* ONE PARAMETER READ DATA */
  1163. #define addr_mode_data 0xfc
  1164. #define diag_res_data 0x00
  1165. #define disp_mode_data 0x23
  1166. #define pxl_fmt_data 0x77
  1167. #define pwr_mode_data 0x74
  1168. #define sig_mode_data 0x00
  1169. /* TWO PARAMETERS READ DATA */
  1170. #define scanline_data1 0xff
  1171. #define scanline_data2 0xff
  1172. #define NON_BURST_MODE_SYNC_PULSE 0x01 /* Non Burst Mode
  1173. * with Sync Pulse
  1174. */
  1175. #define NON_BURST_MODE_SYNC_EVENTS 0x02 /* Non Burst Mode
  1176. * with Sync events
  1177. */
  1178. #define BURST_MODE 0x03 /* Burst Mode */
  1179. #define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */
  1180. /* Allocate at least
  1181. * 0x100 Byte with 32
  1182. * byte alignment
  1183. */
  1184. #define DBI_DATA_BUFFER_SIZE 0x120 /* Allocate at least
  1185. * 0x100 Byte with 32
  1186. * byte alignment
  1187. */
  1188. #define DBI_CB_TIME_OUT 0xFFFF
  1189. #define GEN_FB_TIME_OUT 2000
  1190. #define SKU_83 0x01
  1191. #define SKU_100 0x02
  1192. #define SKU_100L 0x04
  1193. #define SKU_BYPASS 0x08
  1194. /* Some handy macros for playing with bitfields. */
  1195. #define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
  1196. #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK)
  1197. #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
  1198. #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
  1199. /* PCI config space */
  1200. #define SB_PCKT 0x02100 /* cedarview */
  1201. # define SB_OPCODE_MASK PSB_MASK(31, 16)
  1202. # define SB_OPCODE_SHIFT 16
  1203. # define SB_OPCODE_READ 0
  1204. # define SB_OPCODE_WRITE 1
  1205. # define SB_DEST_MASK PSB_MASK(15, 8)
  1206. # define SB_DEST_SHIFT 8
  1207. # define SB_DEST_DPLL 0x88
  1208. # define SB_BYTE_ENABLE_MASK PSB_MASK(7, 4)
  1209. # define SB_BYTE_ENABLE_SHIFT 4
  1210. # define SB_BUSY (1 << 0)
  1211. #define DSPCLK_GATE_D 0x6200
  1212. # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */
  1213. # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
  1214. # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6)
  1215. # define DPUNIT_PIPEB_GATE_DISABLE (1 << 30)
  1216. # define DPUNIT_PIPEA_GATE_DISABLE (1 << 25)
  1217. # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)
  1218. # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13)
  1219. #define RAMCLK_GATE_D 0x6210
  1220. /* 32-bit value read/written from the DPIO reg. */
  1221. #define SB_DATA 0x02104 /* cedarview */
  1222. /* 32-bit address of the DPIO reg to be read/written. */
  1223. #define SB_ADDR 0x02108 /* cedarview */
  1224. #define DPIO_CFG 0x02110 /* cedarview */
  1225. # define DPIO_MODE_SELECT_1 (1 << 3)
  1226. # define DPIO_MODE_SELECT_0 (1 << 2)
  1227. # define DPIO_SFR_BYPASS (1 << 1)
  1228. /* reset is active low */
  1229. # define DPIO_CMN_RESET_N (1 << 0)
  1230. /* Cedarview sideband registers */
  1231. #define _SB_M_A 0x8008
  1232. #define _SB_M_B 0x8028
  1233. #define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B)
  1234. # define SB_M_DIVIDER_MASK (0xFF << 24)
  1235. # define SB_M_DIVIDER_SHIFT 24
  1236. #define _SB_N_VCO_A 0x8014
  1237. #define _SB_N_VCO_B 0x8034
  1238. #define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B)
  1239. #define SB_N_VCO_SEL_MASK PSB_MASK(31, 30)
  1240. #define SB_N_VCO_SEL_SHIFT 30
  1241. #define SB_N_DIVIDER_MASK PSB_MASK(29, 26)
  1242. #define SB_N_DIVIDER_SHIFT 26
  1243. #define SB_N_CB_TUNE_MASK PSB_MASK(25, 24)
  1244. #define SB_N_CB_TUNE_SHIFT 24
  1245. /* the bit 14:13 is used to select between the different reference clock for Pipe A/B */
  1246. #define SB_REF_DPLLA 0x8010
  1247. #define SB_REF_DPLLB 0x8030
  1248. #define REF_CLK_MASK (0x3 << 13)
  1249. #define REF_CLK_CORE (0 << 13)
  1250. #define REF_CLK_DPLL (1 << 13)
  1251. #define REF_CLK_DPLLA (2 << 13)
  1252. /* For the DPLL B, it will use the reference clk from DPLL A when using (2 << 13) */
  1253. #define _SB_REF_A 0x8018
  1254. #define _SB_REF_B 0x8038
  1255. #define SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B)
  1256. #define _SB_P_A 0x801c
  1257. #define _SB_P_B 0x803c
  1258. #define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B)
  1259. #define SB_P2_DIVIDER_MASK PSB_MASK(31, 30)
  1260. #define SB_P2_DIVIDER_SHIFT 30
  1261. #define SB_P2_10 0 /* HDMI, DP, DAC */
  1262. #define SB_P2_5 1 /* DAC */
  1263. #define SB_P2_14 2 /* LVDS single */
  1264. #define SB_P2_7 3 /* LVDS double */
  1265. #define SB_P1_DIVIDER_MASK PSB_MASK(15, 12)
  1266. #define SB_P1_DIVIDER_SHIFT 12
  1267. #define PSB_LANE0 0x120
  1268. #define PSB_LANE1 0x220
  1269. #define PSB_LANE2 0x2320
  1270. #define PSB_LANE3 0x2420
  1271. #define LANE_PLL_MASK (0x7 << 20)
  1272. #define LANE_PLL_ENABLE (0x3 << 20)
  1273. #define LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21))
  1274. #define DP_B 0x64100
  1275. #define DP_C 0x64200
  1276. #define DP_PORT_EN (1 << 31)
  1277. #define DP_PIPEB_SELECT (1 << 30)
  1278. #define DP_PIPE_MASK (1 << 30)
  1279. /* Link training mode - select a suitable mode for each stage */
  1280. #define DP_LINK_TRAIN_PAT_1 (0 << 28)
  1281. #define DP_LINK_TRAIN_PAT_2 (1 << 28)
  1282. #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
  1283. #define DP_LINK_TRAIN_OFF (3 << 28)
  1284. #define DP_LINK_TRAIN_MASK (3 << 28)
  1285. #define DP_LINK_TRAIN_SHIFT 28
  1286. /* Signal voltages. These are mostly controlled by the other end */
  1287. #define DP_VOLTAGE_0_4 (0 << 25)
  1288. #define DP_VOLTAGE_0_6 (1 << 25)
  1289. #define DP_VOLTAGE_0_8 (2 << 25)
  1290. #define DP_VOLTAGE_1_2 (3 << 25)
  1291. #define DP_VOLTAGE_MASK (7 << 25)
  1292. #define DP_VOLTAGE_SHIFT 25
  1293. /* Signal pre-emphasis levels, like voltages, the other end tells us what
  1294. * they want
  1295. */
  1296. #define DP_PRE_EMPHASIS_0 (0 << 22)
  1297. #define DP_PRE_EMPHASIS_3_5 (1 << 22)
  1298. #define DP_PRE_EMPHASIS_6 (2 << 22)
  1299. #define DP_PRE_EMPHASIS_9_5 (3 << 22)
  1300. #define DP_PRE_EMPHASIS_MASK (7 << 22)
  1301. #define DP_PRE_EMPHASIS_SHIFT 22
  1302. /* How many wires to use. I guess 3 was too hard */
  1303. #define DP_PORT_WIDTH_1 (0 << 19)
  1304. #define DP_PORT_WIDTH_2 (1 << 19)
  1305. #define DP_PORT_WIDTH_4 (3 << 19)
  1306. #define DP_PORT_WIDTH_MASK (7 << 19)
  1307. /* Mystic DPCD version 1.1 special mode */
  1308. #define DP_ENHANCED_FRAMING (1 << 18)
  1309. /** locked once port is enabled */
  1310. #define DP_PORT_REVERSAL (1 << 15)
  1311. /** sends the clock on lane 15 of the PEG for debug */
  1312. #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
  1313. #define DP_SCRAMBLING_DISABLE (1 << 12)
  1314. #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
  1315. /** limit RGB values to avoid confusing TVs */
  1316. #define DP_COLOR_RANGE_16_235 (1 << 8)
  1317. /** Turn on the audio link */
  1318. #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
  1319. /** vs and hs sync polarity */
  1320. #define DP_SYNC_VS_HIGH (1 << 4)
  1321. #define DP_SYNC_HS_HIGH (1 << 3)
  1322. /** A fantasy */
  1323. #define DP_DETECTED (1 << 2)
  1324. /** The aux channel provides a way to talk to the
  1325. * signal sink for DDC etc. Max packet size supported
  1326. * is 20 bytes in each direction, hence the 5 fixed
  1327. * data registers
  1328. */
  1329. #define DPB_AUX_CH_CTL 0x64110
  1330. #define DPB_AUX_CH_DATA1 0x64114
  1331. #define DPB_AUX_CH_DATA2 0x64118
  1332. #define DPB_AUX_CH_DATA3 0x6411c
  1333. #define DPB_AUX_CH_DATA4 0x64120
  1334. #define DPB_AUX_CH_DATA5 0x64124
  1335. #define DPC_AUX_CH_CTL 0x64210
  1336. #define DPC_AUX_CH_DATA1 0x64214
  1337. #define DPC_AUX_CH_DATA2 0x64218
  1338. #define DPC_AUX_CH_DATA3 0x6421c
  1339. #define DPC_AUX_CH_DATA4 0x64220
  1340. #define DPC_AUX_CH_DATA5 0x64224
  1341. #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
  1342. #define DP_AUX_CH_CTL_DONE (1 << 30)
  1343. #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
  1344. #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
  1345. #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
  1346. #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
  1347. #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
  1348. #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
  1349. #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
  1350. #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
  1351. #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
  1352. #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
  1353. #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
  1354. #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
  1355. #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
  1356. #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
  1357. #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
  1358. #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
  1359. #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
  1360. #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
  1361. #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
  1362. /*
  1363. * Computing GMCH M and N values for the Display Port link
  1364. *
  1365. * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
  1366. *
  1367. * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
  1368. *
  1369. * The GMCH value is used internally
  1370. *
  1371. * bytes_per_pixel is the number of bytes coming out of the plane,
  1372. * which is after the LUTs, so we want the bytes for our color format.
  1373. * For our current usage, this is always 3, one byte for R, G and B.
  1374. */
  1375. #define _PIPEA_GMCH_DATA_M 0x70050
  1376. #define _PIPEB_GMCH_DATA_M 0x71050
  1377. /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
  1378. #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
  1379. #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
  1380. #define PIPE_GMCH_DATA_M_MASK (0xffffff)
  1381. #define _PIPEA_GMCH_DATA_N 0x70054
  1382. #define _PIPEB_GMCH_DATA_N 0x71054
  1383. #define PIPE_GMCH_DATA_N_MASK (0xffffff)
  1384. /*
  1385. * Computing Link M and N values for the Display Port link
  1386. *
  1387. * Link M / N = pixel_clock / ls_clk
  1388. *
  1389. * (the DP spec calls pixel_clock the 'strm_clk')
  1390. *
  1391. * The Link value is transmitted in the Main Stream
  1392. * Attributes and VB-ID.
  1393. */
  1394. #define _PIPEA_DP_LINK_M 0x70060
  1395. #define _PIPEB_DP_LINK_M 0x71060
  1396. #define PIPEA_DP_LINK_M_MASK (0xffffff)
  1397. #define _PIPEA_DP_LINK_N 0x70064
  1398. #define _PIPEB_DP_LINK_N 0x71064
  1399. #define PIPEA_DP_LINK_N_MASK (0xffffff)
  1400. #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
  1401. #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
  1402. #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
  1403. #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
  1404. #define PIPE_BPC_MASK (7 << 5)
  1405. #define PIPE_8BPC (0 << 5)
  1406. #define PIPE_10BPC (1 << 5)
  1407. #define PIPE_6BPC (2 << 5)
  1408. #endif