oaktrail_lvds_i2c.c 4.5 KB

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  1. /*
  2. * Copyright (c) 2002-2010, Intel Corporation.
  3. * Copyright (c) 2014 ATRON electronic GmbH
  4. * Author: Jan Safrata <jan.nikitenko@gmail.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  19. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. *
  24. */
  25. #include <linux/delay.h>
  26. #include <linux/i2c-algo-bit.h>
  27. #include <linux/i2c.h>
  28. #include <linux/init.h>
  29. #include <linux/io.h>
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/pci.h>
  33. #include <linux/types.h>
  34. #include "psb_drv.h"
  35. #include "psb_intel_reg.h"
  36. /*
  37. * LPC GPIO based I2C bus for LVDS of Atom E6xx
  38. */
  39. /*-----------------------------------------------------------------------------
  40. * LPC Register Offsets. Used for LVDS GPIO Bit Bashing. Registers are part
  41. * Atom E6xx [D31:F0]
  42. ----------------------------------------------------------------------------*/
  43. #define RGEN 0x20
  44. #define RGIO 0x24
  45. #define RGLVL 0x28
  46. #define RGTPE 0x2C
  47. #define RGTNE 0x30
  48. #define RGGPE 0x34
  49. #define RGSMI 0x38
  50. #define RGTS 0x3C
  51. /* The LVDS GPIO clock lines are GPIOSUS[3]
  52. * The LVDS GPIO data lines are GPIOSUS[4]
  53. */
  54. #define GPIO_CLOCK 0x08
  55. #define GPIO_DATA 0x10
  56. #define LPC_READ_REG(chan, r) inl((chan)->reg + (r))
  57. #define LPC_WRITE_REG(chan, r, val) outl((val), (chan)->reg + (r))
  58. static int get_clock(void *data)
  59. {
  60. struct psb_intel_i2c_chan *chan = data;
  61. u32 val, tmp;
  62. val = LPC_READ_REG(chan, RGIO);
  63. val |= GPIO_CLOCK;
  64. LPC_WRITE_REG(chan, RGIO, val);
  65. tmp = LPC_READ_REG(chan, RGLVL);
  66. val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0;
  67. return val;
  68. }
  69. static int get_data(void *data)
  70. {
  71. struct psb_intel_i2c_chan *chan = data;
  72. u32 val, tmp;
  73. val = LPC_READ_REG(chan, RGIO);
  74. val |= GPIO_DATA;
  75. LPC_WRITE_REG(chan, RGIO, val);
  76. tmp = LPC_READ_REG(chan, RGLVL);
  77. val = (LPC_READ_REG(chan, RGLVL) & GPIO_DATA) ? 1 : 0;
  78. return val;
  79. }
  80. static void set_clock(void *data, int state_high)
  81. {
  82. struct psb_intel_i2c_chan *chan = data;
  83. u32 val;
  84. if (state_high) {
  85. val = LPC_READ_REG(chan, RGIO);
  86. val |= GPIO_CLOCK;
  87. LPC_WRITE_REG(chan, RGIO, val);
  88. } else {
  89. val = LPC_READ_REG(chan, RGIO);
  90. val &= ~GPIO_CLOCK;
  91. LPC_WRITE_REG(chan, RGIO, val);
  92. val = LPC_READ_REG(chan, RGLVL);
  93. val &= ~GPIO_CLOCK;
  94. LPC_WRITE_REG(chan, RGLVL, val);
  95. }
  96. }
  97. static void set_data(void *data, int state_high)
  98. {
  99. struct psb_intel_i2c_chan *chan = data;
  100. u32 val;
  101. if (state_high) {
  102. val = LPC_READ_REG(chan, RGIO);
  103. val |= GPIO_DATA;
  104. LPC_WRITE_REG(chan, RGIO, val);
  105. } else {
  106. val = LPC_READ_REG(chan, RGIO);
  107. val &= ~GPIO_DATA;
  108. LPC_WRITE_REG(chan, RGIO, val);
  109. val = LPC_READ_REG(chan, RGLVL);
  110. val &= ~GPIO_DATA;
  111. LPC_WRITE_REG(chan, RGLVL, val);
  112. }
  113. }
  114. void oaktrail_lvds_i2c_init(struct drm_encoder *encoder)
  115. {
  116. struct drm_device *dev = encoder->dev;
  117. struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
  118. struct drm_psb_private *dev_priv = dev->dev_private;
  119. struct psb_intel_i2c_chan *chan;
  120. chan = kzalloc(sizeof(struct psb_intel_i2c_chan), GFP_KERNEL);
  121. if (!chan)
  122. return;
  123. chan->drm_dev = dev;
  124. chan->reg = dev_priv->lpc_gpio_base;
  125. strncpy(chan->adapter.name, "gma500 LPC", I2C_NAME_SIZE - 1);
  126. chan->adapter.owner = THIS_MODULE;
  127. chan->adapter.algo_data = &chan->algo;
  128. chan->adapter.dev.parent = &dev->pdev->dev;
  129. chan->algo.setsda = set_data;
  130. chan->algo.setscl = set_clock;
  131. chan->algo.getsda = get_data;
  132. chan->algo.getscl = get_clock;
  133. chan->algo.udelay = 100;
  134. chan->algo.timeout = usecs_to_jiffies(2200);
  135. chan->algo.data = chan;
  136. i2c_set_adapdata(&chan->adapter, chan);
  137. set_data(chan, 1);
  138. set_clock(chan, 1);
  139. udelay(50);
  140. if (i2c_bit_add_bus(&chan->adapter)) {
  141. kfree(chan);
  142. return;
  143. }
  144. gma_encoder->ddc_bus = chan;
  145. }