oaktrail_crtc.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright © 2009 Intel Corporation
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/i2c.h>
  7. #include <linux/pm_runtime.h>
  8. #include <drm/drm_fourcc.h>
  9. #include "framebuffer.h"
  10. #include "gma_display.h"
  11. #include "power.h"
  12. #include "psb_drv.h"
  13. #include "psb_intel_drv.h"
  14. #include "psb_intel_reg.h"
  15. #define MRST_LIMIT_LVDS_100L 0
  16. #define MRST_LIMIT_LVDS_83 1
  17. #define MRST_LIMIT_LVDS_100 2
  18. #define MRST_LIMIT_SDVO 3
  19. #define MRST_DOT_MIN 19750
  20. #define MRST_DOT_MAX 120000
  21. #define MRST_M_MIN_100L 20
  22. #define MRST_M_MIN_100 10
  23. #define MRST_M_MIN_83 12
  24. #define MRST_M_MAX_100L 34
  25. #define MRST_M_MAX_100 17
  26. #define MRST_M_MAX_83 20
  27. #define MRST_P1_MIN 2
  28. #define MRST_P1_MAX_0 7
  29. #define MRST_P1_MAX_1 8
  30. static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
  31. struct drm_crtc *crtc, int target,
  32. int refclk, struct gma_clock_t *best_clock);
  33. static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
  34. struct drm_crtc *crtc, int target,
  35. int refclk, struct gma_clock_t *best_clock);
  36. static const struct gma_limit_t mrst_limits[] = {
  37. { /* MRST_LIMIT_LVDS_100L */
  38. .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
  39. .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L},
  40. .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
  41. .find_pll = mrst_lvds_find_best_pll,
  42. },
  43. { /* MRST_LIMIT_LVDS_83L */
  44. .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
  45. .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83},
  46. .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
  47. .find_pll = mrst_lvds_find_best_pll,
  48. },
  49. { /* MRST_LIMIT_LVDS_100 */
  50. .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
  51. .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100},
  52. .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
  53. .find_pll = mrst_lvds_find_best_pll,
  54. },
  55. { /* MRST_LIMIT_SDVO */
  56. .vco = {.min = 1400000, .max = 2800000},
  57. .n = {.min = 3, .max = 7},
  58. .m = {.min = 80, .max = 137},
  59. .p1 = {.min = 1, .max = 2},
  60. .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 10},
  61. .find_pll = mrst_sdvo_find_best_pll,
  62. },
  63. };
  64. #define MRST_M_MIN 10
  65. static const u32 oaktrail_m_converts[] = {
  66. 0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C,
  67. 0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25,
  68. 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
  69. };
  70. static const struct gma_limit_t *mrst_limit(struct drm_crtc *crtc,
  71. int refclk)
  72. {
  73. const struct gma_limit_t *limit = NULL;
  74. struct drm_device *dev = crtc->dev;
  75. struct drm_psb_private *dev_priv = dev->dev_private;
  76. if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
  77. || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
  78. switch (dev_priv->core_freq) {
  79. case 100:
  80. limit = &mrst_limits[MRST_LIMIT_LVDS_100L];
  81. break;
  82. case 166:
  83. limit = &mrst_limits[MRST_LIMIT_LVDS_83];
  84. break;
  85. case 200:
  86. limit = &mrst_limits[MRST_LIMIT_LVDS_100];
  87. break;
  88. }
  89. } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  90. limit = &mrst_limits[MRST_LIMIT_SDVO];
  91. } else {
  92. limit = NULL;
  93. dev_err(dev->dev, "mrst_limit Wrong display type.\n");
  94. }
  95. return limit;
  96. }
  97. /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
  98. static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock)
  99. {
  100. clock->dot = (refclk * clock->m) / (14 * clock->p1);
  101. }
  102. static void mrst_print_pll(struct gma_clock_t *clock)
  103. {
  104. DRM_DEBUG_DRIVER("dotclock=%d, m=%d, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n",
  105. clock->dot, clock->m, clock->m1, clock->m2, clock->n,
  106. clock->p1, clock->p2);
  107. }
  108. static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
  109. struct drm_crtc *crtc, int target,
  110. int refclk, struct gma_clock_t *best_clock)
  111. {
  112. struct gma_clock_t clock;
  113. u32 target_vco, actual_freq;
  114. s32 freq_error, min_error = 100000;
  115. memset(best_clock, 0, sizeof(*best_clock));
  116. memset(&clock, 0, sizeof(clock));
  117. for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
  118. for (clock.n = limit->n.min; clock.n <= limit->n.max;
  119. clock.n++) {
  120. for (clock.p1 = limit->p1.min;
  121. clock.p1 <= limit->p1.max; clock.p1++) {
  122. /* p2 value always stored in p2_slow on SDVO */
  123. clock.p = clock.p1 * limit->p2.p2_slow;
  124. target_vco = target * clock.p;
  125. /* VCO will increase at this point so break */
  126. if (target_vco > limit->vco.max)
  127. break;
  128. if (target_vco < limit->vco.min)
  129. continue;
  130. actual_freq = (refclk * clock.m) /
  131. (clock.n * clock.p);
  132. freq_error = 10000 -
  133. ((target * 10000) / actual_freq);
  134. if (freq_error < -min_error) {
  135. /* freq_error will start to decrease at
  136. this point so break */
  137. break;
  138. }
  139. if (freq_error < 0)
  140. freq_error = -freq_error;
  141. if (freq_error < min_error) {
  142. min_error = freq_error;
  143. *best_clock = clock;
  144. }
  145. }
  146. }
  147. if (min_error == 0)
  148. break;
  149. }
  150. return min_error == 0;
  151. }
  152. /**
  153. * Returns a set of divisors for the desired target clock with the given refclk,
  154. * or FALSE. Divisor values are the actual divisors for
  155. */
  156. static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
  157. struct drm_crtc *crtc, int target,
  158. int refclk, struct gma_clock_t *best_clock)
  159. {
  160. struct gma_clock_t clock;
  161. int err = target;
  162. memset(best_clock, 0, sizeof(*best_clock));
  163. memset(&clock, 0, sizeof(clock));
  164. for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
  165. for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
  166. clock.p1++) {
  167. int this_err;
  168. mrst_lvds_clock(refclk, &clock);
  169. this_err = abs(clock.dot - target);
  170. if (this_err < err) {
  171. *best_clock = clock;
  172. err = this_err;
  173. }
  174. }
  175. }
  176. return err != target;
  177. }
  178. /**
  179. * Sets the power management mode of the pipe and plane.
  180. *
  181. * This code should probably grow support for turning the cursor off and back
  182. * on appropriately at the same time as we're turning the pipe off/on.
  183. */
  184. static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
  185. {
  186. struct drm_device *dev = crtc->dev;
  187. struct drm_psb_private *dev_priv = dev->dev_private;
  188. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  189. int pipe = gma_crtc->pipe;
  190. const struct psb_offset *map = &dev_priv->regmap[pipe];
  191. u32 temp;
  192. int i;
  193. int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
  194. if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
  195. oaktrail_crtc_hdmi_dpms(crtc, mode);
  196. return;
  197. }
  198. if (!gma_power_begin(dev, true))
  199. return;
  200. /* XXX: When our outputs are all unaware of DPMS modes other than off
  201. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  202. */
  203. switch (mode) {
  204. case DRM_MODE_DPMS_ON:
  205. case DRM_MODE_DPMS_STANDBY:
  206. case DRM_MODE_DPMS_SUSPEND:
  207. for (i = 0; i <= need_aux; i++) {
  208. /* Enable the DPLL */
  209. temp = REG_READ_WITH_AUX(map->dpll, i);
  210. if ((temp & DPLL_VCO_ENABLE) == 0) {
  211. REG_WRITE_WITH_AUX(map->dpll, temp, i);
  212. REG_READ_WITH_AUX(map->dpll, i);
  213. /* Wait for the clocks to stabilize. */
  214. udelay(150);
  215. REG_WRITE_WITH_AUX(map->dpll,
  216. temp | DPLL_VCO_ENABLE, i);
  217. REG_READ_WITH_AUX(map->dpll, i);
  218. /* Wait for the clocks to stabilize. */
  219. udelay(150);
  220. REG_WRITE_WITH_AUX(map->dpll,
  221. temp | DPLL_VCO_ENABLE, i);
  222. REG_READ_WITH_AUX(map->dpll, i);
  223. /* Wait for the clocks to stabilize. */
  224. udelay(150);
  225. }
  226. /* Enable the pipe */
  227. temp = REG_READ_WITH_AUX(map->conf, i);
  228. if ((temp & PIPEACONF_ENABLE) == 0) {
  229. REG_WRITE_WITH_AUX(map->conf,
  230. temp | PIPEACONF_ENABLE, i);
  231. }
  232. /* Enable the plane */
  233. temp = REG_READ_WITH_AUX(map->cntr, i);
  234. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  235. REG_WRITE_WITH_AUX(map->cntr,
  236. temp | DISPLAY_PLANE_ENABLE,
  237. i);
  238. /* Flush the plane changes */
  239. REG_WRITE_WITH_AUX(map->base,
  240. REG_READ_WITH_AUX(map->base, i), i);
  241. }
  242. }
  243. gma_crtc_load_lut(crtc);
  244. /* Give the overlay scaler a chance to enable
  245. if it's on this pipe */
  246. /* psb_intel_crtc_dpms_video(crtc, true); TODO */
  247. break;
  248. case DRM_MODE_DPMS_OFF:
  249. /* Give the overlay scaler a chance to disable
  250. * if it's on this pipe */
  251. /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
  252. for (i = 0; i <= need_aux; i++) {
  253. /* Disable the VGA plane that we never use */
  254. REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i);
  255. /* Disable display plane */
  256. temp = REG_READ_WITH_AUX(map->cntr, i);
  257. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  258. REG_WRITE_WITH_AUX(map->cntr,
  259. temp & ~DISPLAY_PLANE_ENABLE, i);
  260. /* Flush the plane changes */
  261. REG_WRITE_WITH_AUX(map->base,
  262. REG_READ(map->base), i);
  263. REG_READ_WITH_AUX(map->base, i);
  264. }
  265. /* Next, disable display pipes */
  266. temp = REG_READ_WITH_AUX(map->conf, i);
  267. if ((temp & PIPEACONF_ENABLE) != 0) {
  268. REG_WRITE_WITH_AUX(map->conf,
  269. temp & ~PIPEACONF_ENABLE, i);
  270. REG_READ_WITH_AUX(map->conf, i);
  271. }
  272. /* Wait for for the pipe disable to take effect. */
  273. gma_wait_for_vblank(dev);
  274. temp = REG_READ_WITH_AUX(map->dpll, i);
  275. if ((temp & DPLL_VCO_ENABLE) != 0) {
  276. REG_WRITE_WITH_AUX(map->dpll,
  277. temp & ~DPLL_VCO_ENABLE, i);
  278. REG_READ_WITH_AUX(map->dpll, i);
  279. }
  280. /* Wait for the clocks to turn off. */
  281. udelay(150);
  282. }
  283. break;
  284. }
  285. /* Set FIFO Watermarks (values taken from EMGD) */
  286. REG_WRITE(DSPARB, 0x3f80);
  287. REG_WRITE(DSPFW1, 0x3f8f0404);
  288. REG_WRITE(DSPFW2, 0x04040f04);
  289. REG_WRITE(DSPFW3, 0x0);
  290. REG_WRITE(DSPFW4, 0x04040404);
  291. REG_WRITE(DSPFW5, 0x04040404);
  292. REG_WRITE(DSPFW6, 0x78);
  293. REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040);
  294. gma_power_end(dev);
  295. }
  296. /**
  297. * Return the pipe currently connected to the panel fitter,
  298. * or -1 if the panel fitter is not present or not in use
  299. */
  300. static int oaktrail_panel_fitter_pipe(struct drm_device *dev)
  301. {
  302. u32 pfit_control;
  303. pfit_control = REG_READ(PFIT_CONTROL);
  304. /* See if the panel fitter is in use */
  305. if ((pfit_control & PFIT_ENABLE) == 0)
  306. return -1;
  307. return (pfit_control >> 29) & 3;
  308. }
  309. static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
  310. struct drm_display_mode *mode,
  311. struct drm_display_mode *adjusted_mode,
  312. int x, int y,
  313. struct drm_framebuffer *old_fb)
  314. {
  315. struct drm_device *dev = crtc->dev;
  316. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  317. struct drm_psb_private *dev_priv = dev->dev_private;
  318. int pipe = gma_crtc->pipe;
  319. const struct psb_offset *map = &dev_priv->regmap[pipe];
  320. int refclk = 0;
  321. struct gma_clock_t clock;
  322. const struct gma_limit_t *limit;
  323. u32 dpll = 0, fp = 0, dspcntr, pipeconf;
  324. bool ok, is_sdvo = false;
  325. bool is_lvds = false;
  326. bool is_mipi = false;
  327. struct drm_mode_config *mode_config = &dev->mode_config;
  328. struct gma_encoder *gma_encoder = NULL;
  329. uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
  330. struct drm_connector *connector;
  331. int i;
  332. int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
  333. if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  334. return oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
  335. if (!gma_power_begin(dev, true))
  336. return 0;
  337. memcpy(&gma_crtc->saved_mode,
  338. mode,
  339. sizeof(struct drm_display_mode));
  340. memcpy(&gma_crtc->saved_adjusted_mode,
  341. adjusted_mode,
  342. sizeof(struct drm_display_mode));
  343. list_for_each_entry(connector, &mode_config->connector_list, head) {
  344. if (!connector->encoder || connector->encoder->crtc != crtc)
  345. continue;
  346. gma_encoder = gma_attached_encoder(connector);
  347. switch (gma_encoder->type) {
  348. case INTEL_OUTPUT_LVDS:
  349. is_lvds = true;
  350. break;
  351. case INTEL_OUTPUT_SDVO:
  352. is_sdvo = true;
  353. break;
  354. case INTEL_OUTPUT_MIPI:
  355. is_mipi = true;
  356. break;
  357. }
  358. }
  359. /* Disable the VGA plane that we never use */
  360. for (i = 0; i <= need_aux; i++)
  361. REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i);
  362. /* Disable the panel fitter if it was on our pipe */
  363. if (oaktrail_panel_fitter_pipe(dev) == pipe)
  364. REG_WRITE(PFIT_CONTROL, 0);
  365. for (i = 0; i <= need_aux; i++) {
  366. REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) |
  367. (mode->crtc_vdisplay - 1), i);
  368. }
  369. if (gma_encoder)
  370. drm_object_property_get_value(&connector->base,
  371. dev->mode_config.scaling_mode_property, &scalingType);
  372. if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
  373. /* Moorestown doesn't have register support for centering so
  374. * we need to mess with the h/vblank and h/vsync start and
  375. * ends to get centering */
  376. int offsetX = 0, offsetY = 0;
  377. offsetX = (adjusted_mode->crtc_hdisplay -
  378. mode->crtc_hdisplay) / 2;
  379. offsetY = (adjusted_mode->crtc_vdisplay -
  380. mode->crtc_vdisplay) / 2;
  381. for (i = 0; i <= need_aux; i++) {
  382. REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) |
  383. ((adjusted_mode->crtc_htotal - 1) << 16), i);
  384. REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) |
  385. ((adjusted_mode->crtc_vtotal - 1) << 16), i);
  386. REG_WRITE_WITH_AUX(map->hblank,
  387. (adjusted_mode->crtc_hblank_start - offsetX - 1) |
  388. ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i);
  389. REG_WRITE_WITH_AUX(map->hsync,
  390. (adjusted_mode->crtc_hsync_start - offsetX - 1) |
  391. ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i);
  392. REG_WRITE_WITH_AUX(map->vblank,
  393. (adjusted_mode->crtc_vblank_start - offsetY - 1) |
  394. ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i);
  395. REG_WRITE_WITH_AUX(map->vsync,
  396. (adjusted_mode->crtc_vsync_start - offsetY - 1) |
  397. ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i);
  398. }
  399. } else {
  400. for (i = 0; i <= need_aux; i++) {
  401. REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
  402. ((adjusted_mode->crtc_htotal - 1) << 16), i);
  403. REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
  404. ((adjusted_mode->crtc_vtotal - 1) << 16), i);
  405. REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
  406. ((adjusted_mode->crtc_hblank_end - 1) << 16), i);
  407. REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
  408. ((adjusted_mode->crtc_hsync_end - 1) << 16), i);
  409. REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
  410. ((adjusted_mode->crtc_vblank_end - 1) << 16), i);
  411. REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
  412. ((adjusted_mode->crtc_vsync_end - 1) << 16), i);
  413. }
  414. }
  415. /* Flush the plane changes */
  416. {
  417. const struct drm_crtc_helper_funcs *crtc_funcs =
  418. crtc->helper_private;
  419. crtc_funcs->mode_set_base(crtc, x, y, old_fb);
  420. }
  421. /* setup pipeconf */
  422. pipeconf = REG_READ(map->conf);
  423. /* Set up the display plane register */
  424. dspcntr = REG_READ(map->cntr);
  425. dspcntr |= DISPPLANE_GAMMA_ENABLE;
  426. if (pipe == 0)
  427. dspcntr |= DISPPLANE_SEL_PIPE_A;
  428. else
  429. dspcntr |= DISPPLANE_SEL_PIPE_B;
  430. if (is_mipi)
  431. goto oaktrail_crtc_mode_set_exit;
  432. dpll = 0; /*BIT16 = 0 for 100MHz reference */
  433. refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000;
  434. limit = mrst_limit(crtc, refclk);
  435. ok = limit->find_pll(limit, crtc, adjusted_mode->clock,
  436. refclk, &clock);
  437. if (is_sdvo) {
  438. /* Convert calculated values to register values */
  439. clock.p1 = (1L << (clock.p1 - 1));
  440. clock.m -= 2;
  441. clock.n = (1L << (clock.n - 1));
  442. }
  443. if (!ok)
  444. DRM_ERROR("Failed to find proper PLL settings");
  445. mrst_print_pll(&clock);
  446. if (is_sdvo)
  447. fp = clock.n << 16 | clock.m;
  448. else
  449. fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;
  450. dpll |= DPLL_VGA_MODE_DIS;
  451. dpll |= DPLL_VCO_ENABLE;
  452. if (is_lvds)
  453. dpll |= DPLLA_MODE_LVDS;
  454. else
  455. dpll |= DPLLB_MODE_DAC_SERIAL;
  456. if (is_sdvo) {
  457. int sdvo_pixel_multiply =
  458. adjusted_mode->clock / mode->clock;
  459. dpll |= DPLL_DVO_HIGH_SPEED;
  460. dpll |=
  461. (sdvo_pixel_multiply -
  462. 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  463. }
  464. /* compute bitmask from p1 value */
  465. if (is_sdvo)
  466. dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;
  467. else
  468. dpll |= (1 << (clock.p1 - 2)) << 17;
  469. dpll |= DPLL_VCO_ENABLE;
  470. if (dpll & DPLL_VCO_ENABLE) {
  471. for (i = 0; i <= need_aux; i++) {
  472. REG_WRITE_WITH_AUX(map->fp0, fp, i);
  473. REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);
  474. REG_READ_WITH_AUX(map->dpll, i);
  475. /* Check the DPLLA lock bit PIPEACONF[29] */
  476. udelay(150);
  477. }
  478. }
  479. for (i = 0; i <= need_aux; i++) {
  480. REG_WRITE_WITH_AUX(map->fp0, fp, i);
  481. REG_WRITE_WITH_AUX(map->dpll, dpll, i);
  482. REG_READ_WITH_AUX(map->dpll, i);
  483. /* Wait for the clocks to stabilize. */
  484. udelay(150);
  485. /* write it again -- the BIOS does, after all */
  486. REG_WRITE_WITH_AUX(map->dpll, dpll, i);
  487. REG_READ_WITH_AUX(map->dpll, i);
  488. /* Wait for the clocks to stabilize. */
  489. udelay(150);
  490. REG_WRITE_WITH_AUX(map->conf, pipeconf, i);
  491. REG_READ_WITH_AUX(map->conf, i);
  492. gma_wait_for_vblank(dev);
  493. REG_WRITE_WITH_AUX(map->cntr, dspcntr, i);
  494. gma_wait_for_vblank(dev);
  495. }
  496. oaktrail_crtc_mode_set_exit:
  497. gma_power_end(dev);
  498. return 0;
  499. }
  500. static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
  501. int x, int y, struct drm_framebuffer *old_fb)
  502. {
  503. struct drm_device *dev = crtc->dev;
  504. struct drm_psb_private *dev_priv = dev->dev_private;
  505. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  506. struct drm_framebuffer *fb = crtc->primary->fb;
  507. int pipe = gma_crtc->pipe;
  508. const struct psb_offset *map = &dev_priv->regmap[pipe];
  509. unsigned long start, offset;
  510. u32 dspcntr;
  511. int ret = 0;
  512. /* no fb bound */
  513. if (!fb) {
  514. dev_dbg(dev->dev, "No FB bound\n");
  515. return 0;
  516. }
  517. if (!gma_power_begin(dev, true))
  518. return 0;
  519. start = to_gtt_range(fb->obj[0])->offset;
  520. offset = y * fb->pitches[0] + x * fb->format->cpp[0];
  521. REG_WRITE(map->stride, fb->pitches[0]);
  522. dspcntr = REG_READ(map->cntr);
  523. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  524. switch (fb->format->cpp[0] * 8) {
  525. case 8:
  526. dspcntr |= DISPPLANE_8BPP;
  527. break;
  528. case 16:
  529. if (fb->format->depth == 15)
  530. dspcntr |= DISPPLANE_15_16BPP;
  531. else
  532. dspcntr |= DISPPLANE_16BPP;
  533. break;
  534. case 24:
  535. case 32:
  536. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  537. break;
  538. default:
  539. dev_err(dev->dev, "Unknown color depth\n");
  540. ret = -EINVAL;
  541. goto pipe_set_base_exit;
  542. }
  543. REG_WRITE(map->cntr, dspcntr);
  544. REG_WRITE(map->base, offset);
  545. REG_READ(map->base);
  546. REG_WRITE(map->surf, start);
  547. REG_READ(map->surf);
  548. pipe_set_base_exit:
  549. gma_power_end(dev);
  550. return ret;
  551. }
  552. const struct drm_crtc_helper_funcs oaktrail_helper_funcs = {
  553. .dpms = oaktrail_crtc_dpms,
  554. .mode_set = oaktrail_crtc_mode_set,
  555. .mode_set_base = oaktrail_pipe_set_base,
  556. .prepare = gma_crtc_prepare,
  557. .commit = gma_crtc_commit,
  558. };
  559. /* Not used yet */
  560. const struct gma_clock_funcs mrst_clock_funcs = {
  561. .clock = mrst_lvds_clock,
  562. .limit = mrst_limit,
  563. .pll_is_valid = gma_pll_is_valid,
  564. };