mid_bios.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /**************************************************************************
  3. * Copyright (c) 2011, Intel Corporation.
  4. * All Rights Reserved.
  5. *
  6. **************************************************************************/
  7. /* TODO
  8. * - Split functions by vbt type
  9. * - Make them all take drm_device
  10. * - Check ioremap failures
  11. */
  12. #include <drm/drm.h>
  13. #include "mid_bios.h"
  14. #include "psb_drv.h"
  15. static void mid_get_fuse_settings(struct drm_device *dev)
  16. {
  17. struct drm_psb_private *dev_priv = dev->dev_private;
  18. struct pci_dev *pci_root =
  19. pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
  20. 0, 0);
  21. uint32_t fuse_value = 0;
  22. uint32_t fuse_value_tmp = 0;
  23. #define FB_REG06 0xD0810600
  24. #define FB_MIPI_DISABLE (1 << 11)
  25. #define FB_REG09 0xD0810900
  26. #define FB_SKU_MASK 0x7000
  27. #define FB_SKU_SHIFT 12
  28. #define FB_SKU_100 0
  29. #define FB_SKU_100L 1
  30. #define FB_SKU_83 2
  31. if (pci_root == NULL) {
  32. WARN_ON(1);
  33. return;
  34. }
  35. pci_write_config_dword(pci_root, 0xD0, FB_REG06);
  36. pci_read_config_dword(pci_root, 0xD4, &fuse_value);
  37. /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
  38. if (IS_MRST(dev))
  39. dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
  40. DRM_INFO("internal display is %s\n",
  41. dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
  42. /* Prevent runtime suspend at start*/
  43. if (dev_priv->iLVDS_enable) {
  44. dev_priv->is_lvds_on = true;
  45. dev_priv->is_mipi_on = false;
  46. } else {
  47. dev_priv->is_mipi_on = true;
  48. dev_priv->is_lvds_on = false;
  49. }
  50. dev_priv->video_device_fuse = fuse_value;
  51. pci_write_config_dword(pci_root, 0xD0, FB_REG09);
  52. pci_read_config_dword(pci_root, 0xD4, &fuse_value);
  53. dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
  54. fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
  55. dev_priv->fuse_reg_value = fuse_value;
  56. switch (fuse_value_tmp) {
  57. case FB_SKU_100:
  58. dev_priv->core_freq = 200;
  59. break;
  60. case FB_SKU_100L:
  61. dev_priv->core_freq = 100;
  62. break;
  63. case FB_SKU_83:
  64. dev_priv->core_freq = 166;
  65. break;
  66. default:
  67. dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
  68. fuse_value_tmp);
  69. dev_priv->core_freq = 0;
  70. }
  71. dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
  72. pci_dev_put(pci_root);
  73. }
  74. /*
  75. * Get the revison ID, B0:D2:F0;0x08
  76. */
  77. static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
  78. {
  79. uint32_t platform_rev_id = 0;
  80. int domain = pci_domain_nr(dev_priv->dev->pdev->bus);
  81. struct pci_dev *pci_gfx_root =
  82. pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
  83. if (pci_gfx_root == NULL) {
  84. WARN_ON(1);
  85. return;
  86. }
  87. pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
  88. dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
  89. pci_dev_put(pci_gfx_root);
  90. dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
  91. dev_priv->platform_rev_id);
  92. }
  93. struct mid_vbt_header {
  94. u32 signature;
  95. u8 revision;
  96. } __packed;
  97. /* The same for r0 and r1 */
  98. struct vbt_r0 {
  99. struct mid_vbt_header vbt_header;
  100. u8 size;
  101. u8 checksum;
  102. } __packed;
  103. struct vbt_r10 {
  104. struct mid_vbt_header vbt_header;
  105. u8 checksum;
  106. u16 size;
  107. u8 panel_count;
  108. u8 primary_panel_idx;
  109. u8 secondary_panel_idx;
  110. u8 __reserved[5];
  111. } __packed;
  112. static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt)
  113. {
  114. void __iomem *vbt_virtual;
  115. vbt_virtual = ioremap(addr, sizeof(*vbt));
  116. if (vbt_virtual == NULL)
  117. return -1;
  118. memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
  119. iounmap(vbt_virtual);
  120. return 0;
  121. }
  122. static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt)
  123. {
  124. void __iomem *vbt_virtual;
  125. vbt_virtual = ioremap(addr, sizeof(*vbt));
  126. if (!vbt_virtual)
  127. return -1;
  128. memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
  129. iounmap(vbt_virtual);
  130. return 0;
  131. }
  132. static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr)
  133. {
  134. struct vbt_r0 vbt;
  135. void __iomem *gct_virtual;
  136. struct gct_r0 gct;
  137. u8 bpi;
  138. if (read_vbt_r0(addr, &vbt))
  139. return -1;
  140. gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
  141. if (!gct_virtual)
  142. return -1;
  143. memcpy_fromio(&gct, gct_virtual, sizeof(gct));
  144. iounmap(gct_virtual);
  145. bpi = gct.PD.BootPanelIndex;
  146. dev_priv->gct_data.bpi = bpi;
  147. dev_priv->gct_data.pt = gct.PD.PanelType;
  148. dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
  149. dev_priv->gct_data.Panel_Port_Control =
  150. gct.panel[bpi].Panel_Port_Control;
  151. dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
  152. gct.panel[bpi].Panel_MIPI_Display_Descriptor;
  153. return 0;
  154. }
  155. static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr)
  156. {
  157. struct vbt_r0 vbt;
  158. void __iomem *gct_virtual;
  159. struct gct_r1 gct;
  160. u8 bpi;
  161. if (read_vbt_r0(addr, &vbt))
  162. return -1;
  163. gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
  164. if (!gct_virtual)
  165. return -1;
  166. memcpy_fromio(&gct, gct_virtual, sizeof(gct));
  167. iounmap(gct_virtual);
  168. bpi = gct.PD.BootPanelIndex;
  169. dev_priv->gct_data.bpi = bpi;
  170. dev_priv->gct_data.pt = gct.PD.PanelType;
  171. dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
  172. dev_priv->gct_data.Panel_Port_Control =
  173. gct.panel[bpi].Panel_Port_Control;
  174. dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
  175. gct.panel[bpi].Panel_MIPI_Display_Descriptor;
  176. return 0;
  177. }
  178. static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)
  179. {
  180. struct vbt_r10 vbt;
  181. void __iomem *gct_virtual;
  182. struct gct_r10 *gct;
  183. struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
  184. struct gct_r10_timing_info *ti;
  185. int ret = -1;
  186. if (read_vbt_r10(addr, &vbt))
  187. return -1;
  188. gct = kmalloc_array(vbt.panel_count, sizeof(*gct), GFP_KERNEL);
  189. if (!gct)
  190. return -ENOMEM;
  191. gct_virtual = ioremap(addr + sizeof(vbt),
  192. sizeof(*gct) * vbt.panel_count);
  193. if (!gct_virtual)
  194. goto out;
  195. memcpy_fromio(gct, gct_virtual, sizeof(*gct));
  196. iounmap(gct_virtual);
  197. dev_priv->gct_data.bpi = vbt.primary_panel_idx;
  198. dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
  199. gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor;
  200. ti = &gct[vbt.primary_panel_idx].DTD;
  201. dp_ti->pixel_clock = ti->pixel_clock;
  202. dp_ti->hactive_hi = ti->hactive_hi;
  203. dp_ti->hactive_lo = ti->hactive_lo;
  204. dp_ti->hblank_hi = ti->hblank_hi;
  205. dp_ti->hblank_lo = ti->hblank_lo;
  206. dp_ti->hsync_offset_hi = ti->hsync_offset_hi;
  207. dp_ti->hsync_offset_lo = ti->hsync_offset_lo;
  208. dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi;
  209. dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo;
  210. dp_ti->vactive_hi = ti->vactive_hi;
  211. dp_ti->vactive_lo = ti->vactive_lo;
  212. dp_ti->vblank_hi = ti->vblank_hi;
  213. dp_ti->vblank_lo = ti->vblank_lo;
  214. dp_ti->vsync_offset_hi = ti->vsync_offset_hi;
  215. dp_ti->vsync_offset_lo = ti->vsync_offset_lo;
  216. dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi;
  217. dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo;
  218. ret = 0;
  219. out:
  220. kfree(gct);
  221. return ret;
  222. }
  223. static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
  224. {
  225. struct drm_device *dev = dev_priv->dev;
  226. u32 addr;
  227. u8 __iomem *vbt_virtual;
  228. struct mid_vbt_header vbt_header;
  229. struct pci_dev *pci_gfx_root =
  230. pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
  231. 0, PCI_DEVFN(2, 0));
  232. int ret = -1;
  233. /* Get the address of the platform config vbt */
  234. pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
  235. pci_dev_put(pci_gfx_root);
  236. dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
  237. if (!addr)
  238. goto out;
  239. /* get the virtual address of the vbt */
  240. vbt_virtual = ioremap(addr, sizeof(vbt_header));
  241. if (!vbt_virtual)
  242. goto out;
  243. memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header));
  244. iounmap(vbt_virtual);
  245. if (memcmp(&vbt_header.signature, "$GCT", 4))
  246. goto out;
  247. dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision);
  248. switch (vbt_header.revision) {
  249. case 0x00:
  250. ret = mid_get_vbt_data_r0(dev_priv, addr);
  251. break;
  252. case 0x01:
  253. ret = mid_get_vbt_data_r1(dev_priv, addr);
  254. break;
  255. case 0x10:
  256. ret = mid_get_vbt_data_r10(dev_priv, addr);
  257. break;
  258. default:
  259. dev_err(dev->dev, "Unknown revision of GCT!\n");
  260. }
  261. out:
  262. if (ret)
  263. dev_err(dev->dev, "Unable to read GCT!");
  264. else
  265. dev_priv->has_gct = true;
  266. }
  267. int mid_chip_setup(struct drm_device *dev)
  268. {
  269. struct drm_psb_private *dev_priv = dev->dev_private;
  270. mid_get_fuse_settings(dev);
  271. mid_get_vbt_data(dev_priv);
  272. mid_get_pci_revID(dev_priv);
  273. return 0;
  274. }