mdfld_dsi_output.h 12 KB

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  1. /*
  2. * Copyright © 2010 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * jim liu <jim.liu@intel.com>
  25. * Jackie Li<yaodong.li@intel.com>
  26. */
  27. #ifndef __MDFLD_DSI_OUTPUT_H__
  28. #define __MDFLD_DSI_OUTPUT_H__
  29. #include <linux/backlight.h>
  30. #include <asm/intel-mid.h>
  31. #include <drm/drm.h>
  32. #include <drm/drm_crtc.h>
  33. #include <drm/drm_edid.h>
  34. #include "mdfld_output.h"
  35. #include "psb_drv.h"
  36. #include "psb_intel_drv.h"
  37. #include "psb_intel_reg.h"
  38. #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
  39. #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  40. #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  41. #define FLD_MOD(orig, val, start, end) \
  42. (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  43. #define REG_FLD_MOD(reg, val, start, end) \
  44. REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))
  45. static inline int REGISTER_FLD_WAIT(struct drm_device *dev, u32 reg,
  46. u32 val, int start, int end)
  47. {
  48. int t = 100000;
  49. while (FLD_GET(REG_READ(reg), start, end) != val) {
  50. if (--t == 0)
  51. return 1;
  52. }
  53. return 0;
  54. }
  55. #define REG_FLD_WAIT(reg, val, start, end) \
  56. REGISTER_FLD_WAIT(dev, reg, val, start, end)
  57. #define REG_BIT_WAIT(reg, val, bitnum) \
  58. REGISTER_FLD_WAIT(dev, reg, val, bitnum, bitnum)
  59. #define MDFLD_DSI_BRIGHTNESS_MAX_LEVEL 100
  60. #ifdef DEBUG
  61. #define CHECK_PIPE(pipe) ({ \
  62. const typeof(pipe) __pipe = (pipe); \
  63. BUG_ON(__pipe != 0 && __pipe != 2); \
  64. __pipe; })
  65. #else
  66. #define CHECK_PIPE(pipe) (pipe)
  67. #endif
  68. /*
  69. * Actual MIPIA->MIPIC reg offset is 0x800, value 0x400 is valid for 0 and 2
  70. */
  71. #define REG_OFFSET(pipe) (CHECK_PIPE(pipe) * 0x400)
  72. /* mdfld DSI controller registers */
  73. #define MIPI_DEVICE_READY_REG(pipe) (0xb000 + REG_OFFSET(pipe))
  74. #define MIPI_INTR_STAT_REG(pipe) (0xb004 + REG_OFFSET(pipe))
  75. #define MIPI_INTR_EN_REG(pipe) (0xb008 + REG_OFFSET(pipe))
  76. #define MIPI_DSI_FUNC_PRG_REG(pipe) (0xb00c + REG_OFFSET(pipe))
  77. #define MIPI_HS_TX_TIMEOUT_REG(pipe) (0xb010 + REG_OFFSET(pipe))
  78. #define MIPI_LP_RX_TIMEOUT_REG(pipe) (0xb014 + REG_OFFSET(pipe))
  79. #define MIPI_TURN_AROUND_TIMEOUT_REG(pipe) (0xb018 + REG_OFFSET(pipe))
  80. #define MIPI_DEVICE_RESET_TIMER_REG(pipe) (0xb01c + REG_OFFSET(pipe))
  81. #define MIPI_DPI_RESOLUTION_REG(pipe) (0xb020 + REG_OFFSET(pipe))
  82. #define MIPI_DBI_FIFO_THROTTLE_REG(pipe) (0xb024 + REG_OFFSET(pipe))
  83. #define MIPI_HSYNC_COUNT_REG(pipe) (0xb028 + REG_OFFSET(pipe))
  84. #define MIPI_HBP_COUNT_REG(pipe) (0xb02c + REG_OFFSET(pipe))
  85. #define MIPI_HFP_COUNT_REG(pipe) (0xb030 + REG_OFFSET(pipe))
  86. #define MIPI_HACTIVE_COUNT_REG(pipe) (0xb034 + REG_OFFSET(pipe))
  87. #define MIPI_VSYNC_COUNT_REG(pipe) (0xb038 + REG_OFFSET(pipe))
  88. #define MIPI_VBP_COUNT_REG(pipe) (0xb03c + REG_OFFSET(pipe))
  89. #define MIPI_VFP_COUNT_REG(pipe) (0xb040 + REG_OFFSET(pipe))
  90. #define MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe) (0xb044 + REG_OFFSET(pipe))
  91. #define MIPI_DPI_CONTROL_REG(pipe) (0xb048 + REG_OFFSET(pipe))
  92. #define MIPI_DPI_DATA_REG(pipe) (0xb04c + REG_OFFSET(pipe))
  93. #define MIPI_INIT_COUNT_REG(pipe) (0xb050 + REG_OFFSET(pipe))
  94. #define MIPI_MAX_RETURN_PACK_SIZE_REG(pipe) (0xb054 + REG_OFFSET(pipe))
  95. #define MIPI_VIDEO_MODE_FORMAT_REG(pipe) (0xb058 + REG_OFFSET(pipe))
  96. #define MIPI_EOT_DISABLE_REG(pipe) (0xb05c + REG_OFFSET(pipe))
  97. #define MIPI_LP_BYTECLK_REG(pipe) (0xb060 + REG_OFFSET(pipe))
  98. #define MIPI_LP_GEN_DATA_REG(pipe) (0xb064 + REG_OFFSET(pipe))
  99. #define MIPI_HS_GEN_DATA_REG(pipe) (0xb068 + REG_OFFSET(pipe))
  100. #define MIPI_LP_GEN_CTRL_REG(pipe) (0xb06c + REG_OFFSET(pipe))
  101. #define MIPI_HS_GEN_CTRL_REG(pipe) (0xb070 + REG_OFFSET(pipe))
  102. #define MIPI_GEN_FIFO_STAT_REG(pipe) (0xb074 + REG_OFFSET(pipe))
  103. #define MIPI_HS_LS_DBI_ENABLE_REG(pipe) (0xb078 + REG_OFFSET(pipe))
  104. #define MIPI_DPHY_PARAM_REG(pipe) (0xb080 + REG_OFFSET(pipe))
  105. #define MIPI_DBI_BW_CTRL_REG(pipe) (0xb084 + REG_OFFSET(pipe))
  106. #define MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe) (0xb088 + REG_OFFSET(pipe))
  107. #define MIPI_CTRL_REG(pipe) (0xb104 + REG_OFFSET(pipe))
  108. #define MIPI_DATA_ADD_REG(pipe) (0xb108 + REG_OFFSET(pipe))
  109. #define MIPI_DATA_LEN_REG(pipe) (0xb10c + REG_OFFSET(pipe))
  110. #define MIPI_CMD_ADD_REG(pipe) (0xb110 + REG_OFFSET(pipe))
  111. #define MIPI_CMD_LEN_REG(pipe) (0xb114 + REG_OFFSET(pipe))
  112. /* non-uniform reg offset */
  113. #define MIPI_PORT_CONTROL(pipe) (CHECK_PIPE(pipe) ? MIPI_C : MIPI)
  114. #define DSI_DEVICE_READY (0x1)
  115. #define DSI_POWER_STATE_ULPS_ENTER (0x2 << 1)
  116. #define DSI_POWER_STATE_ULPS_EXIT (0x1 << 1)
  117. #define DSI_POWER_STATE_ULPS_OFFSET (0x1)
  118. #define DSI_ONE_DATA_LANE (0x1)
  119. #define DSI_TWO_DATA_LANE (0x2)
  120. #define DSI_THREE_DATA_LANE (0X3)
  121. #define DSI_FOUR_DATA_LANE (0x4)
  122. #define DSI_DPI_VIRT_CHANNEL_OFFSET (0x3)
  123. #define DSI_DBI_VIRT_CHANNEL_OFFSET (0x5)
  124. #define DSI_DPI_COLOR_FORMAT_RGB565 (0x01 << 7)
  125. #define DSI_DPI_COLOR_FORMAT_RGB666 (0x02 << 7)
  126. #define DSI_DPI_COLOR_FORMAT_RGB666_UNPACK (0x03 << 7)
  127. #define DSI_DPI_COLOR_FORMAT_RGB888 (0x04 << 7)
  128. #define DSI_DBI_COLOR_FORMAT_OPTION2 (0x05 << 13)
  129. #define DSI_INTR_STATE_RXSOTERROR BIT(0)
  130. #define DSI_INTR_STATE_SPL_PKG_SENT BIT(30)
  131. #define DSI_INTR_STATE_TE BIT(31)
  132. #define DSI_HS_TX_TIMEOUT_MASK (0xffffff)
  133. #define DSI_LP_RX_TIMEOUT_MASK (0xffffff)
  134. #define DSI_TURN_AROUND_TIMEOUT_MASK (0x3f)
  135. #define DSI_RESET_TIMER_MASK (0xffff)
  136. #define DSI_DBI_FIFO_WM_HALF (0x0)
  137. #define DSI_DBI_FIFO_WM_QUARTER (0x1)
  138. #define DSI_DBI_FIFO_WM_LOW (0x2)
  139. #define DSI_DPI_TIMING_MASK (0xffff)
  140. #define DSI_INIT_TIMER_MASK (0xffff)
  141. #define DSI_DBI_RETURN_PACK_SIZE_MASK (0x3ff)
  142. #define DSI_LP_BYTECLK_MASK (0x0ffff)
  143. #define DSI_HS_CTRL_GEN_SHORT_W0 (0x03)
  144. #define DSI_HS_CTRL_GEN_SHORT_W1 (0x13)
  145. #define DSI_HS_CTRL_GEN_SHORT_W2 (0x23)
  146. #define DSI_HS_CTRL_GEN_R0 (0x04)
  147. #define DSI_HS_CTRL_GEN_R1 (0x14)
  148. #define DSI_HS_CTRL_GEN_R2 (0x24)
  149. #define DSI_HS_CTRL_GEN_LONG_W (0x29)
  150. #define DSI_HS_CTRL_MCS_SHORT_W0 (0x05)
  151. #define DSI_HS_CTRL_MCS_SHORT_W1 (0x15)
  152. #define DSI_HS_CTRL_MCS_R0 (0x06)
  153. #define DSI_HS_CTRL_MCS_LONG_W (0x39)
  154. #define DSI_HS_CTRL_VC_OFFSET (0x06)
  155. #define DSI_HS_CTRL_WC_OFFSET (0x08)
  156. #define DSI_FIFO_GEN_HS_DATA_FULL BIT(0)
  157. #define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY BIT(1)
  158. #define DSI_FIFO_GEN_HS_DATA_EMPTY BIT(2)
  159. #define DSI_FIFO_GEN_LP_DATA_FULL BIT(8)
  160. #define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY BIT(9)
  161. #define DSI_FIFO_GEN_LP_DATA_EMPTY BIT(10)
  162. #define DSI_FIFO_GEN_HS_CTRL_FULL BIT(16)
  163. #define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY BIT(17)
  164. #define DSI_FIFO_GEN_HS_CTRL_EMPTY BIT(18)
  165. #define DSI_FIFO_GEN_LP_CTRL_FULL BIT(24)
  166. #define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY BIT(25)
  167. #define DSI_FIFO_GEN_LP_CTRL_EMPTY BIT(26)
  168. #define DSI_FIFO_DBI_EMPTY BIT(27)
  169. #define DSI_FIFO_DPI_EMPTY BIT(28)
  170. #define DSI_DBI_HS_LP_SWITCH_MASK (0x1)
  171. #define DSI_HS_LP_SWITCH_COUNTER_OFFSET (0x0)
  172. #define DSI_LP_HS_SWITCH_COUNTER_OFFSET (0x16)
  173. #define DSI_DPI_CTRL_HS_SHUTDOWN (0x00000001)
  174. #define DSI_DPI_CTRL_HS_TURN_ON (0x00000002)
  175. /*dsi power modes*/
  176. #define DSI_POWER_MODE_DISPLAY_ON BIT(2)
  177. #define DSI_POWER_MODE_NORMAL_ON BIT(3)
  178. #define DSI_POWER_MODE_SLEEP_OUT BIT(4)
  179. #define DSI_POWER_MODE_PARTIAL_ON BIT(5)
  180. #define DSI_POWER_MODE_IDLE_ON BIT(6)
  181. enum {
  182. MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_PULSE = 1,
  183. MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_EVENTS = 2,
  184. MDFLD_DSI_VIDEO_BURST_MODE = 3,
  185. };
  186. #define DSI_DPI_COMPLETE_LAST_LINE BIT(2)
  187. #define DSI_DPI_DISABLE_BTA BIT(3)
  188. struct mdfld_dsi_connector {
  189. struct gma_connector base;
  190. int pipe;
  191. void *private;
  192. void *pkg_sender;
  193. /* Connection status */
  194. enum drm_connector_status status;
  195. };
  196. struct mdfld_dsi_encoder {
  197. struct gma_encoder base;
  198. void *private;
  199. };
  200. /*
  201. * DSI config, consists of one DSI connector, two DSI encoders.
  202. * DRM will pick up on DSI encoder basing on differents configs.
  203. */
  204. struct mdfld_dsi_config {
  205. struct drm_device *dev;
  206. struct drm_display_mode *fixed_mode;
  207. struct drm_display_mode *mode;
  208. struct mdfld_dsi_connector *connector;
  209. struct mdfld_dsi_encoder *encoder;
  210. int changed;
  211. int bpp;
  212. int lane_count;
  213. /*Virtual channel number for this encoder*/
  214. int channel_num;
  215. /*video mode configure*/
  216. int video_mode;
  217. int dvr_ic_inited;
  218. };
  219. static inline struct mdfld_dsi_connector *mdfld_dsi_connector(
  220. struct drm_connector *connector)
  221. {
  222. struct gma_connector *gma_connector;
  223. gma_connector = to_gma_connector(connector);
  224. return container_of(gma_connector, struct mdfld_dsi_connector, base);
  225. }
  226. static inline struct mdfld_dsi_encoder *mdfld_dsi_encoder(
  227. struct drm_encoder *encoder)
  228. {
  229. struct gma_encoder *gma_encoder;
  230. gma_encoder = to_gma_encoder(encoder);
  231. return container_of(gma_encoder, struct mdfld_dsi_encoder, base);
  232. }
  233. static inline struct mdfld_dsi_config *
  234. mdfld_dsi_get_config(struct mdfld_dsi_connector *connector)
  235. {
  236. if (!connector)
  237. return NULL;
  238. return (struct mdfld_dsi_config *)connector->private;
  239. }
  240. static inline void *mdfld_dsi_get_pkg_sender(struct mdfld_dsi_config *config)
  241. {
  242. struct mdfld_dsi_connector *dsi_connector;
  243. if (!config)
  244. return NULL;
  245. dsi_connector = config->connector;
  246. if (!dsi_connector)
  247. return NULL;
  248. return dsi_connector->pkg_sender;
  249. }
  250. static inline struct mdfld_dsi_config *
  251. mdfld_dsi_encoder_get_config(struct mdfld_dsi_encoder *encoder)
  252. {
  253. if (!encoder)
  254. return NULL;
  255. return (struct mdfld_dsi_config *)encoder->private;
  256. }
  257. static inline struct mdfld_dsi_connector *
  258. mdfld_dsi_encoder_get_connector(struct mdfld_dsi_encoder *encoder)
  259. {
  260. struct mdfld_dsi_config *config;
  261. if (!encoder)
  262. return NULL;
  263. config = mdfld_dsi_encoder_get_config(encoder);
  264. if (!config)
  265. return NULL;
  266. return config->connector;
  267. }
  268. static inline void *mdfld_dsi_encoder_get_pkg_sender(
  269. struct mdfld_dsi_encoder *encoder)
  270. {
  271. struct mdfld_dsi_config *dsi_config;
  272. dsi_config = mdfld_dsi_encoder_get_config(encoder);
  273. if (!dsi_config)
  274. return NULL;
  275. return mdfld_dsi_get_pkg_sender(dsi_config);
  276. }
  277. static inline int mdfld_dsi_encoder_get_pipe(struct mdfld_dsi_encoder *encoder)
  278. {
  279. struct mdfld_dsi_connector *connector;
  280. if (!encoder)
  281. return -1;
  282. connector = mdfld_dsi_encoder_get_connector(encoder);
  283. if (!connector)
  284. return -1;
  285. return connector->pipe;
  286. }
  287. /* Export functions */
  288. extern void mdfld_dsi_gen_fifo_ready(struct drm_device *dev,
  289. u32 gen_fifo_stat_reg, u32 fifo_stat);
  290. extern void mdfld_dsi_brightness_init(struct mdfld_dsi_config *dsi_config,
  291. int pipe);
  292. extern void mdfld_dsi_brightness_control(struct drm_device *dev, int pipe,
  293. int level);
  294. extern void mdfld_dsi_output_init(struct drm_device *dev,
  295. int pipe,
  296. const struct panel_funcs *p_vid_funcs);
  297. extern void mdfld_dsi_controller_init(struct mdfld_dsi_config *dsi_config,
  298. int pipe);
  299. extern int mdfld_dsi_get_power_mode(struct mdfld_dsi_config *dsi_config,
  300. u32 *mode, bool hs);
  301. extern int mdfld_dsi_panel_reset(struct drm_device *dev, int pipe);
  302. #endif /*__MDFLD_DSI_OUTPUT_H__*/