mdfld_dsi_dpi.c 31 KB

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  1. /*
  2. * Copyright © 2010 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * jim liu <jim.liu@intel.com>
  25. * Jackie Li<yaodong.li@intel.com>
  26. */
  27. #include <linux/delay.h>
  28. #include <drm/drm_simple_kms_helper.h>
  29. #include "mdfld_dsi_dpi.h"
  30. #include "mdfld_dsi_pkg_sender.h"
  31. #include "mdfld_output.h"
  32. #include "psb_drv.h"
  33. #include "tc35876x-dsi-lvds.h"
  34. static void mdfld_dsi_dpi_shut_down(struct mdfld_dsi_dpi_output *output,
  35. int pipe);
  36. static void mdfld_wait_for_HS_DATA_FIFO(struct drm_device *dev, u32 pipe)
  37. {
  38. u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe);
  39. int timeout = 0;
  40. udelay(500);
  41. /* This will time out after approximately 2+ seconds */
  42. while ((timeout < 20000) &&
  43. (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) {
  44. udelay(100);
  45. timeout++;
  46. }
  47. if (timeout == 20000)
  48. DRM_INFO("MIPI: HS Data FIFO was never cleared!\n");
  49. }
  50. static void mdfld_wait_for_HS_CTRL_FIFO(struct drm_device *dev, u32 pipe)
  51. {
  52. u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe);
  53. int timeout = 0;
  54. udelay(500);
  55. /* This will time out after approximately 2+ seconds */
  56. while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg)
  57. & DSI_FIFO_GEN_HS_CTRL_FULL)) {
  58. udelay(100);
  59. timeout++;
  60. }
  61. if (timeout == 20000)
  62. DRM_INFO("MIPI: HS CMD FIFO was never cleared!\n");
  63. }
  64. static void mdfld_wait_for_DPI_CTRL_FIFO(struct drm_device *dev, u32 pipe)
  65. {
  66. u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe);
  67. int timeout = 0;
  68. udelay(500);
  69. /* This will time out after approximately 2+ seconds */
  70. while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) &
  71. DPI_FIFO_EMPTY) != DPI_FIFO_EMPTY)) {
  72. udelay(100);
  73. timeout++;
  74. }
  75. if (timeout == 20000)
  76. DRM_ERROR("MIPI: DPI FIFO was never cleared\n");
  77. }
  78. static void mdfld_wait_for_SPL_PKG_SENT(struct drm_device *dev, u32 pipe)
  79. {
  80. u32 intr_stat_reg = MIPI_INTR_STAT_REG(pipe);
  81. int timeout = 0;
  82. udelay(500);
  83. /* This will time out after approximately 2+ seconds */
  84. while ((timeout < 20000) && (!(REG_READ(intr_stat_reg)
  85. & DSI_INTR_STATE_SPL_PKG_SENT))) {
  86. udelay(100);
  87. timeout++;
  88. }
  89. if (timeout == 20000)
  90. DRM_ERROR("MIPI: SPL_PKT_SENT_INTERRUPT was not sent successfully!\n");
  91. }
  92. /* For TC35876X */
  93. static void dsi_set_device_ready_state(struct drm_device *dev, int state,
  94. int pipe)
  95. {
  96. REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), !!state, 0, 0);
  97. }
  98. static void dsi_set_pipe_plane_enable_state(struct drm_device *dev,
  99. int state, int pipe)
  100. {
  101. struct drm_psb_private *dev_priv = dev->dev_private;
  102. u32 pipeconf_reg = PIPEACONF;
  103. u32 dspcntr_reg = DSPACNTR;
  104. u32 dspcntr = dev_priv->dspcntr[pipe];
  105. u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX;
  106. if (pipe) {
  107. pipeconf_reg = PIPECCONF;
  108. dspcntr_reg = DSPCCNTR;
  109. } else
  110. mipi &= (~0x03);
  111. if (state) {
  112. /*Set up pipe */
  113. REG_WRITE(pipeconf_reg, BIT(31));
  114. if (REG_BIT_WAIT(pipeconf_reg, 1, 30))
  115. dev_err(&dev->pdev->dev, "%s: Pipe enable timeout\n",
  116. __func__);
  117. /*Set up display plane */
  118. REG_WRITE(dspcntr_reg, dspcntr);
  119. } else {
  120. u32 dspbase_reg = pipe ? MDFLD_DSPCBASE : MRST_DSPABASE;
  121. /* Put DSI lanes to ULPS to disable pipe */
  122. REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1);
  123. REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */
  124. /* LP Hold */
  125. REG_FLD_MOD(MIPI_PORT_CONTROL(pipe), 0, 16, 16);
  126. REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */
  127. /* Disable display plane */
  128. REG_FLD_MOD(dspcntr_reg, 0, 31, 31);
  129. /* Flush the plane changes ??? posted write? */
  130. REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
  131. REG_READ(dspbase_reg);
  132. /* Disable PIPE */
  133. REG_FLD_MOD(pipeconf_reg, 0, 31, 31);
  134. if (REG_BIT_WAIT(pipeconf_reg, 0, 30))
  135. dev_err(&dev->pdev->dev, "%s: Pipe disable timeout\n",
  136. __func__);
  137. if (REG_BIT_WAIT(MIPI_GEN_FIFO_STAT_REG(pipe), 1, 28))
  138. dev_err(&dev->pdev->dev, "%s: FIFO not empty\n",
  139. __func__);
  140. }
  141. }
  142. static void mdfld_dsi_configure_down(struct mdfld_dsi_encoder *dsi_encoder,
  143. int pipe)
  144. {
  145. struct mdfld_dsi_dpi_output *dpi_output =
  146. MDFLD_DSI_DPI_OUTPUT(dsi_encoder);
  147. struct mdfld_dsi_config *dsi_config =
  148. mdfld_dsi_encoder_get_config(dsi_encoder);
  149. struct drm_device *dev = dsi_config->dev;
  150. struct drm_psb_private *dev_priv = dev->dev_private;
  151. if (!dev_priv->dpi_panel_on[pipe]) {
  152. dev_err(dev->dev, "DPI panel is already off\n");
  153. return;
  154. }
  155. tc35876x_toshiba_bridge_panel_off(dev);
  156. tc35876x_set_bridge_reset_state(dev, 1);
  157. dsi_set_pipe_plane_enable_state(dev, 0, pipe);
  158. mdfld_dsi_dpi_shut_down(dpi_output, pipe);
  159. dsi_set_device_ready_state(dev, 0, pipe);
  160. }
  161. static void mdfld_dsi_configure_up(struct mdfld_dsi_encoder *dsi_encoder,
  162. int pipe)
  163. {
  164. struct mdfld_dsi_dpi_output *dpi_output =
  165. MDFLD_DSI_DPI_OUTPUT(dsi_encoder);
  166. struct mdfld_dsi_config *dsi_config =
  167. mdfld_dsi_encoder_get_config(dsi_encoder);
  168. struct drm_device *dev = dsi_config->dev;
  169. struct drm_psb_private *dev_priv = dev->dev_private;
  170. if (dev_priv->dpi_panel_on[pipe]) {
  171. dev_err(dev->dev, "DPI panel is already on\n");
  172. return;
  173. }
  174. /* For resume path sequence */
  175. mdfld_dsi_dpi_shut_down(dpi_output, pipe);
  176. dsi_set_device_ready_state(dev, 0, pipe);
  177. dsi_set_device_ready_state(dev, 1, pipe);
  178. tc35876x_set_bridge_reset_state(dev, 0);
  179. tc35876x_configure_lvds_bridge(dev);
  180. mdfld_dsi_dpi_turn_on(dpi_output, pipe); /* Send turn on command */
  181. dsi_set_pipe_plane_enable_state(dev, 1, pipe);
  182. }
  183. /* End for TC35876X */
  184. /* ************************************************************************* *\
  185. * FUNCTION: mdfld_dsi_tpo_ic_init
  186. *
  187. * DESCRIPTION: This function is called only by mrst_dsi_mode_set and
  188. * restore_display_registers. since this function does not
  189. * acquire the mutex, it is important that the calling function
  190. * does!
  191. \* ************************************************************************* */
  192. static void mdfld_dsi_tpo_ic_init(struct mdfld_dsi_config *dsi_config, u32 pipe)
  193. {
  194. struct drm_device *dev = dsi_config->dev;
  195. u32 dcsChannelNumber = dsi_config->channel_num;
  196. u32 gen_data_reg = MIPI_HS_GEN_DATA_REG(pipe);
  197. u32 gen_ctrl_reg = MIPI_HS_GEN_CTRL_REG(pipe);
  198. u32 gen_ctrl_val = GEN_LONG_WRITE;
  199. DRM_INFO("Enter mrst init TPO MIPI display.\n");
  200. gen_ctrl_val |= dcsChannelNumber << DCS_CHANNEL_NUMBER_POS;
  201. /* Flip page order */
  202. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  203. REG_WRITE(gen_data_reg, 0x00008036);
  204. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  205. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS));
  206. /* 0xF0 */
  207. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  208. REG_WRITE(gen_data_reg, 0x005a5af0);
  209. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  210. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS));
  211. /* Write protection key */
  212. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  213. REG_WRITE(gen_data_reg, 0x005a5af1);
  214. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  215. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS));
  216. /* 0xFC */
  217. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  218. REG_WRITE(gen_data_reg, 0x005a5afc);
  219. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  220. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS));
  221. /* 0xB7 */
  222. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  223. REG_WRITE(gen_data_reg, 0x770000b7);
  224. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  225. REG_WRITE(gen_data_reg, 0x00000044);
  226. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  227. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x05 << WORD_COUNTS_POS));
  228. /* 0xB6 */
  229. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  230. REG_WRITE(gen_data_reg, 0x000a0ab6);
  231. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  232. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS));
  233. /* 0xF2 */
  234. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  235. REG_WRITE(gen_data_reg, 0x081010f2);
  236. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  237. REG_WRITE(gen_data_reg, 0x4a070708);
  238. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  239. REG_WRITE(gen_data_reg, 0x000000c5);
  240. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  241. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS));
  242. /* 0xF8 */
  243. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  244. REG_WRITE(gen_data_reg, 0x024003f8);
  245. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  246. REG_WRITE(gen_data_reg, 0x01030a04);
  247. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  248. REG_WRITE(gen_data_reg, 0x0e020220);
  249. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  250. REG_WRITE(gen_data_reg, 0x00000004);
  251. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  252. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x0d << WORD_COUNTS_POS));
  253. /* 0xE2 */
  254. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  255. REG_WRITE(gen_data_reg, 0x398fc3e2);
  256. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  257. REG_WRITE(gen_data_reg, 0x0000916f);
  258. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  259. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x06 << WORD_COUNTS_POS));
  260. /* 0xB0 */
  261. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  262. REG_WRITE(gen_data_reg, 0x000000b0);
  263. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  264. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS));
  265. /* 0xF4 */
  266. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  267. REG_WRITE(gen_data_reg, 0x240242f4);
  268. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  269. REG_WRITE(gen_data_reg, 0x78ee2002);
  270. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  271. REG_WRITE(gen_data_reg, 0x2a071050);
  272. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  273. REG_WRITE(gen_data_reg, 0x507fee10);
  274. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  275. REG_WRITE(gen_data_reg, 0x10300710);
  276. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  277. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x14 << WORD_COUNTS_POS));
  278. /* 0xBA */
  279. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  280. REG_WRITE(gen_data_reg, 0x19fe07ba);
  281. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  282. REG_WRITE(gen_data_reg, 0x101c0a31);
  283. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  284. REG_WRITE(gen_data_reg, 0x00000010);
  285. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  286. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS));
  287. /* 0xBB */
  288. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  289. REG_WRITE(gen_data_reg, 0x28ff07bb);
  290. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  291. REG_WRITE(gen_data_reg, 0x24280a31);
  292. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  293. REG_WRITE(gen_data_reg, 0x00000034);
  294. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  295. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS));
  296. /* 0xFB */
  297. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  298. REG_WRITE(gen_data_reg, 0x535d05fb);
  299. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  300. REG_WRITE(gen_data_reg, 0x1b1a2130);
  301. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  302. REG_WRITE(gen_data_reg, 0x221e180e);
  303. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  304. REG_WRITE(gen_data_reg, 0x131d2120);
  305. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  306. REG_WRITE(gen_data_reg, 0x535d0508);
  307. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  308. REG_WRITE(gen_data_reg, 0x1c1a2131);
  309. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  310. REG_WRITE(gen_data_reg, 0x231f160d);
  311. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  312. REG_WRITE(gen_data_reg, 0x111b2220);
  313. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  314. REG_WRITE(gen_data_reg, 0x535c2008);
  315. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  316. REG_WRITE(gen_data_reg, 0x1f1d2433);
  317. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  318. REG_WRITE(gen_data_reg, 0x2c251a10);
  319. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  320. REG_WRITE(gen_data_reg, 0x2c34372d);
  321. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  322. REG_WRITE(gen_data_reg, 0x00000023);
  323. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  324. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS));
  325. /* 0xFA */
  326. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  327. REG_WRITE(gen_data_reg, 0x525c0bfa);
  328. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  329. REG_WRITE(gen_data_reg, 0x1c1c232f);
  330. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  331. REG_WRITE(gen_data_reg, 0x2623190e);
  332. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  333. REG_WRITE(gen_data_reg, 0x18212625);
  334. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  335. REG_WRITE(gen_data_reg, 0x545d0d0e);
  336. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  337. REG_WRITE(gen_data_reg, 0x1e1d2333);
  338. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  339. REG_WRITE(gen_data_reg, 0x26231a10);
  340. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  341. REG_WRITE(gen_data_reg, 0x1a222725);
  342. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  343. REG_WRITE(gen_data_reg, 0x545d280f);
  344. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  345. REG_WRITE(gen_data_reg, 0x21202635);
  346. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  347. REG_WRITE(gen_data_reg, 0x31292013);
  348. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  349. REG_WRITE(gen_data_reg, 0x31393d33);
  350. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  351. REG_WRITE(gen_data_reg, 0x00000029);
  352. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  353. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS));
  354. /* Set DM */
  355. mdfld_wait_for_HS_DATA_FIFO(dev, pipe);
  356. REG_WRITE(gen_data_reg, 0x000100f7);
  357. mdfld_wait_for_HS_CTRL_FIFO(dev, pipe);
  358. REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS));
  359. }
  360. static u16 mdfld_dsi_dpi_to_byte_clock_count(int pixel_clock_count,
  361. int num_lane, int bpp)
  362. {
  363. return (u16)((pixel_clock_count * bpp) / (num_lane * 8));
  364. }
  365. /*
  366. * Calculate the dpi time basing on a given drm mode @mode
  367. * return 0 on success.
  368. * FIXME: I was using proposed mode value for calculation, may need to
  369. * use crtc mode values later
  370. */
  371. int mdfld_dsi_dpi_timing_calculation(struct drm_display_mode *mode,
  372. struct mdfld_dsi_dpi_timing *dpi_timing,
  373. int num_lane, int bpp)
  374. {
  375. int pclk_hsync, pclk_hfp, pclk_hbp, pclk_hactive;
  376. int pclk_vsync, pclk_vfp, pclk_vbp;
  377. pclk_hactive = mode->hdisplay;
  378. pclk_hfp = mode->hsync_start - mode->hdisplay;
  379. pclk_hsync = mode->hsync_end - mode->hsync_start;
  380. pclk_hbp = mode->htotal - mode->hsync_end;
  381. pclk_vfp = mode->vsync_start - mode->vdisplay;
  382. pclk_vsync = mode->vsync_end - mode->vsync_start;
  383. pclk_vbp = mode->vtotal - mode->vsync_end;
  384. /*
  385. * byte clock counts were calculated by following formula
  386. * bclock_count = pclk_count * bpp / num_lane / 8
  387. */
  388. dpi_timing->hsync_count = mdfld_dsi_dpi_to_byte_clock_count(
  389. pclk_hsync, num_lane, bpp);
  390. dpi_timing->hbp_count = mdfld_dsi_dpi_to_byte_clock_count(
  391. pclk_hbp, num_lane, bpp);
  392. dpi_timing->hfp_count = mdfld_dsi_dpi_to_byte_clock_count(
  393. pclk_hfp, num_lane, bpp);
  394. dpi_timing->hactive_count = mdfld_dsi_dpi_to_byte_clock_count(
  395. pclk_hactive, num_lane, bpp);
  396. dpi_timing->vsync_count = mdfld_dsi_dpi_to_byte_clock_count(
  397. pclk_vsync, num_lane, bpp);
  398. dpi_timing->vbp_count = mdfld_dsi_dpi_to_byte_clock_count(
  399. pclk_vbp, num_lane, bpp);
  400. dpi_timing->vfp_count = mdfld_dsi_dpi_to_byte_clock_count(
  401. pclk_vfp, num_lane, bpp);
  402. return 0;
  403. }
  404. void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config *dsi_config,
  405. int pipe)
  406. {
  407. struct drm_device *dev = dsi_config->dev;
  408. int lane_count = dsi_config->lane_count;
  409. struct mdfld_dsi_dpi_timing dpi_timing;
  410. struct drm_display_mode *mode = dsi_config->mode;
  411. u32 val;
  412. /*un-ready device*/
  413. REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0);
  414. /*init dsi adapter before kicking off*/
  415. REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018);
  416. /*enable all interrupts*/
  417. REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff);
  418. /*set up func_prg*/
  419. val = lane_count;
  420. val |= dsi_config->channel_num << DSI_DPI_VIRT_CHANNEL_OFFSET;
  421. switch (dsi_config->bpp) {
  422. case 16:
  423. val |= DSI_DPI_COLOR_FORMAT_RGB565;
  424. break;
  425. case 18:
  426. val |= DSI_DPI_COLOR_FORMAT_RGB666;
  427. break;
  428. case 24:
  429. val |= DSI_DPI_COLOR_FORMAT_RGB888;
  430. break;
  431. default:
  432. DRM_ERROR("unsupported color format, bpp = %d\n",
  433. dsi_config->bpp);
  434. }
  435. REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val);
  436. REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe),
  437. (mode->vtotal * mode->htotal * dsi_config->bpp /
  438. (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK);
  439. REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe),
  440. 0xffff & DSI_LP_RX_TIMEOUT_MASK);
  441. /*max value: 20 clock cycles of txclkesc*/
  442. REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe),
  443. 0x14 & DSI_TURN_AROUND_TIMEOUT_MASK);
  444. /*min 21 txclkesc, max: ffffh*/
  445. REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe),
  446. 0xffff & DSI_RESET_TIMER_MASK);
  447. REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe),
  448. mode->vdisplay << 16 | mode->hdisplay);
  449. /*set DPI timing registers*/
  450. mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing,
  451. dsi_config->lane_count, dsi_config->bpp);
  452. REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe),
  453. dpi_timing.hsync_count & DSI_DPI_TIMING_MASK);
  454. REG_WRITE(MIPI_HBP_COUNT_REG(pipe),
  455. dpi_timing.hbp_count & DSI_DPI_TIMING_MASK);
  456. REG_WRITE(MIPI_HFP_COUNT_REG(pipe),
  457. dpi_timing.hfp_count & DSI_DPI_TIMING_MASK);
  458. REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe),
  459. dpi_timing.hactive_count & DSI_DPI_TIMING_MASK);
  460. REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe),
  461. dpi_timing.vsync_count & DSI_DPI_TIMING_MASK);
  462. REG_WRITE(MIPI_VBP_COUNT_REG(pipe),
  463. dpi_timing.vbp_count & DSI_DPI_TIMING_MASK);
  464. REG_WRITE(MIPI_VFP_COUNT_REG(pipe),
  465. dpi_timing.vfp_count & DSI_DPI_TIMING_MASK);
  466. REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x46);
  467. /*min: 7d0 max: 4e20*/
  468. REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0x000007d0);
  469. /*set up video mode*/
  470. val = dsi_config->video_mode | DSI_DPI_COMPLETE_LAST_LINE;
  471. REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val);
  472. REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000);
  473. REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004);
  474. /*TODO: figure out how to setup these registers*/
  475. if (mdfld_get_panel_type(dev, pipe) == TC35876X)
  476. REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008);
  477. else
  478. REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150c3408);
  479. REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14);
  480. if (mdfld_get_panel_type(dev, pipe) == TC35876X)
  481. tc35876x_set_bridge_reset_state(dev, 0); /*Pull High Reset */
  482. /*set device ready*/
  483. REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0);
  484. }
  485. void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output, int pipe)
  486. {
  487. struct drm_device *dev = output->dev;
  488. /* clear special packet sent bit */
  489. if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT)
  490. REG_WRITE(MIPI_INTR_STAT_REG(pipe),
  491. DSI_INTR_STATE_SPL_PKG_SENT);
  492. /*send turn on package*/
  493. REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_TURN_ON);
  494. /*wait for SPL_PKG_SENT interrupt*/
  495. mdfld_wait_for_SPL_PKG_SENT(dev, pipe);
  496. if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT)
  497. REG_WRITE(MIPI_INTR_STAT_REG(pipe),
  498. DSI_INTR_STATE_SPL_PKG_SENT);
  499. output->panel_on = 1;
  500. /* FIXME the following is disabled to WA the X slow start issue
  501. for TMD panel
  502. if (pipe == 2)
  503. dev_priv->dpi_panel_on2 = true;
  504. else if (pipe == 0)
  505. dev_priv->dpi_panel_on = true; */
  506. }
  507. static void mdfld_dsi_dpi_shut_down(struct mdfld_dsi_dpi_output *output,
  508. int pipe)
  509. {
  510. struct drm_device *dev = output->dev;
  511. /*if output is on, or mode setting didn't happen, ignore this*/
  512. if ((!output->panel_on) || output->first_boot) {
  513. output->first_boot = 0;
  514. return;
  515. }
  516. /* Wait for dpi fifo to empty */
  517. mdfld_wait_for_DPI_CTRL_FIFO(dev, pipe);
  518. /* Clear the special packet interrupt bit if set */
  519. if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT)
  520. REG_WRITE(MIPI_INTR_STAT_REG(pipe),
  521. DSI_INTR_STATE_SPL_PKG_SENT);
  522. if (REG_READ(MIPI_DPI_CONTROL_REG(pipe)) == DSI_DPI_CTRL_HS_SHUTDOWN)
  523. goto shutdown_out;
  524. REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_SHUTDOWN);
  525. shutdown_out:
  526. output->panel_on = 0;
  527. output->first_boot = 0;
  528. /* FIXME the following is disabled to WA the X slow start issue
  529. for TMD panel
  530. if (pipe == 2)
  531. dev_priv->dpi_panel_on2 = false;
  532. else if (pipe == 0)
  533. dev_priv->dpi_panel_on = false; */
  534. }
  535. static void mdfld_dsi_dpi_set_power(struct drm_encoder *encoder, bool on)
  536. {
  537. struct mdfld_dsi_encoder *dsi_encoder = mdfld_dsi_encoder(encoder);
  538. struct mdfld_dsi_dpi_output *dpi_output =
  539. MDFLD_DSI_DPI_OUTPUT(dsi_encoder);
  540. struct mdfld_dsi_config *dsi_config =
  541. mdfld_dsi_encoder_get_config(dsi_encoder);
  542. int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
  543. struct drm_device *dev = dsi_config->dev;
  544. struct drm_psb_private *dev_priv = dev->dev_private;
  545. /*start up display island if it was shutdown*/
  546. if (!gma_power_begin(dev, true))
  547. return;
  548. if (on) {
  549. if (mdfld_get_panel_type(dev, pipe) == TMD_VID)
  550. mdfld_dsi_dpi_turn_on(dpi_output, pipe);
  551. else if (mdfld_get_panel_type(dev, pipe) == TC35876X)
  552. mdfld_dsi_configure_up(dsi_encoder, pipe);
  553. else {
  554. /*enable mipi port*/
  555. REG_WRITE(MIPI_PORT_CONTROL(pipe),
  556. REG_READ(MIPI_PORT_CONTROL(pipe)) | BIT(31));
  557. REG_READ(MIPI_PORT_CONTROL(pipe));
  558. mdfld_dsi_dpi_turn_on(dpi_output, pipe);
  559. mdfld_dsi_tpo_ic_init(dsi_config, pipe);
  560. }
  561. dev_priv->dpi_panel_on[pipe] = true;
  562. } else {
  563. if (mdfld_get_panel_type(dev, pipe) == TMD_VID)
  564. mdfld_dsi_dpi_shut_down(dpi_output, pipe);
  565. else if (mdfld_get_panel_type(dev, pipe) == TC35876X)
  566. mdfld_dsi_configure_down(dsi_encoder, pipe);
  567. else {
  568. mdfld_dsi_dpi_shut_down(dpi_output, pipe);
  569. /*disable mipi port*/
  570. REG_WRITE(MIPI_PORT_CONTROL(pipe),
  571. REG_READ(MIPI_PORT_CONTROL(pipe)) & ~BIT(31));
  572. REG_READ(MIPI_PORT_CONTROL(pipe));
  573. }
  574. dev_priv->dpi_panel_on[pipe] = false;
  575. }
  576. gma_power_end(dev);
  577. }
  578. void mdfld_dsi_dpi_dpms(struct drm_encoder *encoder, int mode)
  579. {
  580. mdfld_dsi_dpi_set_power(encoder, mode == DRM_MODE_DPMS_ON);
  581. }
  582. bool mdfld_dsi_dpi_mode_fixup(struct drm_encoder *encoder,
  583. const struct drm_display_mode *mode,
  584. struct drm_display_mode *adjusted_mode)
  585. {
  586. struct mdfld_dsi_encoder *dsi_encoder = mdfld_dsi_encoder(encoder);
  587. struct mdfld_dsi_config *dsi_config =
  588. mdfld_dsi_encoder_get_config(dsi_encoder);
  589. struct drm_display_mode *fixed_mode = dsi_config->fixed_mode;
  590. if (fixed_mode) {
  591. adjusted_mode->hdisplay = fixed_mode->hdisplay;
  592. adjusted_mode->hsync_start = fixed_mode->hsync_start;
  593. adjusted_mode->hsync_end = fixed_mode->hsync_end;
  594. adjusted_mode->htotal = fixed_mode->htotal;
  595. adjusted_mode->vdisplay = fixed_mode->vdisplay;
  596. adjusted_mode->vsync_start = fixed_mode->vsync_start;
  597. adjusted_mode->vsync_end = fixed_mode->vsync_end;
  598. adjusted_mode->vtotal = fixed_mode->vtotal;
  599. adjusted_mode->clock = fixed_mode->clock;
  600. drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  601. }
  602. return true;
  603. }
  604. void mdfld_dsi_dpi_prepare(struct drm_encoder *encoder)
  605. {
  606. mdfld_dsi_dpi_set_power(encoder, false);
  607. }
  608. void mdfld_dsi_dpi_commit(struct drm_encoder *encoder)
  609. {
  610. mdfld_dsi_dpi_set_power(encoder, true);
  611. }
  612. /* For TC35876X */
  613. /* This functionality was implemented in FW in iCDK */
  614. /* But removed in DV0 and later. So need to add here. */
  615. static void mipi_set_properties(struct mdfld_dsi_config *dsi_config, int pipe)
  616. {
  617. struct drm_device *dev = dsi_config->dev;
  618. REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018);
  619. REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff);
  620. REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), 0xffffff);
  621. REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), 0xffffff);
  622. REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), 0x14);
  623. REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), 0xff);
  624. REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x25);
  625. REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0xf0);
  626. REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000);
  627. REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004);
  628. REG_WRITE(MIPI_DBI_BW_CTRL_REG(pipe), 0x00000820);
  629. REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14);
  630. }
  631. static void mdfld_mipi_set_video_timing(struct mdfld_dsi_config *dsi_config,
  632. int pipe)
  633. {
  634. struct drm_device *dev = dsi_config->dev;
  635. struct mdfld_dsi_dpi_timing dpi_timing;
  636. struct drm_display_mode *mode = dsi_config->mode;
  637. mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing,
  638. dsi_config->lane_count,
  639. dsi_config->bpp);
  640. REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe),
  641. mode->vdisplay << 16 | mode->hdisplay);
  642. REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe),
  643. dpi_timing.hsync_count & DSI_DPI_TIMING_MASK);
  644. REG_WRITE(MIPI_HBP_COUNT_REG(pipe),
  645. dpi_timing.hbp_count & DSI_DPI_TIMING_MASK);
  646. REG_WRITE(MIPI_HFP_COUNT_REG(pipe),
  647. dpi_timing.hfp_count & DSI_DPI_TIMING_MASK);
  648. REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe),
  649. dpi_timing.hactive_count & DSI_DPI_TIMING_MASK);
  650. REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe),
  651. dpi_timing.vsync_count & DSI_DPI_TIMING_MASK);
  652. REG_WRITE(MIPI_VBP_COUNT_REG(pipe),
  653. dpi_timing.vbp_count & DSI_DPI_TIMING_MASK);
  654. REG_WRITE(MIPI_VFP_COUNT_REG(pipe),
  655. dpi_timing.vfp_count & DSI_DPI_TIMING_MASK);
  656. }
  657. static void mdfld_mipi_config(struct mdfld_dsi_config *dsi_config, int pipe)
  658. {
  659. struct drm_device *dev = dsi_config->dev;
  660. int lane_count = dsi_config->lane_count;
  661. if (pipe) {
  662. REG_WRITE(MIPI_PORT_CONTROL(0), 0x00000002);
  663. REG_WRITE(MIPI_PORT_CONTROL(2), 0x80000000);
  664. } else {
  665. REG_WRITE(MIPI_PORT_CONTROL(0), 0x80010000);
  666. REG_WRITE(MIPI_PORT_CONTROL(2), 0x00);
  667. }
  668. REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150A600F);
  669. REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), 0x0000000F);
  670. /* lane_count = 3 */
  671. REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count);
  672. mdfld_mipi_set_video_timing(dsi_config, pipe);
  673. }
  674. static void mdfld_set_pipe_timing(struct mdfld_dsi_config *dsi_config, int pipe)
  675. {
  676. struct drm_device *dev = dsi_config->dev;
  677. struct drm_display_mode *mode = dsi_config->mode;
  678. REG_WRITE(HTOTAL_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1));
  679. REG_WRITE(HBLANK_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1));
  680. REG_WRITE(HSYNC_A,
  681. ((mode->hsync_end - 1) << 16) | (mode->hsync_start - 1));
  682. REG_WRITE(VTOTAL_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1));
  683. REG_WRITE(VBLANK_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1));
  684. REG_WRITE(VSYNC_A,
  685. ((mode->vsync_end - 1) << 16) | (mode->vsync_start - 1));
  686. REG_WRITE(PIPEASRC,
  687. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  688. }
  689. /* End for TC35876X */
  690. void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder,
  691. struct drm_display_mode *mode,
  692. struct drm_display_mode *adjusted_mode)
  693. {
  694. struct mdfld_dsi_encoder *dsi_encoder = mdfld_dsi_encoder(encoder);
  695. struct mdfld_dsi_dpi_output *dpi_output =
  696. MDFLD_DSI_DPI_OUTPUT(dsi_encoder);
  697. struct mdfld_dsi_config *dsi_config =
  698. mdfld_dsi_encoder_get_config(dsi_encoder);
  699. struct drm_device *dev = dsi_config->dev;
  700. struct drm_psb_private *dev_priv = dev->dev_private;
  701. int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
  702. u32 pipeconf_reg = PIPEACONF;
  703. u32 dspcntr_reg = DSPACNTR;
  704. u32 pipeconf, dspcntr;
  705. u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX;
  706. if (WARN_ON(pipe < 0))
  707. return;
  708. pipeconf = dev_priv->pipeconf[pipe];
  709. dspcntr = dev_priv->dspcntr[pipe];
  710. if (pipe) {
  711. pipeconf_reg = PIPECCONF;
  712. dspcntr_reg = DSPCCNTR;
  713. } else {
  714. if (mdfld_get_panel_type(dev, pipe) == TC35876X)
  715. mipi &= (~0x03); /* Use all four lanes */
  716. else
  717. mipi |= 2;
  718. }
  719. /*start up display island if it was shutdown*/
  720. if (!gma_power_begin(dev, true))
  721. return;
  722. if (mdfld_get_panel_type(dev, pipe) == TC35876X) {
  723. /*
  724. * The following logic is required to reset the bridge and
  725. * configure. This also starts the DSI clock at 200MHz.
  726. */
  727. tc35876x_set_bridge_reset_state(dev, 0); /*Pull High Reset */
  728. tc35876x_toshiba_bridge_panel_on(dev);
  729. udelay(100);
  730. /* Now start the DSI clock */
  731. REG_WRITE(MRST_DPLL_A, 0x00);
  732. REG_WRITE(MRST_FPA0, 0xC1);
  733. REG_WRITE(MRST_DPLL_A, 0x00800000);
  734. udelay(500);
  735. REG_WRITE(MRST_DPLL_A, 0x80800000);
  736. if (REG_BIT_WAIT(pipeconf_reg, 1, 29))
  737. dev_err(&dev->pdev->dev, "%s: DSI PLL lock timeout\n",
  738. __func__);
  739. REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008);
  740. mipi_set_properties(dsi_config, pipe);
  741. mdfld_mipi_config(dsi_config, pipe);
  742. mdfld_set_pipe_timing(dsi_config, pipe);
  743. REG_WRITE(DSPABASE, 0x00);
  744. REG_WRITE(DSPASIZE,
  745. ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
  746. REG_WRITE(DSPACNTR, 0x98000000);
  747. REG_WRITE(DSPASURF, 0x00);
  748. REG_WRITE(VGACNTRL, 0x80000000);
  749. REG_WRITE(DEVICE_READY_REG, 0x00000001);
  750. REG_WRITE(MIPI_PORT_CONTROL(pipe), 0x80810000);
  751. } else {
  752. /*set up mipi port FIXME: do at init time */
  753. REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi);
  754. }
  755. REG_READ(MIPI_PORT_CONTROL(pipe));
  756. if (mdfld_get_panel_type(dev, pipe) == TMD_VID) {
  757. /* NOP */
  758. } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) {
  759. /* set up DSI controller DPI interface */
  760. mdfld_dsi_dpi_controller_init(dsi_config, pipe);
  761. /* Configure MIPI Bridge and Panel */
  762. tc35876x_configure_lvds_bridge(dev);
  763. dev_priv->dpi_panel_on[pipe] = true;
  764. } else {
  765. /*turn on DPI interface*/
  766. mdfld_dsi_dpi_turn_on(dpi_output, pipe);
  767. }
  768. /*set up pipe*/
  769. REG_WRITE(pipeconf_reg, pipeconf);
  770. REG_READ(pipeconf_reg);
  771. /*set up display plane*/
  772. REG_WRITE(dspcntr_reg, dspcntr);
  773. REG_READ(dspcntr_reg);
  774. msleep(20); /* FIXME: this should wait for vblank */
  775. if (mdfld_get_panel_type(dev, pipe) == TMD_VID) {
  776. /* NOP */
  777. } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) {
  778. mdfld_dsi_dpi_turn_on(dpi_output, pipe);
  779. } else {
  780. /* init driver ic */
  781. mdfld_dsi_tpo_ic_init(dsi_config, pipe);
  782. /*init backlight*/
  783. mdfld_dsi_brightness_init(dsi_config, pipe);
  784. }
  785. gma_power_end(dev);
  786. }
  787. /*
  788. * Init DSI DPI encoder.
  789. * Allocate an mdfld_dsi_encoder and attach it to given @dsi_connector
  790. * return pointer of newly allocated DPI encoder, NULL on error
  791. */
  792. struct mdfld_dsi_encoder *mdfld_dsi_dpi_init(struct drm_device *dev,
  793. struct mdfld_dsi_connector *dsi_connector,
  794. const struct panel_funcs *p_funcs)
  795. {
  796. struct mdfld_dsi_dpi_output *dpi_output = NULL;
  797. struct mdfld_dsi_config *dsi_config;
  798. struct drm_connector *connector = NULL;
  799. struct drm_encoder *encoder = NULL;
  800. int pipe;
  801. u32 data;
  802. int ret;
  803. pipe = dsi_connector->pipe;
  804. if (mdfld_get_panel_type(dev, pipe) != TC35876X) {
  805. dsi_config = mdfld_dsi_get_config(dsi_connector);
  806. /* panel hard-reset */
  807. if (p_funcs->reset) {
  808. ret = p_funcs->reset(dev, pipe);
  809. if (ret) {
  810. DRM_ERROR("Panel %d hard-reset failed\n", pipe);
  811. return NULL;
  812. }
  813. }
  814. /* panel drvIC init */
  815. if (p_funcs->drv_ic_init)
  816. p_funcs->drv_ic_init(dsi_config, pipe);
  817. /* panel power mode detect */
  818. ret = mdfld_dsi_get_power_mode(dsi_config, &data, false);
  819. if (ret) {
  820. DRM_ERROR("Panel %d get power mode failed\n", pipe);
  821. dsi_connector->status = connector_status_disconnected;
  822. } else {
  823. DRM_INFO("pipe %d power mode 0x%x\n", pipe, data);
  824. dsi_connector->status = connector_status_connected;
  825. }
  826. }
  827. dpi_output = kzalloc(sizeof(struct mdfld_dsi_dpi_output), GFP_KERNEL);
  828. if (!dpi_output) {
  829. DRM_ERROR("No memory\n");
  830. return NULL;
  831. }
  832. dpi_output->panel_on = 0;
  833. dpi_output->dev = dev;
  834. if (mdfld_get_panel_type(dev, pipe) != TC35876X)
  835. dpi_output->p_funcs = p_funcs;
  836. dpi_output->first_boot = 1;
  837. /*get fixed mode*/
  838. dsi_config = mdfld_dsi_get_config(dsi_connector);
  839. /*create drm encoder object*/
  840. connector = &dsi_connector->base.base;
  841. encoder = &dpi_output->base.base.base;
  842. drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_LVDS);
  843. drm_encoder_helper_add(encoder,
  844. p_funcs->encoder_helper_funcs);
  845. /*attach to given connector*/
  846. drm_connector_attach_encoder(connector, encoder);
  847. /*set possible crtcs and clones*/
  848. if (dsi_connector->pipe) {
  849. encoder->possible_crtcs = (1 << 2);
  850. encoder->possible_clones = 0;
  851. } else {
  852. encoder->possible_crtcs = (1 << 0);
  853. encoder->possible_clones = 0;
  854. }
  855. dsi_connector->base.encoder = &dpi_output->base.base;
  856. return &dpi_output->base;
  857. }