intel_gmbus.c 13 KB

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  1. /*
  2. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2008,2010 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. * Chris Wilson <chris@chris-wilson.co.uk>
  28. */
  29. #include <linux/delay.h>
  30. #include <linux/i2c-algo-bit.h>
  31. #include <linux/i2c.h>
  32. #include <linux/module.h>
  33. #include "psb_drv.h"
  34. #include "psb_intel_drv.h"
  35. #include "psb_intel_reg.h"
  36. #define _wait_for(COND, MS, W) ({ \
  37. unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
  38. int ret__ = 0; \
  39. while (! (COND)) { \
  40. if (time_after(jiffies, timeout__)) { \
  41. ret__ = -ETIMEDOUT; \
  42. break; \
  43. } \
  44. if (W && !(in_atomic() || in_dbg_master())) msleep(W); \
  45. } \
  46. ret__; \
  47. })
  48. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  49. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  50. #define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))
  51. #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))
  52. /* Intel GPIO access functions */
  53. #define I2C_RISEFALL_TIME 20
  54. static inline struct intel_gmbus *
  55. to_intel_gmbus(struct i2c_adapter *i2c)
  56. {
  57. return container_of(i2c, struct intel_gmbus, adapter);
  58. }
  59. struct intel_gpio {
  60. struct i2c_adapter adapter;
  61. struct i2c_algo_bit_data algo;
  62. struct drm_psb_private *dev_priv;
  63. u32 reg;
  64. };
  65. void
  66. gma_intel_i2c_reset(struct drm_device *dev)
  67. {
  68. struct drm_psb_private *dev_priv = dev->dev_private;
  69. GMBUS_REG_WRITE(GMBUS0, 0);
  70. }
  71. static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
  72. {
  73. /* When using bit bashing for I2C, this bit needs to be set to 1 */
  74. /* FIXME: We are never Pineview, right?
  75. u32 val;
  76. if (!IS_PINEVIEW(dev_priv->dev))
  77. return;
  78. val = REG_READ(DSPCLK_GATE_D);
  79. if (enable)
  80. val |= DPCUNIT_CLOCK_GATE_DISABLE;
  81. else
  82. val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  83. REG_WRITE(DSPCLK_GATE_D, val);
  84. return;
  85. */
  86. }
  87. static u32 get_reserved(struct intel_gpio *gpio)
  88. {
  89. struct drm_psb_private *dev_priv = gpio->dev_priv;
  90. u32 reserved = 0;
  91. /* On most chips, these bits must be preserved in software. */
  92. reserved = GMBUS_REG_READ(gpio->reg) &
  93. (GPIO_DATA_PULLUP_DISABLE |
  94. GPIO_CLOCK_PULLUP_DISABLE);
  95. return reserved;
  96. }
  97. static int get_clock(void *data)
  98. {
  99. struct intel_gpio *gpio = data;
  100. struct drm_psb_private *dev_priv = gpio->dev_priv;
  101. u32 reserved = get_reserved(gpio);
  102. GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
  103. GMBUS_REG_WRITE(gpio->reg, reserved);
  104. return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
  105. }
  106. static int get_data(void *data)
  107. {
  108. struct intel_gpio *gpio = data;
  109. struct drm_psb_private *dev_priv = gpio->dev_priv;
  110. u32 reserved = get_reserved(gpio);
  111. GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
  112. GMBUS_REG_WRITE(gpio->reg, reserved);
  113. return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
  114. }
  115. static void set_clock(void *data, int state_high)
  116. {
  117. struct intel_gpio *gpio = data;
  118. struct drm_psb_private *dev_priv = gpio->dev_priv;
  119. u32 reserved = get_reserved(gpio);
  120. u32 clock_bits;
  121. if (state_high)
  122. clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
  123. else
  124. clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
  125. GPIO_CLOCK_VAL_MASK;
  126. GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits);
  127. GMBUS_REG_READ(gpio->reg); /* Posting */
  128. }
  129. static void set_data(void *data, int state_high)
  130. {
  131. struct intel_gpio *gpio = data;
  132. struct drm_psb_private *dev_priv = gpio->dev_priv;
  133. u32 reserved = get_reserved(gpio);
  134. u32 data_bits;
  135. if (state_high)
  136. data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
  137. else
  138. data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
  139. GPIO_DATA_VAL_MASK;
  140. GMBUS_REG_WRITE(gpio->reg, reserved | data_bits);
  141. GMBUS_REG_READ(gpio->reg);
  142. }
  143. static struct i2c_adapter *
  144. intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
  145. {
  146. static const int map_pin_to_reg[] = {
  147. 0,
  148. GPIOB,
  149. GPIOA,
  150. GPIOC,
  151. GPIOD,
  152. GPIOE,
  153. 0,
  154. GPIOF,
  155. };
  156. struct intel_gpio *gpio;
  157. if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
  158. return NULL;
  159. gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
  160. if (gpio == NULL)
  161. return NULL;
  162. gpio->reg = map_pin_to_reg[pin];
  163. gpio->dev_priv = dev_priv;
  164. snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
  165. "gma500 GPIO%c", "?BACDE?F"[pin]);
  166. gpio->adapter.owner = THIS_MODULE;
  167. gpio->adapter.algo_data = &gpio->algo;
  168. gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
  169. gpio->algo.setsda = set_data;
  170. gpio->algo.setscl = set_clock;
  171. gpio->algo.getsda = get_data;
  172. gpio->algo.getscl = get_clock;
  173. gpio->algo.udelay = I2C_RISEFALL_TIME;
  174. gpio->algo.timeout = usecs_to_jiffies(2200);
  175. gpio->algo.data = gpio;
  176. if (i2c_bit_add_bus(&gpio->adapter))
  177. goto out_free;
  178. return &gpio->adapter;
  179. out_free:
  180. kfree(gpio);
  181. return NULL;
  182. }
  183. static int
  184. intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
  185. struct i2c_adapter *adapter,
  186. struct i2c_msg *msgs,
  187. int num)
  188. {
  189. struct intel_gpio *gpio = container_of(adapter,
  190. struct intel_gpio,
  191. adapter);
  192. int ret;
  193. gma_intel_i2c_reset(dev_priv->dev);
  194. intel_i2c_quirk_set(dev_priv, true);
  195. set_data(gpio, 1);
  196. set_clock(gpio, 1);
  197. udelay(I2C_RISEFALL_TIME);
  198. ret = adapter->algo->master_xfer(adapter, msgs, num);
  199. set_data(gpio, 1);
  200. set_clock(gpio, 1);
  201. intel_i2c_quirk_set(dev_priv, false);
  202. return ret;
  203. }
  204. static int
  205. gmbus_xfer(struct i2c_adapter *adapter,
  206. struct i2c_msg *msgs,
  207. int num)
  208. {
  209. struct intel_gmbus *bus = container_of(adapter,
  210. struct intel_gmbus,
  211. adapter);
  212. struct drm_psb_private *dev_priv = adapter->algo_data;
  213. int i, reg_offset;
  214. if (bus->force_bit)
  215. return intel_i2c_quirk_xfer(dev_priv,
  216. bus->force_bit, msgs, num);
  217. reg_offset = 0;
  218. GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
  219. for (i = 0; i < num; i++) {
  220. u16 len = msgs[i].len;
  221. u8 *buf = msgs[i].buf;
  222. if (msgs[i].flags & I2C_M_RD) {
  223. GMBUS_REG_WRITE(GMBUS1 + reg_offset,
  224. GMBUS_CYCLE_WAIT |
  225. (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
  226. (len << GMBUS_BYTE_COUNT_SHIFT) |
  227. (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
  228. GMBUS_SLAVE_READ | GMBUS_SW_RDY);
  229. GMBUS_REG_READ(GMBUS2+reg_offset);
  230. do {
  231. u32 val, loop = 0;
  232. if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
  233. (GMBUS_SATOER | GMBUS_HW_RDY), 50))
  234. goto timeout;
  235. if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  236. goto clear_err;
  237. val = GMBUS_REG_READ(GMBUS3 + reg_offset);
  238. do {
  239. *buf++ = val & 0xff;
  240. val >>= 8;
  241. } while (--len && ++loop < 4);
  242. } while (len);
  243. } else {
  244. u32 val, loop;
  245. val = loop = 0;
  246. do {
  247. val |= *buf++ << (8 * loop);
  248. } while (--len && ++loop < 4);
  249. GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
  250. GMBUS_REG_WRITE(GMBUS1 + reg_offset,
  251. (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
  252. (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
  253. (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
  254. GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
  255. GMBUS_REG_READ(GMBUS2+reg_offset);
  256. while (len) {
  257. if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
  258. (GMBUS_SATOER | GMBUS_HW_RDY), 50))
  259. goto timeout;
  260. if (GMBUS_REG_READ(GMBUS2 + reg_offset) &
  261. GMBUS_SATOER)
  262. goto clear_err;
  263. val = loop = 0;
  264. do {
  265. val |= *buf++ << (8 * loop);
  266. } while (--len && ++loop < 4);
  267. GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
  268. GMBUS_REG_READ(GMBUS2+reg_offset);
  269. }
  270. }
  271. if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
  272. goto timeout;
  273. if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  274. goto clear_err;
  275. }
  276. goto done;
  277. clear_err:
  278. /* Toggle the Software Clear Interrupt bit. This has the effect
  279. * of resetting the GMBUS controller and so clearing the
  280. * BUS_ERROR raised by the slave's NAK.
  281. */
  282. GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
  283. GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);
  284. done:
  285. /* Mark the GMBUS interface as disabled. We will re-enable it at the
  286. * start of the next xfer, till then let it sleep.
  287. */
  288. GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
  289. return i;
  290. timeout:
  291. DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
  292. bus->reg0 & 0xff, bus->adapter.name);
  293. GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
  294. /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
  295. bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
  296. if (!bus->force_bit)
  297. return -ENOMEM;
  298. return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
  299. }
  300. static u32 gmbus_func(struct i2c_adapter *adapter)
  301. {
  302. struct intel_gmbus *bus = container_of(adapter,
  303. struct intel_gmbus,
  304. adapter);
  305. if (bus->force_bit)
  306. bus->force_bit->algo->functionality(bus->force_bit);
  307. return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  308. /* I2C_FUNC_10BIT_ADDR | */
  309. I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  310. I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
  311. }
  312. static const struct i2c_algorithm gmbus_algorithm = {
  313. .master_xfer = gmbus_xfer,
  314. .functionality = gmbus_func
  315. };
  316. /**
  317. * intel_gmbus_setup - instantiate all Intel i2c GMBuses
  318. * @dev: DRM device
  319. */
  320. int gma_intel_setup_gmbus(struct drm_device *dev)
  321. {
  322. static const char *names[GMBUS_NUM_PORTS] = {
  323. "disabled",
  324. "ssc",
  325. "vga",
  326. "panel",
  327. "dpc",
  328. "dpb",
  329. "reserved",
  330. "dpd",
  331. };
  332. struct drm_psb_private *dev_priv = dev->dev_private;
  333. int ret, i;
  334. dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
  335. GFP_KERNEL);
  336. if (dev_priv->gmbus == NULL)
  337. return -ENOMEM;
  338. if (IS_MRST(dev))
  339. dev_priv->gmbus_reg = dev_priv->aux_reg;
  340. else
  341. dev_priv->gmbus_reg = dev_priv->vdc_reg;
  342. for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  343. struct intel_gmbus *bus = &dev_priv->gmbus[i];
  344. bus->adapter.owner = THIS_MODULE;
  345. bus->adapter.class = I2C_CLASS_DDC;
  346. snprintf(bus->adapter.name,
  347. sizeof(bus->adapter.name),
  348. "gma500 gmbus %s",
  349. names[i]);
  350. bus->adapter.dev.parent = &dev->pdev->dev;
  351. bus->adapter.algo_data = dev_priv;
  352. bus->adapter.algo = &gmbus_algorithm;
  353. ret = i2c_add_adapter(&bus->adapter);
  354. if (ret)
  355. goto err;
  356. /* By default use a conservative clock rate */
  357. bus->reg0 = i | GMBUS_RATE_100KHZ;
  358. /* XXX force bit banging until GMBUS is fully debugged */
  359. bus->force_bit = intel_gpio_create(dev_priv, i);
  360. }
  361. gma_intel_i2c_reset(dev_priv->dev);
  362. return 0;
  363. err:
  364. while (i--) {
  365. struct intel_gmbus *bus = &dev_priv->gmbus[i];
  366. i2c_del_adapter(&bus->adapter);
  367. }
  368. kfree(dev_priv->gmbus);
  369. dev_priv->gmbus = NULL;
  370. return ret;
  371. }
  372. void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
  373. {
  374. struct intel_gmbus *bus = to_intel_gmbus(adapter);
  375. /* speed:
  376. * 0x0 = 100 KHz
  377. * 0x1 = 50 KHz
  378. * 0x2 = 400 KHz
  379. * 0x3 = 1000 Khz
  380. */
  381. bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
  382. }
  383. void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
  384. {
  385. struct intel_gmbus *bus = to_intel_gmbus(adapter);
  386. if (force_bit) {
  387. if (bus->force_bit == NULL) {
  388. struct drm_psb_private *dev_priv = adapter->algo_data;
  389. bus->force_bit = intel_gpio_create(dev_priv,
  390. bus->reg0 & 0xff);
  391. }
  392. } else {
  393. if (bus->force_bit) {
  394. i2c_del_adapter(bus->force_bit);
  395. kfree(bus->force_bit);
  396. bus->force_bit = NULL;
  397. }
  398. }
  399. }
  400. void gma_intel_teardown_gmbus(struct drm_device *dev)
  401. {
  402. struct drm_psb_private *dev_priv = dev->dev_private;
  403. int i;
  404. if (dev_priv->gmbus == NULL)
  405. return;
  406. for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  407. struct intel_gmbus *bus = &dev_priv->gmbus[i];
  408. if (bus->force_bit) {
  409. i2c_del_adapter(bus->force_bit);
  410. kfree(bus->force_bit);
  411. }
  412. i2c_del_adapter(&bus->adapter);
  413. }
  414. dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */
  415. kfree(dev_priv->gmbus);
  416. dev_priv->gmbus = NULL;
  417. }