intel_bios.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2006 Intel Corporation
  4. *
  5. * Authors:
  6. * Eric Anholt <eric@anholt.net>
  7. */
  8. #ifndef _INTEL_BIOS_H_
  9. #define _INTEL_BIOS_H_
  10. struct drm_device;
  11. struct vbt_header {
  12. u8 signature[20]; /**< Always starts with 'VBT$' */
  13. u16 version; /**< decimal */
  14. u16 header_size; /**< in bytes */
  15. u16 vbt_size; /**< in bytes */
  16. u8 vbt_checksum;
  17. u8 reserved0;
  18. u32 bdb_offset; /**< from beginning of VBT */
  19. u32 aim_offset[4]; /**< from beginning of VBT */
  20. } __packed;
  21. struct bdb_header {
  22. u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
  23. u16 version; /**< decimal */
  24. u16 header_size; /**< in bytes */
  25. u16 bdb_size; /**< in bytes */
  26. };
  27. /* strictly speaking, this is a "skip" block, but it has interesting info */
  28. struct vbios_data {
  29. u8 type; /* 0 == desktop, 1 == mobile */
  30. u8 relstage;
  31. u8 chipset;
  32. u8 lvds_present:1;
  33. u8 tv_present:1;
  34. u8 rsvd2:6; /* finish byte */
  35. u8 rsvd3[4];
  36. u8 signon[155];
  37. u8 copyright[61];
  38. u16 code_segment;
  39. u8 dos_boot_mode;
  40. u8 bandwidth_percent;
  41. u8 rsvd4; /* popup memory size */
  42. u8 resize_pci_bios;
  43. u8 rsvd5; /* is crt already on ddc2 */
  44. } __packed;
  45. /*
  46. * There are several types of BIOS data blocks (BDBs), each block has
  47. * an ID and size in the first 3 bytes (ID in first, size in next 2).
  48. * Known types are listed below.
  49. */
  50. #define BDB_GENERAL_FEATURES 1
  51. #define BDB_GENERAL_DEFINITIONS 2
  52. #define BDB_OLD_TOGGLE_LIST 3
  53. #define BDB_MODE_SUPPORT_LIST 4
  54. #define BDB_GENERIC_MODE_TABLE 5
  55. #define BDB_EXT_MMIO_REGS 6
  56. #define BDB_SWF_IO 7
  57. #define BDB_SWF_MMIO 8
  58. #define BDB_DOT_CLOCK_TABLE 9
  59. #define BDB_MODE_REMOVAL_TABLE 10
  60. #define BDB_CHILD_DEVICE_TABLE 11
  61. #define BDB_DRIVER_FEATURES 12
  62. #define BDB_DRIVER_PERSISTENCE 13
  63. #define BDB_EXT_TABLE_PTRS 14
  64. #define BDB_DOT_CLOCK_OVERRIDE 15
  65. #define BDB_DISPLAY_SELECT 16
  66. /* 17 rsvd */
  67. #define BDB_DRIVER_ROTATION 18
  68. #define BDB_DISPLAY_REMOVE 19
  69. #define BDB_OEM_CUSTOM 20
  70. #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
  71. #define BDB_SDVO_LVDS_OPTIONS 22
  72. #define BDB_SDVO_PANEL_DTDS 23
  73. #define BDB_SDVO_LVDS_PNP_IDS 24
  74. #define BDB_SDVO_LVDS_POWER_SEQ 25
  75. #define BDB_TV_OPTIONS 26
  76. #define BDB_EDP 27
  77. #define BDB_LVDS_OPTIONS 40
  78. #define BDB_LVDS_LFP_DATA_PTRS 41
  79. #define BDB_LVDS_LFP_DATA 42
  80. #define BDB_LVDS_BACKLIGHT 43
  81. #define BDB_LVDS_POWER 44
  82. #define BDB_SKIP 254 /* VBIOS private block, ignore */
  83. struct bdb_general_features {
  84. /* bits 1 */
  85. u8 panel_fitting:2;
  86. u8 flexaim:1;
  87. u8 msg_enable:1;
  88. u8 clear_screen:3;
  89. u8 color_flip:1;
  90. /* bits 2 */
  91. u8 download_ext_vbt:1;
  92. u8 enable_ssc:1;
  93. u8 ssc_freq:1;
  94. u8 enable_lfp_on_override:1;
  95. u8 disable_ssc_ddt:1;
  96. u8 rsvd8:3; /* finish byte */
  97. /* bits 3 */
  98. u8 disable_smooth_vision:1;
  99. u8 single_dvi:1;
  100. u8 rsvd9:6; /* finish byte */
  101. /* bits 4 */
  102. u8 legacy_monitor_detect;
  103. /* bits 5 */
  104. u8 int_crt_support:1;
  105. u8 int_tv_support:1;
  106. u8 int_efp_support:1;
  107. u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
  108. u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
  109. u8 rsvd11:3; /* finish byte */
  110. } __packed;
  111. /* pre-915 */
  112. #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
  113. #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
  114. #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
  115. #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
  116. /* Pre 915 */
  117. #define DEVICE_TYPE_NONE 0x00
  118. #define DEVICE_TYPE_CRT 0x01
  119. #define DEVICE_TYPE_TV 0x09
  120. #define DEVICE_TYPE_EFP 0x12
  121. #define DEVICE_TYPE_LFP 0x22
  122. /* On 915+ */
  123. #define DEVICE_TYPE_CRT_DPMS 0x6001
  124. #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
  125. #define DEVICE_TYPE_TV_COMPOSITE 0x0209
  126. #define DEVICE_TYPE_TV_MACROVISION 0x0289
  127. #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
  128. #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
  129. #define DEVICE_TYPE_TV_SCART 0x0209
  130. #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
  131. #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
  132. #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
  133. #define DEVICE_TYPE_EFP_DVI_I 0x6053
  134. #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
  135. #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
  136. #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
  137. #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
  138. #define DEVICE_TYPE_LFP_PANELLINK 0x5012
  139. #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
  140. #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
  141. #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
  142. #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
  143. #define DEVICE_CFG_NONE 0x00
  144. #define DEVICE_CFG_12BIT_DVOB 0x01
  145. #define DEVICE_CFG_12BIT_DVOC 0x02
  146. #define DEVICE_CFG_24BIT_DVOBC 0x09
  147. #define DEVICE_CFG_24BIT_DVOCB 0x0a
  148. #define DEVICE_CFG_DUAL_DVOB 0x11
  149. #define DEVICE_CFG_DUAL_DVOC 0x12
  150. #define DEVICE_CFG_DUAL_DVOBC 0x13
  151. #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
  152. #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
  153. #define DEVICE_WIRE_NONE 0x00
  154. #define DEVICE_WIRE_DVOB 0x01
  155. #define DEVICE_WIRE_DVOC 0x02
  156. #define DEVICE_WIRE_DVOBC 0x03
  157. #define DEVICE_WIRE_DVOBB 0x05
  158. #define DEVICE_WIRE_DVOCC 0x06
  159. #define DEVICE_WIRE_DVOB_MASTER 0x0d
  160. #define DEVICE_WIRE_DVOC_MASTER 0x0e
  161. #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
  162. #define DEVICE_PORT_DVOB 0x01
  163. #define DEVICE_PORT_DVOC 0x02
  164. struct child_device_config {
  165. u16 handle;
  166. u16 device_type;
  167. u8 device_id[10]; /* ascii string */
  168. u16 addin_offset;
  169. u8 dvo_port; /* See Device_PORT_* above */
  170. u8 i2c_pin;
  171. u8 slave_addr;
  172. u8 ddc_pin;
  173. u16 edid_ptr;
  174. u8 dvo_cfg; /* See DEVICE_CFG_* above */
  175. u8 dvo2_port;
  176. u8 i2c2_pin;
  177. u8 slave2_addr;
  178. u8 ddc2_pin;
  179. u8 capabilities;
  180. u8 dvo_wiring;/* See DEVICE_WIRE_* above */
  181. u8 dvo2_wiring;
  182. u16 extended_type;
  183. u8 dvo_function;
  184. } __packed;
  185. struct bdb_general_definitions {
  186. /* DDC GPIO */
  187. u8 crt_ddc_gmbus_pin;
  188. /* DPMS bits */
  189. u8 dpms_acpi:1;
  190. u8 skip_boot_crt_detect:1;
  191. u8 dpms_aim:1;
  192. u8 rsvd1:5; /* finish byte */
  193. /* boot device bits */
  194. u8 boot_display[2];
  195. u8 child_dev_size;
  196. /*
  197. * Device info:
  198. * If TV is present, it'll be at devices[0].
  199. * LVDS will be next, either devices[0] or [1], if present.
  200. * On some platforms the number of device is 6. But could be as few as
  201. * 4 if both TV and LVDS are missing.
  202. * And the device num is related with the size of general definition
  203. * block. It is obtained by using the following formula:
  204. * number = (block_size - sizeof(bdb_general_definitions))/
  205. * sizeof(child_device_config);
  206. */
  207. struct child_device_config devices[];
  208. };
  209. struct bdb_lvds_options {
  210. u8 panel_type;
  211. u8 rsvd1;
  212. /* LVDS capabilities, stored in a dword */
  213. u8 pfit_mode:2;
  214. u8 pfit_text_mode_enhanced:1;
  215. u8 pfit_gfx_mode_enhanced:1;
  216. u8 pfit_ratio_auto:1;
  217. u8 pixel_dither:1;
  218. u8 lvds_edid:1;
  219. u8 rsvd2:1;
  220. u8 rsvd4;
  221. } __packed;
  222. struct bdb_lvds_backlight {
  223. u8 type:2;
  224. u8 pol:1;
  225. u8 gpio:3;
  226. u8 gmbus:2;
  227. u16 freq;
  228. u8 minbrightness;
  229. u8 i2caddr;
  230. u8 brightnesscmd;
  231. /*FIXME: more...*/
  232. } __packed;
  233. /* LFP pointer table contains entries to the struct below */
  234. struct bdb_lvds_lfp_data_ptr {
  235. u16 fp_timing_offset; /* offsets are from start of bdb */
  236. u8 fp_table_size;
  237. u16 dvo_timing_offset;
  238. u8 dvo_table_size;
  239. u16 panel_pnp_id_offset;
  240. u8 pnp_table_size;
  241. } __packed;
  242. struct bdb_lvds_lfp_data_ptrs {
  243. u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
  244. struct bdb_lvds_lfp_data_ptr ptr[16];
  245. } __packed;
  246. /* LFP data has 3 blocks per entry */
  247. struct lvds_fp_timing {
  248. u16 x_res;
  249. u16 y_res;
  250. u32 lvds_reg;
  251. u32 lvds_reg_val;
  252. u32 pp_on_reg;
  253. u32 pp_on_reg_val;
  254. u32 pp_off_reg;
  255. u32 pp_off_reg_val;
  256. u32 pp_cycle_reg;
  257. u32 pp_cycle_reg_val;
  258. u32 pfit_reg;
  259. u32 pfit_reg_val;
  260. u16 terminator;
  261. } __packed;
  262. struct lvds_dvo_timing {
  263. u16 clock; /**< In 10khz */
  264. u8 hactive_lo;
  265. u8 hblank_lo;
  266. u8 hblank_hi:4;
  267. u8 hactive_hi:4;
  268. u8 vactive_lo;
  269. u8 vblank_lo;
  270. u8 vblank_hi:4;
  271. u8 vactive_hi:4;
  272. u8 hsync_off_lo;
  273. u8 hsync_pulse_width;
  274. u8 vsync_pulse_width:4;
  275. u8 vsync_off:4;
  276. u8 rsvd0:6;
  277. u8 hsync_off_hi:2;
  278. u8 h_image;
  279. u8 v_image;
  280. u8 max_hv;
  281. u8 h_border;
  282. u8 v_border;
  283. u8 rsvd1:3;
  284. u8 digital:2;
  285. u8 vsync_positive:1;
  286. u8 hsync_positive:1;
  287. u8 rsvd2:1;
  288. } __packed;
  289. struct lvds_pnp_id {
  290. u16 mfg_name;
  291. u16 product_code;
  292. u32 serial;
  293. u8 mfg_week;
  294. u8 mfg_year;
  295. } __packed;
  296. struct bdb_lvds_lfp_data_entry {
  297. struct lvds_fp_timing fp_timing;
  298. struct lvds_dvo_timing dvo_timing;
  299. struct lvds_pnp_id pnp_id;
  300. } __packed;
  301. struct bdb_lvds_lfp_data {
  302. struct bdb_lvds_lfp_data_entry data[16];
  303. } __packed;
  304. struct aimdb_header {
  305. char signature[16];
  306. char oem_device[20];
  307. u16 aimdb_version;
  308. u16 aimdb_header_size;
  309. u16 aimdb_size;
  310. } __packed;
  311. struct aimdb_block {
  312. u8 aimdb_id;
  313. u16 aimdb_size;
  314. } __packed;
  315. struct vch_panel_data {
  316. u16 fp_timing_offset;
  317. u8 fp_timing_size;
  318. u16 dvo_timing_offset;
  319. u8 dvo_timing_size;
  320. u16 text_fitting_offset;
  321. u8 text_fitting_size;
  322. u16 graphics_fitting_offset;
  323. u8 graphics_fitting_size;
  324. } __packed;
  325. struct vch_bdb_22 {
  326. struct aimdb_block aimdb_block;
  327. struct vch_panel_data panels[16];
  328. } __packed;
  329. struct bdb_sdvo_lvds_options {
  330. u8 panel_backlight;
  331. u8 h40_set_panel_type;
  332. u8 panel_type;
  333. u8 ssc_clk_freq;
  334. u16 als_low_trip;
  335. u16 als_high_trip;
  336. u8 sclalarcoeff_tab_row_num;
  337. u8 sclalarcoeff_tab_row_size;
  338. u8 coefficient[8];
  339. u8 panel_misc_bits_1;
  340. u8 panel_misc_bits_2;
  341. u8 panel_misc_bits_3;
  342. u8 panel_misc_bits_4;
  343. } __packed;
  344. #define BDB_DRIVER_FEATURE_NO_LVDS 0
  345. #define BDB_DRIVER_FEATURE_INT_LVDS 1
  346. #define BDB_DRIVER_FEATURE_SDVO_LVDS 2
  347. #define BDB_DRIVER_FEATURE_EDP 3
  348. struct bdb_driver_features {
  349. u8 boot_dev_algorithm:1;
  350. u8 block_display_switch:1;
  351. u8 allow_display_switch:1;
  352. u8 hotplug_dvo:1;
  353. u8 dual_view_zoom:1;
  354. u8 int15h_hook:1;
  355. u8 sprite_in_clone:1;
  356. u8 primary_lfp_id:1;
  357. u16 boot_mode_x;
  358. u16 boot_mode_y;
  359. u8 boot_mode_bpp;
  360. u8 boot_mode_refresh;
  361. u16 enable_lfp_primary:1;
  362. u16 selective_mode_pruning:1;
  363. u16 dual_frequency:1;
  364. u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
  365. u16 nt_clone_support:1;
  366. u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
  367. u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
  368. u16 cui_aspect_scaling:1;
  369. u16 preserve_aspect_ratio:1;
  370. u16 sdvo_device_power_down:1;
  371. u16 crt_hotplug:1;
  372. u16 lvds_config:2;
  373. u16 tv_hotplug:1;
  374. u16 hdmi_config:2;
  375. u8 static_display:1;
  376. u8 reserved2:7;
  377. u16 legacy_crt_max_x;
  378. u16 legacy_crt_max_y;
  379. u8 legacy_crt_max_refresh;
  380. u8 hdmi_termination;
  381. u8 custom_vbt_version;
  382. } __packed;
  383. #define EDP_18BPP 0
  384. #define EDP_24BPP 1
  385. #define EDP_30BPP 2
  386. #define EDP_RATE_1_62 0
  387. #define EDP_RATE_2_7 1
  388. #define EDP_LANE_1 0
  389. #define EDP_LANE_2 1
  390. #define EDP_LANE_4 3
  391. #define EDP_PREEMPHASIS_NONE 0
  392. #define EDP_PREEMPHASIS_3_5dB 1
  393. #define EDP_PREEMPHASIS_6dB 2
  394. #define EDP_PREEMPHASIS_9_5dB 3
  395. #define EDP_VSWING_0_4V 0
  396. #define EDP_VSWING_0_6V 1
  397. #define EDP_VSWING_0_8V 2
  398. #define EDP_VSWING_1_2V 3
  399. struct edp_power_seq {
  400. u16 t1_t3;
  401. u16 t8;
  402. u16 t9;
  403. u16 t10;
  404. u16 t11_t12;
  405. } __attribute__ ((packed));
  406. struct edp_link_params {
  407. u8 rate:4;
  408. u8 lanes:4;
  409. u8 preemphasis:4;
  410. u8 vswing:4;
  411. } __attribute__ ((packed));
  412. struct bdb_edp {
  413. struct edp_power_seq power_seqs[16];
  414. u32 color_depth;
  415. u32 sdrrs_msa_timing_delay;
  416. struct edp_link_params link_params[16];
  417. } __attribute__ ((packed));
  418. extern int psb_intel_init_bios(struct drm_device *dev);
  419. extern void psb_intel_destroy_bios(struct drm_device *dev);
  420. /*
  421. * Driver<->VBIOS interaction occurs through scratch bits in
  422. * GR18 & SWF*.
  423. */
  424. /* GR18 bits are set on display switch and hotkey events */
  425. #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
  426. #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
  427. #define GR18_HK_NONE (0x0<<3)
  428. #define GR18_HK_LFP_STRETCH (0x1<<3)
  429. #define GR18_HK_TOGGLE_DISP (0x2<<3)
  430. #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
  431. #define GR18_HK_POPUP_DISABLED (0x6<<3)
  432. #define GR18_HK_POPUP_ENABLED (0x7<<3)
  433. #define GR18_HK_PFIT (0x8<<3)
  434. #define GR18_HK_APM_CHANGE (0xa<<3)
  435. #define GR18_HK_MULTIPLE (0xc<<3)
  436. #define GR18_USER_INT_EN (1<<2)
  437. #define GR18_A0000_FLUSH_EN (1<<1)
  438. #define GR18_SMM_EN (1<<0)
  439. /* Set by driver, cleared by VBIOS */
  440. #define SWF00_YRES_SHIFT 16
  441. #define SWF00_XRES_SHIFT 0
  442. #define SWF00_RES_MASK 0xffff
  443. /* Set by VBIOS at boot time and driver at runtime */
  444. #define SWF01_TV2_FORMAT_SHIFT 8
  445. #define SWF01_TV1_FORMAT_SHIFT 0
  446. #define SWF01_TV_FORMAT_MASK 0xffff
  447. #define SWF10_VBIOS_BLC_I2C_EN (1<<29)
  448. #define SWF10_GTT_OVERRIDE_EN (1<<28)
  449. #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
  450. #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
  451. #define SWF10_OLD_TOGGLE 0x0
  452. #define SWF10_TOGGLE_LIST_1 0x1
  453. #define SWF10_TOGGLE_LIST_2 0x2
  454. #define SWF10_TOGGLE_LIST_3 0x3
  455. #define SWF10_TOGGLE_LIST_4 0x4
  456. #define SWF10_PANNING_EN (1<<23)
  457. #define SWF10_DRIVER_LOADED (1<<22)
  458. #define SWF10_EXTENDED_DESKTOP (1<<21)
  459. #define SWF10_EXCLUSIVE_MODE (1<<20)
  460. #define SWF10_OVERLAY_EN (1<<19)
  461. #define SWF10_PLANEB_HOLDOFF (1<<18)
  462. #define SWF10_PLANEA_HOLDOFF (1<<17)
  463. #define SWF10_VGA_HOLDOFF (1<<16)
  464. #define SWF10_ACTIVE_DISP_MASK 0xffff
  465. #define SWF10_PIPEB_LFP2 (1<<15)
  466. #define SWF10_PIPEB_EFP2 (1<<14)
  467. #define SWF10_PIPEB_TV2 (1<<13)
  468. #define SWF10_PIPEB_CRT2 (1<<12)
  469. #define SWF10_PIPEB_LFP (1<<11)
  470. #define SWF10_PIPEB_EFP (1<<10)
  471. #define SWF10_PIPEB_TV (1<<9)
  472. #define SWF10_PIPEB_CRT (1<<8)
  473. #define SWF10_PIPEA_LFP2 (1<<7)
  474. #define SWF10_PIPEA_EFP2 (1<<6)
  475. #define SWF10_PIPEA_TV2 (1<<5)
  476. #define SWF10_PIPEA_CRT2 (1<<4)
  477. #define SWF10_PIPEA_LFP (1<<3)
  478. #define SWF10_PIPEA_EFP (1<<2)
  479. #define SWF10_PIPEA_TV (1<<1)
  480. #define SWF10_PIPEA_CRT (1<<0)
  481. #define SWF11_MEMORY_SIZE_SHIFT 16
  482. #define SWF11_SV_TEST_EN (1<<15)
  483. #define SWF11_IS_AGP (1<<14)
  484. #define SWF11_DISPLAY_HOLDOFF (1<<13)
  485. #define SWF11_DPMS_REDUCED (1<<12)
  486. #define SWF11_IS_VBE_MODE (1<<11)
  487. #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
  488. #define SWF11_DPMS_MASK 0x07
  489. #define SWF11_DPMS_OFF (1<<2)
  490. #define SWF11_DPMS_SUSPEND (1<<1)
  491. #define SWF11_DPMS_STANDBY (1<<0)
  492. #define SWF11_DPMS_ON 0
  493. #define SWF14_GFX_PFIT_EN (1<<31)
  494. #define SWF14_TEXT_PFIT_EN (1<<30)
  495. #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
  496. #define SWF14_POPUP_EN (1<<28)
  497. #define SWF14_DISPLAY_HOLDOFF (1<<27)
  498. #define SWF14_DISP_DETECT_EN (1<<26)
  499. #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
  500. #define SWF14_DRIVER_STATUS (1<<24)
  501. #define SWF14_OS_TYPE_WIN9X (1<<23)
  502. #define SWF14_OS_TYPE_WINNT (1<<22)
  503. /* 21:19 rsvd */
  504. #define SWF14_PM_TYPE_MASK 0x00070000
  505. #define SWF14_PM_ACPI_VIDEO (0x4 << 16)
  506. #define SWF14_PM_ACPI (0x3 << 16)
  507. #define SWF14_PM_APM_12 (0x2 << 16)
  508. #define SWF14_PM_APM_11 (0x1 << 16)
  509. #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
  510. /* if GR18 indicates a display switch */
  511. #define SWF14_DS_PIPEB_LFP2_EN (1<<15)
  512. #define SWF14_DS_PIPEB_EFP2_EN (1<<14)
  513. #define SWF14_DS_PIPEB_TV2_EN (1<<13)
  514. #define SWF14_DS_PIPEB_CRT2_EN (1<<12)
  515. #define SWF14_DS_PIPEB_LFP_EN (1<<11)
  516. #define SWF14_DS_PIPEB_EFP_EN (1<<10)
  517. #define SWF14_DS_PIPEB_TV_EN (1<<9)
  518. #define SWF14_DS_PIPEB_CRT_EN (1<<8)
  519. #define SWF14_DS_PIPEA_LFP2_EN (1<<7)
  520. #define SWF14_DS_PIPEA_EFP2_EN (1<<6)
  521. #define SWF14_DS_PIPEA_TV2_EN (1<<5)
  522. #define SWF14_DS_PIPEA_CRT2_EN (1<<4)
  523. #define SWF14_DS_PIPEA_LFP_EN (1<<3)
  524. #define SWF14_DS_PIPEA_EFP_EN (1<<2)
  525. #define SWF14_DS_PIPEA_TV_EN (1<<1)
  526. #define SWF14_DS_PIPEA_CRT_EN (1<<0)
  527. /* if GR18 indicates a panel fitting request */
  528. #define SWF14_PFIT_EN (1<<0) /* 0 means disable */
  529. /* if GR18 indicates an APM change request */
  530. #define SWF14_APM_HIBERNATE 0x4
  531. #define SWF14_APM_SUSPEND 0x3
  532. #define SWF14_APM_STANDBY 0x1
  533. #define SWF14_APM_RESTORE 0x0
  534. /* Add the device class for LFP, TV, HDMI */
  535. #define DEVICE_TYPE_INT_LFP 0x1022
  536. #define DEVICE_TYPE_INT_TV 0x1009
  537. #define DEVICE_TYPE_HDMI 0x60D2
  538. #define DEVICE_TYPE_DP 0x68C6
  539. #define DEVICE_TYPE_eDP 0x78C6
  540. /* define the DVO port for HDMI output type */
  541. #define DVO_B 1
  542. #define DVO_C 2
  543. #define DVO_D 3
  544. /* define the PORT for DP output type */
  545. #define PORT_IDPB 7
  546. #define PORT_IDPC 8
  547. #define PORT_IDPD 9
  548. #endif /* _INTEL_BIOS_H_ */