cdv_device.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /**************************************************************************
  3. * Copyright (c) 2011, Intel Corporation.
  4. * All Rights Reserved.
  5. *
  6. **************************************************************************/
  7. #include <linux/backlight.h>
  8. #include <linux/delay.h>
  9. #include <drm/drm.h>
  10. #include "cdv_device.h"
  11. #include "gma_device.h"
  12. #include "intel_bios.h"
  13. #include "psb_drv.h"
  14. #include "psb_intel_reg.h"
  15. #include "psb_reg.h"
  16. #define VGA_SR_INDEX 0x3c4
  17. #define VGA_SR_DATA 0x3c5
  18. static void cdv_disable_vga(struct drm_device *dev)
  19. {
  20. u8 sr1;
  21. u32 vga_reg;
  22. vga_reg = VGACNTRL;
  23. outb(1, VGA_SR_INDEX);
  24. sr1 = inb(VGA_SR_DATA);
  25. outb(sr1 | 1<<5, VGA_SR_DATA);
  26. udelay(300);
  27. REG_WRITE(vga_reg, VGA_DISP_DISABLE);
  28. REG_READ(vga_reg);
  29. }
  30. static int cdv_output_init(struct drm_device *dev)
  31. {
  32. struct drm_psb_private *dev_priv = dev->dev_private;
  33. drm_mode_create_scaling_mode_property(dev);
  34. cdv_disable_vga(dev);
  35. cdv_intel_crt_init(dev, &dev_priv->mode_dev);
  36. cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
  37. /* These bits indicate HDMI not SDVO on CDV */
  38. if (REG_READ(SDVOB) & SDVO_DETECTED) {
  39. cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
  40. if (REG_READ(DP_B) & DP_DETECTED)
  41. cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B);
  42. }
  43. if (REG_READ(SDVOC) & SDVO_DETECTED) {
  44. cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
  45. if (REG_READ(DP_C) & DP_DETECTED)
  46. cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C);
  47. }
  48. return 0;
  49. }
  50. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  51. /*
  52. * Cedartrail Backlght Interfaces
  53. */
  54. static struct backlight_device *cdv_backlight_device;
  55. static int cdv_backlight_combination_mode(struct drm_device *dev)
  56. {
  57. return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
  58. }
  59. static u32 cdv_get_max_backlight(struct drm_device *dev)
  60. {
  61. u32 max = REG_READ(BLC_PWM_CTL);
  62. if (max == 0) {
  63. DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n");
  64. /* i915 does this, I believe which means that we should not
  65. * smash PWM control as firmware will take control of it. */
  66. return 1;
  67. }
  68. max >>= 16;
  69. if (cdv_backlight_combination_mode(dev))
  70. max *= 0xff;
  71. return max;
  72. }
  73. static int cdv_get_brightness(struct backlight_device *bd)
  74. {
  75. struct drm_device *dev = bl_get_data(bd);
  76. u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  77. if (cdv_backlight_combination_mode(dev)) {
  78. u8 lbpc;
  79. val &= ~1;
  80. pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
  81. val *= lbpc;
  82. }
  83. return (val * 100)/cdv_get_max_backlight(dev);
  84. }
  85. static int cdv_set_brightness(struct backlight_device *bd)
  86. {
  87. struct drm_device *dev = bl_get_data(bd);
  88. int level = bd->props.brightness;
  89. u32 blc_pwm_ctl;
  90. /* Percentage 1-100% being valid */
  91. if (level < 1)
  92. level = 1;
  93. level *= cdv_get_max_backlight(dev);
  94. level /= 100;
  95. if (cdv_backlight_combination_mode(dev)) {
  96. u32 max = cdv_get_max_backlight(dev);
  97. u8 lbpc;
  98. lbpc = level * 0xfe / max + 1;
  99. level /= lbpc;
  100. pci_write_config_byte(dev->pdev, 0xF4, lbpc);
  101. }
  102. blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
  103. REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl |
  104. (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
  105. return 0;
  106. }
  107. static const struct backlight_ops cdv_ops = {
  108. .get_brightness = cdv_get_brightness,
  109. .update_status = cdv_set_brightness,
  110. };
  111. static int cdv_backlight_init(struct drm_device *dev)
  112. {
  113. struct drm_psb_private *dev_priv = dev->dev_private;
  114. struct backlight_properties props;
  115. memset(&props, 0, sizeof(struct backlight_properties));
  116. props.max_brightness = 100;
  117. props.type = BACKLIGHT_PLATFORM;
  118. cdv_backlight_device = backlight_device_register("psb-bl",
  119. NULL, (void *)dev, &cdv_ops, &props);
  120. if (IS_ERR(cdv_backlight_device))
  121. return PTR_ERR(cdv_backlight_device);
  122. cdv_backlight_device->props.brightness =
  123. cdv_get_brightness(cdv_backlight_device);
  124. backlight_update_status(cdv_backlight_device);
  125. dev_priv->backlight_device = cdv_backlight_device;
  126. dev_priv->backlight_enabled = true;
  127. return 0;
  128. }
  129. #endif
  130. /*
  131. * Provide the Cedarview specific chip logic and low level methods
  132. * for power management
  133. *
  134. * FIXME: we need to implement the apm/ospm base management bits
  135. * for this and the MID devices.
  136. */
  137. static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset)
  138. {
  139. int mcr = (0x10<<24) | (port << 16) | (offset << 8);
  140. uint32_t ret_val = 0;
  141. struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
  142. pci_write_config_dword(pci_root, 0xD0, mcr);
  143. pci_read_config_dword(pci_root, 0xD4, &ret_val);
  144. pci_dev_put(pci_root);
  145. return ret_val;
  146. }
  147. static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset,
  148. u32 value)
  149. {
  150. int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
  151. struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
  152. pci_write_config_dword(pci_root, 0xD4, value);
  153. pci_write_config_dword(pci_root, 0xD0, mcr);
  154. pci_dev_put(pci_root);
  155. }
  156. #define PSB_PM_SSC 0x20
  157. #define PSB_PM_SSS 0x30
  158. #define PSB_PWRGT_GFX_ON 0x02
  159. #define PSB_PWRGT_GFX_OFF 0x01
  160. #define PSB_PWRGT_GFX_D0 0x00
  161. #define PSB_PWRGT_GFX_D3 0x03
  162. static void cdv_init_pm(struct drm_device *dev)
  163. {
  164. struct drm_psb_private *dev_priv = dev->dev_private;
  165. u32 pwr_cnt;
  166. int domain = pci_domain_nr(dev->pdev->bus);
  167. int i;
  168. dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
  169. PSB_APMBA) & 0xFFFF;
  170. dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
  171. PSB_OSPMBA) & 0xFFFF;
  172. /* Power status */
  173. pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
  174. /* Enable the GPU */
  175. pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
  176. pwr_cnt |= PSB_PWRGT_GFX_ON;
  177. outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
  178. /* Wait for the GPU power */
  179. for (i = 0; i < 5; i++) {
  180. u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
  181. if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
  182. return;
  183. udelay(10);
  184. }
  185. dev_err(dev->dev, "GPU: power management timed out.\n");
  186. }
  187. static void cdv_errata(struct drm_device *dev)
  188. {
  189. /* Disable bonus launch.
  190. * CPU and GPU competes for memory and display misses updates and
  191. * flickers. Worst with dual core, dual displays.
  192. *
  193. * Fixes were done to Win 7 gfx driver to disable a feature called
  194. * Bonus Launch to work around the issue, by degrading
  195. * performance.
  196. */
  197. CDV_MSG_WRITE32(pci_domain_nr(dev->pdev->bus), 3, 0x30, 0x08027108);
  198. }
  199. /**
  200. * cdv_save_display_registers - save registers lost on suspend
  201. * @dev: our DRM device
  202. *
  203. * Save the state we need in order to be able to restore the interface
  204. * upon resume from suspend
  205. */
  206. static int cdv_save_display_registers(struct drm_device *dev)
  207. {
  208. struct drm_psb_private *dev_priv = dev->dev_private;
  209. struct psb_save_area *regs = &dev_priv->regs;
  210. struct drm_connector *connector;
  211. dev_dbg(dev->dev, "Saving GPU registers.\n");
  212. pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);
  213. regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
  214. regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
  215. regs->cdv.saveDSPARB = REG_READ(DSPARB);
  216. regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
  217. regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
  218. regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
  219. regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
  220. regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
  221. regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
  222. regs->cdv.saveADPA = REG_READ(ADPA);
  223. regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
  224. regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
  225. regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
  226. regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
  227. regs->cdv.saveLVDS = REG_READ(LVDS);
  228. regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
  229. regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
  230. regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
  231. regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
  232. regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
  233. regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
  234. regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
  235. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  236. connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
  237. return 0;
  238. }
  239. /**
  240. * cdv_restore_display_registers - restore lost register state
  241. * @dev: our DRM device
  242. *
  243. * Restore register state that was lost during suspend and resume.
  244. *
  245. * FIXME: review
  246. */
  247. static int cdv_restore_display_registers(struct drm_device *dev)
  248. {
  249. struct drm_psb_private *dev_priv = dev->dev_private;
  250. struct psb_save_area *regs = &dev_priv->regs;
  251. struct drm_connector *connector;
  252. u32 temp;
  253. pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
  254. REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
  255. REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
  256. /* BIOS does below anyway */
  257. REG_WRITE(DPIO_CFG, 0);
  258. REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
  259. temp = REG_READ(DPLL_A);
  260. if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
  261. REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
  262. REG_READ(DPLL_A);
  263. }
  264. temp = REG_READ(DPLL_B);
  265. if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
  266. REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
  267. REG_READ(DPLL_B);
  268. }
  269. udelay(500);
  270. REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
  271. REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
  272. REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
  273. REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
  274. REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
  275. REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
  276. REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
  277. REG_WRITE(ADPA, regs->cdv.saveADPA);
  278. REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
  279. REG_WRITE(LVDS, regs->cdv.saveLVDS);
  280. REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
  281. REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
  282. REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
  283. REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
  284. REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
  285. REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
  286. REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
  287. REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
  288. REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
  289. REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
  290. /* Fix arbitration bug */
  291. cdv_errata(dev);
  292. drm_mode_config_reset(dev);
  293. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  294. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  295. /* Resume the modeset for every activated CRTC */
  296. drm_helper_resume_force_mode(dev);
  297. return 0;
  298. }
  299. static int cdv_power_down(struct drm_device *dev)
  300. {
  301. struct drm_psb_private *dev_priv = dev->dev_private;
  302. u32 pwr_cnt, pwr_mask, pwr_sts;
  303. int tries = 5;
  304. pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
  305. pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
  306. pwr_cnt |= PSB_PWRGT_GFX_OFF;
  307. pwr_mask = PSB_PWRGT_GFX_MASK;
  308. outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
  309. while (tries--) {
  310. pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
  311. if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
  312. return 0;
  313. udelay(10);
  314. }
  315. return 0;
  316. }
  317. static int cdv_power_up(struct drm_device *dev)
  318. {
  319. struct drm_psb_private *dev_priv = dev->dev_private;
  320. u32 pwr_cnt, pwr_mask, pwr_sts;
  321. int tries = 5;
  322. pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
  323. pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
  324. pwr_cnt |= PSB_PWRGT_GFX_ON;
  325. pwr_mask = PSB_PWRGT_GFX_MASK;
  326. outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
  327. while (tries--) {
  328. pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
  329. if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
  330. return 0;
  331. udelay(10);
  332. }
  333. return 0;
  334. }
  335. static void cdv_hotplug_work_func(struct work_struct *work)
  336. {
  337. struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
  338. hotplug_work);
  339. struct drm_device *dev = dev_priv->dev;
  340. /* Just fire off a uevent and let userspace tell us what to do */
  341. drm_helper_hpd_irq_event(dev);
  342. }
  343. /* The core driver has received a hotplug IRQ. We are in IRQ context
  344. so extract the needed information and kick off queued processing */
  345. static int cdv_hotplug_event(struct drm_device *dev)
  346. {
  347. struct drm_psb_private *dev_priv = dev->dev_private;
  348. schedule_work(&dev_priv->hotplug_work);
  349. REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
  350. return 1;
  351. }
  352. static void cdv_hotplug_enable(struct drm_device *dev, bool on)
  353. {
  354. if (on) {
  355. u32 hotplug = REG_READ(PORT_HOTPLUG_EN);
  356. hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN |
  357. HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN;
  358. REG_WRITE(PORT_HOTPLUG_EN, hotplug);
  359. } else {
  360. REG_WRITE(PORT_HOTPLUG_EN, 0);
  361. REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
  362. }
  363. }
  364. static const char *force_audio_names[] = {
  365. "off",
  366. "auto",
  367. "on",
  368. };
  369. void cdv_intel_attach_force_audio_property(struct drm_connector *connector)
  370. {
  371. struct drm_device *dev = connector->dev;
  372. struct drm_psb_private *dev_priv = dev->dev_private;
  373. struct drm_property *prop;
  374. int i;
  375. prop = dev_priv->force_audio_property;
  376. if (prop == NULL) {
  377. prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
  378. "audio",
  379. ARRAY_SIZE(force_audio_names));
  380. if (prop == NULL)
  381. return;
  382. for (i = 0; i < ARRAY_SIZE(force_audio_names); i++)
  383. drm_property_add_enum(prop, i-1, force_audio_names[i]);
  384. dev_priv->force_audio_property = prop;
  385. }
  386. drm_object_attach_property(&connector->base, prop, 0);
  387. }
  388. static const char *broadcast_rgb_names[] = {
  389. "Full",
  390. "Limited 16:235",
  391. };
  392. void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector)
  393. {
  394. struct drm_device *dev = connector->dev;
  395. struct drm_psb_private *dev_priv = dev->dev_private;
  396. struct drm_property *prop;
  397. int i;
  398. prop = dev_priv->broadcast_rgb_property;
  399. if (prop == NULL) {
  400. prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
  401. "Broadcast RGB",
  402. ARRAY_SIZE(broadcast_rgb_names));
  403. if (prop == NULL)
  404. return;
  405. for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++)
  406. drm_property_add_enum(prop, i, broadcast_rgb_names[i]);
  407. dev_priv->broadcast_rgb_property = prop;
  408. }
  409. drm_object_attach_property(&connector->base, prop, 0);
  410. }
  411. /* Cedarview */
  412. static const struct psb_offset cdv_regmap[2] = {
  413. {
  414. .fp0 = FPA0,
  415. .fp1 = FPA1,
  416. .cntr = DSPACNTR,
  417. .conf = PIPEACONF,
  418. .src = PIPEASRC,
  419. .dpll = DPLL_A,
  420. .dpll_md = DPLL_A_MD,
  421. .htotal = HTOTAL_A,
  422. .hblank = HBLANK_A,
  423. .hsync = HSYNC_A,
  424. .vtotal = VTOTAL_A,
  425. .vblank = VBLANK_A,
  426. .vsync = VSYNC_A,
  427. .stride = DSPASTRIDE,
  428. .size = DSPASIZE,
  429. .pos = DSPAPOS,
  430. .base = DSPABASE,
  431. .surf = DSPASURF,
  432. .addr = DSPABASE,
  433. .status = PIPEASTAT,
  434. .linoff = DSPALINOFF,
  435. .tileoff = DSPATILEOFF,
  436. .palette = PALETTE_A,
  437. },
  438. {
  439. .fp0 = FPB0,
  440. .fp1 = FPB1,
  441. .cntr = DSPBCNTR,
  442. .conf = PIPEBCONF,
  443. .src = PIPEBSRC,
  444. .dpll = DPLL_B,
  445. .dpll_md = DPLL_B_MD,
  446. .htotal = HTOTAL_B,
  447. .hblank = HBLANK_B,
  448. .hsync = HSYNC_B,
  449. .vtotal = VTOTAL_B,
  450. .vblank = VBLANK_B,
  451. .vsync = VSYNC_B,
  452. .stride = DSPBSTRIDE,
  453. .size = DSPBSIZE,
  454. .pos = DSPBPOS,
  455. .base = DSPBBASE,
  456. .surf = DSPBSURF,
  457. .addr = DSPBBASE,
  458. .status = PIPEBSTAT,
  459. .linoff = DSPBLINOFF,
  460. .tileoff = DSPBTILEOFF,
  461. .palette = PALETTE_B,
  462. }
  463. };
  464. static int cdv_chip_setup(struct drm_device *dev)
  465. {
  466. struct drm_psb_private *dev_priv = dev->dev_private;
  467. INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
  468. if (pci_enable_msi(dev->pdev))
  469. dev_warn(dev->dev, "Enabling MSI failed!\n");
  470. dev_priv->regmap = cdv_regmap;
  471. gma_get_core_freq(dev);
  472. psb_intel_opregion_init(dev);
  473. psb_intel_init_bios(dev);
  474. cdv_hotplug_enable(dev, false);
  475. return 0;
  476. }
  477. /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
  478. const struct psb_ops cdv_chip_ops = {
  479. .name = "GMA3600/3650",
  480. .accel_2d = 0,
  481. .pipes = 2,
  482. .crtcs = 2,
  483. .hdmi_mask = (1 << 0) | (1 << 1),
  484. .lvds_mask = (1 << 1),
  485. .sdvo_mask = (1 << 0),
  486. .cursor_needs_phys = 0,
  487. .sgx_offset = MRST_SGX_OFFSET,
  488. .chip_setup = cdv_chip_setup,
  489. .errata = cdv_errata,
  490. .crtc_helper = &cdv_intel_helper_funcs,
  491. .crtc_funcs = &cdv_intel_crtc_funcs,
  492. .clock_funcs = &cdv_clock_funcs,
  493. .output_init = cdv_output_init,
  494. .hotplug = cdv_hotplug_event,
  495. .hotplug_enable = cdv_hotplug_enable,
  496. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  497. .backlight_init = cdv_backlight_init,
  498. #endif
  499. .init_pm = cdv_init_pm,
  500. .save_regs = cdv_save_display_registers,
  501. .restore_regs = cdv_restore_display_registers,
  502. .save_crtc = gma_crtc_save,
  503. .restore_crtc = gma_crtc_restore,
  504. .power_down = cdv_power_down,
  505. .power_up = cdv_power_up,
  506. .update_wm = cdv_update_wm,
  507. .disable_sr = cdv_disable_sr,
  508. };