fsl_dcu_drm_drv.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Freescale DCU drm device driver
  6. */
  7. #ifndef __FSL_DCU_DRM_DRV_H__
  8. #define __FSL_DCU_DRM_DRV_H__
  9. #include <drm/drm_encoder.h>
  10. #include "fsl_dcu_drm_crtc.h"
  11. #include "fsl_dcu_drm_output.h"
  12. #include "fsl_dcu_drm_plane.h"
  13. #define DCU_DCU_MODE 0x0010
  14. #define DCU_MODE_BLEND_ITER(x) ((x) << 20)
  15. #define DCU_MODE_RASTER_EN BIT(14)
  16. #define DCU_MODE_DCU_MODE(x) (x)
  17. #define DCU_MODE_DCU_MODE_MASK 0x03
  18. #define DCU_MODE_OFF 0
  19. #define DCU_MODE_NORMAL 1
  20. #define DCU_MODE_TEST 2
  21. #define DCU_MODE_COLORBAR 3
  22. #define DCU_BGND 0x0014
  23. #define DCU_BGND_R(x) ((x) << 16)
  24. #define DCU_BGND_G(x) ((x) << 8)
  25. #define DCU_BGND_B(x) (x)
  26. #define DCU_DISP_SIZE 0x0018
  27. #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
  28. /*Regisiter value 1/16 of horizontal resolution*/
  29. #define DCU_DISP_SIZE_DELTA_X(x) ((x) >> 4)
  30. #define DCU_HSYN_PARA 0x001c
  31. #define DCU_HSYN_PARA_BP(x) ((x) << 22)
  32. #define DCU_HSYN_PARA_PW(x) ((x) << 11)
  33. #define DCU_HSYN_PARA_FP(x) (x)
  34. #define DCU_VSYN_PARA 0x0020
  35. #define DCU_VSYN_PARA_BP(x) ((x) << 22)
  36. #define DCU_VSYN_PARA_PW(x) ((x) << 11)
  37. #define DCU_VSYN_PARA_FP(x) (x)
  38. #define DCU_SYN_POL 0x0024
  39. #define DCU_SYN_POL_INV_PXCK BIT(6)
  40. #define DCU_SYN_POL_NEG BIT(5)
  41. #define DCU_SYN_POL_INV_VS_LOW BIT(1)
  42. #define DCU_SYN_POL_INV_HS_LOW BIT(0)
  43. #define DCU_THRESHOLD 0x0028
  44. #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
  45. #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
  46. #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
  47. #define BF_VS_VAL 0x03
  48. #define BUF_MAX_VAL 0x78
  49. #define BUF_MIN_VAL 0x0a
  50. #define DCU_INT_STATUS 0x002C
  51. #define DCU_INT_STATUS_VSYNC BIT(0)
  52. #define DCU_INT_STATUS_UNDRUN BIT(1)
  53. #define DCU_INT_STATUS_LSBFVS BIT(2)
  54. #define DCU_INT_STATUS_VBLANK BIT(3)
  55. #define DCU_INT_STATUS_CRCREADY BIT(4)
  56. #define DCU_INT_STATUS_CRCOVERFLOW BIT(5)
  57. #define DCU_INT_STATUS_P1FIFOLO BIT(6)
  58. #define DCU_INT_STATUS_P1FIFOHI BIT(7)
  59. #define DCU_INT_STATUS_P2FIFOLO BIT(8)
  60. #define DCU_INT_STATUS_P2FIFOHI BIT(9)
  61. #define DCU_INT_STATUS_PROGEND BIT(10)
  62. #define DCU_INT_STATUS_IPMERROR BIT(11)
  63. #define DCU_INT_STATUS_LYRTRANS BIT(12)
  64. #define DCU_INT_STATUS_DMATRANS BIT(14)
  65. #define DCU_INT_STATUS_P3FIFOLO BIT(16)
  66. #define DCU_INT_STATUS_P3FIFOHI BIT(17)
  67. #define DCU_INT_STATUS_P4FIFOLO BIT(18)
  68. #define DCU_INT_STATUS_P4FIFOHI BIT(19)
  69. #define DCU_INT_STATUS_P1EMPTY BIT(26)
  70. #define DCU_INT_STATUS_P2EMPTY BIT(27)
  71. #define DCU_INT_STATUS_P3EMPTY BIT(28)
  72. #define DCU_INT_STATUS_P4EMPTY BIT(29)
  73. #define DCU_INT_MASK 0x0030
  74. #define DCU_INT_MASK_VSYNC BIT(0)
  75. #define DCU_INT_MASK_UNDRUN BIT(1)
  76. #define DCU_INT_MASK_LSBFVS BIT(2)
  77. #define DCU_INT_MASK_VBLANK BIT(3)
  78. #define DCU_INT_MASK_CRCREADY BIT(4)
  79. #define DCU_INT_MASK_CRCOVERFLOW BIT(5)
  80. #define DCU_INT_MASK_P1FIFOLO BIT(6)
  81. #define DCU_INT_MASK_P1FIFOHI BIT(7)
  82. #define DCU_INT_MASK_P2FIFOLO BIT(8)
  83. #define DCU_INT_MASK_P2FIFOHI BIT(9)
  84. #define DCU_INT_MASK_PROGEND BIT(10)
  85. #define DCU_INT_MASK_IPMERROR BIT(11)
  86. #define DCU_INT_MASK_LYRTRANS BIT(12)
  87. #define DCU_INT_MASK_DMATRANS BIT(14)
  88. #define DCU_INT_MASK_P3FIFOLO BIT(16)
  89. #define DCU_INT_MASK_P3FIFOHI BIT(17)
  90. #define DCU_INT_MASK_P4FIFOLO BIT(18)
  91. #define DCU_INT_MASK_P4FIFOHI BIT(19)
  92. #define DCU_INT_MASK_P1EMPTY BIT(26)
  93. #define DCU_INT_MASK_P2EMPTY BIT(27)
  94. #define DCU_INT_MASK_P3EMPTY BIT(28)
  95. #define DCU_INT_MASK_P4EMPTY BIT(29)
  96. #define DCU_DIV_RATIO 0x0054
  97. #define DCU_UPDATE_MODE 0x00cc
  98. #define DCU_UPDATE_MODE_MODE BIT(31)
  99. #define DCU_UPDATE_MODE_READREG BIT(30)
  100. #define DCU_DCFB_MAX 0x300
  101. #define DCU_CTRLDESCLN(layer, reg) (0x200 + (reg - 1) * 4 + (layer) * 0x40)
  102. #define DCU_LAYER_HEIGHT(x) ((x) << 16)
  103. #define DCU_LAYER_WIDTH(x) (x)
  104. #define DCU_LAYER_POSY(x) ((x) << 16)
  105. #define DCU_LAYER_POSX(x) (x)
  106. #define DCU_LAYER_EN BIT(31)
  107. #define DCU_LAYER_TILE_EN BIT(30)
  108. #define DCU_LAYER_DATA_SEL_CLUT BIT(29)
  109. #define DCU_LAYER_SAFETY_EN BIT(28)
  110. #define DCU_LAYER_TRANS(x) ((x) << 20)
  111. #define DCU_LAYER_BPP(x) ((x) << 16)
  112. #define DCU_LAYER_RLE_EN BIT(15)
  113. #define DCU_LAYER_LUOFFS(x) ((x) << 4)
  114. #define DCU_LAYER_BB_ON BIT(2)
  115. #define DCU_LAYER_AB_NONE 0
  116. #define DCU_LAYER_AB_CHROMA_KEYING 1
  117. #define DCU_LAYER_AB_WHOLE_FRAME 2
  118. #define DCU_LAYER_CKMAX_R(x) ((x) << 16)
  119. #define DCU_LAYER_CKMAX_G(x) ((x) << 8)
  120. #define DCU_LAYER_CKMAX_B(x) (x)
  121. #define DCU_LAYER_CKMIN_R(x) ((x) << 16)
  122. #define DCU_LAYER_CKMIN_G(x) ((x) << 8)
  123. #define DCU_LAYER_CKMIN_B(x) (x)
  124. #define DCU_LAYER_TILE_VER(x) ((x) << 16)
  125. #define DCU_LAYER_TILE_HOR(x) (x)
  126. #define DCU_LAYER_FG_FCOLOR(x) (x)
  127. #define DCU_LAYER_BG_BCOLOR(x) (x)
  128. #define DCU_LAYER_POST_SKIP(x) ((x) << 16)
  129. #define DCU_LAYER_PRE_SKIP(x) (x)
  130. #define FSL_DCU_RGB565 4
  131. #define FSL_DCU_RGB888 5
  132. #define FSL_DCU_ARGB8888 6
  133. #define FSL_DCU_ARGB1555 11
  134. #define FSL_DCU_ARGB4444 12
  135. #define FSL_DCU_YUV422 14
  136. #define VF610_LAYER_REG_NUM 9
  137. #define LS1021A_LAYER_REG_NUM 10
  138. struct clk;
  139. struct device;
  140. struct drm_device;
  141. struct fsl_dcu_soc_data {
  142. const char *name;
  143. /*total layer number*/
  144. unsigned int total_layer;
  145. /*max layer number DCU supported*/
  146. unsigned int max_layer;
  147. unsigned int layer_regs;
  148. };
  149. struct fsl_dcu_drm_device {
  150. struct device *dev;
  151. struct device_node *np;
  152. struct regmap *regmap;
  153. int irq;
  154. struct clk *clk;
  155. struct clk *pix_clk;
  156. struct fsl_tcon *tcon;
  157. /*protects hardware register*/
  158. spinlock_t irq_lock;
  159. struct drm_device *drm;
  160. struct drm_crtc crtc;
  161. struct drm_encoder encoder;
  162. struct fsl_dcu_drm_connector connector;
  163. const struct fsl_dcu_soc_data *soc;
  164. };
  165. int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev);
  166. #endif /* __FSL_DCU_DRM_DRV_H__ */