fsl_dcu_drm_drv.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Freescale DCU drm device driver
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/console.h>
  10. #include <linux/io.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/mm.h>
  13. #include <linux/module.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/regmap.h>
  19. #include <drm/drm_atomic_helper.h>
  20. #include <drm/drm_drv.h>
  21. #include <drm/drm_fb_cma_helper.h>
  22. #include <drm/drm_fb_helper.h>
  23. #include <drm/drm_gem_cma_helper.h>
  24. #include <drm/drm_irq.h>
  25. #include <drm/drm_modeset_helper.h>
  26. #include <drm/drm_probe_helper.h>
  27. #include <drm/drm_vblank.h>
  28. #include "fsl_dcu_drm_crtc.h"
  29. #include "fsl_dcu_drm_drv.h"
  30. #include "fsl_tcon.h"
  31. static int legacyfb_depth = 24;
  32. module_param(legacyfb_depth, int, 0444);
  33. static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg)
  34. {
  35. if (reg == DCU_INT_STATUS || reg == DCU_UPDATE_MODE)
  36. return true;
  37. return false;
  38. }
  39. static const struct regmap_config fsl_dcu_regmap_config = {
  40. .reg_bits = 32,
  41. .reg_stride = 4,
  42. .val_bits = 32,
  43. .volatile_reg = fsl_dcu_drm_is_volatile_reg,
  44. };
  45. static void fsl_dcu_irq_uninstall(struct drm_device *dev)
  46. {
  47. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  48. regmap_write(fsl_dev->regmap, DCU_INT_STATUS, ~0);
  49. regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0);
  50. }
  51. static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
  52. {
  53. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  54. int ret;
  55. ret = fsl_dcu_drm_modeset_init(fsl_dev);
  56. if (ret < 0) {
  57. dev_err(dev->dev, "failed to initialize mode setting\n");
  58. return ret;
  59. }
  60. ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
  61. if (ret < 0) {
  62. dev_err(dev->dev, "failed to initialize vblank\n");
  63. goto done;
  64. }
  65. ret = drm_irq_install(dev, fsl_dev->irq);
  66. if (ret < 0) {
  67. dev_err(dev->dev, "failed to install IRQ handler\n");
  68. goto done;
  69. }
  70. if (legacyfb_depth != 16 && legacyfb_depth != 24 &&
  71. legacyfb_depth != 32) {
  72. dev_warn(dev->dev,
  73. "Invalid legacyfb_depth. Defaulting to 24bpp\n");
  74. legacyfb_depth = 24;
  75. }
  76. return 0;
  77. done:
  78. drm_kms_helper_poll_fini(dev);
  79. drm_mode_config_cleanup(dev);
  80. drm_irq_uninstall(dev);
  81. dev->dev_private = NULL;
  82. return ret;
  83. }
  84. static void fsl_dcu_unload(struct drm_device *dev)
  85. {
  86. drm_atomic_helper_shutdown(dev);
  87. drm_kms_helper_poll_fini(dev);
  88. drm_mode_config_cleanup(dev);
  89. drm_irq_uninstall(dev);
  90. dev->dev_private = NULL;
  91. }
  92. static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
  93. {
  94. struct drm_device *dev = arg;
  95. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  96. unsigned int int_status;
  97. int ret;
  98. ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
  99. if (ret) {
  100. dev_err(dev->dev, "read DCU_INT_STATUS failed\n");
  101. return IRQ_NONE;
  102. }
  103. if (int_status & DCU_INT_STATUS_VBLANK)
  104. drm_handle_vblank(dev, 0);
  105. regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status);
  106. return IRQ_HANDLED;
  107. }
  108. DEFINE_DRM_GEM_CMA_FOPS(fsl_dcu_drm_fops);
  109. static struct drm_driver fsl_dcu_drm_driver = {
  110. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
  111. .load = fsl_dcu_load,
  112. .unload = fsl_dcu_unload,
  113. .irq_handler = fsl_dcu_drm_irq,
  114. .irq_preinstall = fsl_dcu_irq_uninstall,
  115. .irq_uninstall = fsl_dcu_irq_uninstall,
  116. DRM_GEM_CMA_DRIVER_OPS,
  117. .fops = &fsl_dcu_drm_fops,
  118. .name = "fsl-dcu-drm",
  119. .desc = "Freescale DCU DRM",
  120. .date = "20160425",
  121. .major = 1,
  122. .minor = 1,
  123. };
  124. #ifdef CONFIG_PM_SLEEP
  125. static int fsl_dcu_drm_pm_suspend(struct device *dev)
  126. {
  127. struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
  128. int ret;
  129. if (!fsl_dev)
  130. return 0;
  131. disable_irq(fsl_dev->irq);
  132. ret = drm_mode_config_helper_suspend(fsl_dev->drm);
  133. if (ret) {
  134. enable_irq(fsl_dev->irq);
  135. return ret;
  136. }
  137. clk_disable_unprepare(fsl_dev->clk);
  138. return 0;
  139. }
  140. static int fsl_dcu_drm_pm_resume(struct device *dev)
  141. {
  142. struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
  143. int ret;
  144. if (!fsl_dev)
  145. return 0;
  146. ret = clk_prepare_enable(fsl_dev->clk);
  147. if (ret < 0) {
  148. dev_err(dev, "failed to enable dcu clk\n");
  149. return ret;
  150. }
  151. if (fsl_dev->tcon)
  152. fsl_tcon_bypass_enable(fsl_dev->tcon);
  153. fsl_dcu_drm_init_planes(fsl_dev->drm);
  154. enable_irq(fsl_dev->irq);
  155. drm_mode_config_helper_resume(fsl_dev->drm);
  156. return 0;
  157. }
  158. #endif
  159. static const struct dev_pm_ops fsl_dcu_drm_pm_ops = {
  160. SET_SYSTEM_SLEEP_PM_OPS(fsl_dcu_drm_pm_suspend, fsl_dcu_drm_pm_resume)
  161. };
  162. static const struct fsl_dcu_soc_data fsl_dcu_ls1021a_data = {
  163. .name = "ls1021a",
  164. .total_layer = 16,
  165. .max_layer = 4,
  166. .layer_regs = LS1021A_LAYER_REG_NUM,
  167. };
  168. static const struct fsl_dcu_soc_data fsl_dcu_vf610_data = {
  169. .name = "vf610",
  170. .total_layer = 64,
  171. .max_layer = 6,
  172. .layer_regs = VF610_LAYER_REG_NUM,
  173. };
  174. static const struct of_device_id fsl_dcu_of_match[] = {
  175. {
  176. .compatible = "fsl,ls1021a-dcu",
  177. .data = &fsl_dcu_ls1021a_data,
  178. }, {
  179. .compatible = "fsl,vf610-dcu",
  180. .data = &fsl_dcu_vf610_data,
  181. }, {
  182. },
  183. };
  184. MODULE_DEVICE_TABLE(of, fsl_dcu_of_match);
  185. static int fsl_dcu_drm_probe(struct platform_device *pdev)
  186. {
  187. struct fsl_dcu_drm_device *fsl_dev;
  188. struct drm_device *drm;
  189. struct device *dev = &pdev->dev;
  190. struct resource *res;
  191. void __iomem *base;
  192. struct drm_driver *driver = &fsl_dcu_drm_driver;
  193. struct clk *pix_clk_in;
  194. char pix_clk_name[32];
  195. const char *pix_clk_in_name;
  196. const struct of_device_id *id;
  197. int ret;
  198. u8 div_ratio_shift = 0;
  199. fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
  200. if (!fsl_dev)
  201. return -ENOMEM;
  202. id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
  203. if (!id)
  204. return -ENODEV;
  205. fsl_dev->soc = id->data;
  206. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  207. base = devm_ioremap_resource(dev, res);
  208. if (IS_ERR(base)) {
  209. ret = PTR_ERR(base);
  210. return ret;
  211. }
  212. fsl_dev->irq = platform_get_irq(pdev, 0);
  213. if (fsl_dev->irq < 0) {
  214. dev_err(dev, "failed to get irq\n");
  215. return fsl_dev->irq;
  216. }
  217. fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
  218. &fsl_dcu_regmap_config);
  219. if (IS_ERR(fsl_dev->regmap)) {
  220. dev_err(dev, "regmap init failed\n");
  221. return PTR_ERR(fsl_dev->regmap);
  222. }
  223. fsl_dev->clk = devm_clk_get(dev, "dcu");
  224. if (IS_ERR(fsl_dev->clk)) {
  225. dev_err(dev, "failed to get dcu clock\n");
  226. return PTR_ERR(fsl_dev->clk);
  227. }
  228. ret = clk_prepare_enable(fsl_dev->clk);
  229. if (ret < 0) {
  230. dev_err(dev, "failed to enable dcu clk\n");
  231. return ret;
  232. }
  233. pix_clk_in = devm_clk_get(dev, "pix");
  234. if (IS_ERR(pix_clk_in)) {
  235. /* legancy binding, use dcu clock as pixel clock input */
  236. pix_clk_in = fsl_dev->clk;
  237. }
  238. if (of_property_read_bool(dev->of_node, "big-endian"))
  239. div_ratio_shift = 24;
  240. pix_clk_in_name = __clk_get_name(pix_clk_in);
  241. snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
  242. fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
  243. pix_clk_in_name, 0, base + DCU_DIV_RATIO,
  244. div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
  245. if (IS_ERR(fsl_dev->pix_clk)) {
  246. dev_err(dev, "failed to register pix clk\n");
  247. ret = PTR_ERR(fsl_dev->pix_clk);
  248. goto disable_clk;
  249. }
  250. fsl_dev->tcon = fsl_tcon_init(dev);
  251. drm = drm_dev_alloc(driver, dev);
  252. if (IS_ERR(drm)) {
  253. ret = PTR_ERR(drm);
  254. goto unregister_pix_clk;
  255. }
  256. fsl_dev->dev = dev;
  257. fsl_dev->drm = drm;
  258. fsl_dev->np = dev->of_node;
  259. drm->dev_private = fsl_dev;
  260. dev_set_drvdata(dev, fsl_dev);
  261. ret = drm_dev_register(drm, 0);
  262. if (ret < 0)
  263. goto put;
  264. drm_fbdev_generic_setup(drm, legacyfb_depth);
  265. return 0;
  266. put:
  267. drm_dev_put(drm);
  268. unregister_pix_clk:
  269. clk_unregister(fsl_dev->pix_clk);
  270. disable_clk:
  271. clk_disable_unprepare(fsl_dev->clk);
  272. return ret;
  273. }
  274. static int fsl_dcu_drm_remove(struct platform_device *pdev)
  275. {
  276. struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
  277. drm_dev_unregister(fsl_dev->drm);
  278. drm_dev_put(fsl_dev->drm);
  279. clk_disable_unprepare(fsl_dev->clk);
  280. clk_unregister(fsl_dev->pix_clk);
  281. return 0;
  282. }
  283. static struct platform_driver fsl_dcu_drm_platform_driver = {
  284. .probe = fsl_dcu_drm_probe,
  285. .remove = fsl_dcu_drm_remove,
  286. .driver = {
  287. .name = "fsl-dcu",
  288. .pm = &fsl_dcu_drm_pm_ops,
  289. .of_match_table = fsl_dcu_of_match,
  290. },
  291. };
  292. module_platform_driver(fsl_dcu_drm_platform_driver);
  293. MODULE_DESCRIPTION("Freescale DCU DRM Driver");
  294. MODULE_LICENSE("GPL");