regs-decon5433.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2014 Samsung Electronics Co.Ltd
  4. */
  5. #ifndef EXYNOS_REGS_DECON5433_H
  6. #define EXYNOS_REGS_DECON5433_H
  7. /* Exynos543X DECON */
  8. #define DECON_VIDCON0 0x0000
  9. #define DECON_VIDOUTCON0 0x0010
  10. #define DECON_WINCONx(n) (0x0020 + ((n) * 4))
  11. #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4))
  12. #define DECON_SHADOWCON 0x00A0
  13. #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20))
  14. #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20))
  15. #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20))
  16. #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20))
  17. #define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20))
  18. #define DECON_VIDW0xADD0B0(n) (0x0150 + ((n) * 0x10))
  19. #define DECON_VIDW0xADD0B1(n) (0x0154 + ((n) * 0x10))
  20. #define DECON_VIDW0xADD0B2(n) (0x0158 + ((n) * 0x10))
  21. #define DECON_VIDW0xADD1B0(n) (0x01A0 + ((n) * 0x10))
  22. #define DECON_VIDW0xADD1B1(n) (0x01A4 + ((n) * 0x10))
  23. #define DECON_VIDW0xADD1B2(n) (0x01A8 + ((n) * 0x10))
  24. #define DECON_VIDW0xADD2(n) (0x0200 + ((n) * 4))
  25. #define DECON_LOCALxSIZE(n) (0x0214 + ((n) * 4))
  26. #define DECON_VIDINTCON0 0x0220
  27. #define DECON_VIDINTCON1 0x0224
  28. #define DECON_WxKEYCON0(n) (0x0230 + ((n - 1) * 8))
  29. #define DECON_WxKEYCON1(n) (0x0234 + ((n - 1) * 8))
  30. #define DECON_WxKEYALPHA(n) (0x0250 + ((n - 1) * 4))
  31. #define DECON_WINxMAP(n) (0x0270 + ((n) * 4))
  32. #define DECON_QOSLUT07_00 0x02C0
  33. #define DECON_QOSLUT15_08 0x02C4
  34. #define DECON_QOSCTRL 0x02C8
  35. #define DECON_BLENDERQx(n) (0x0300 + ((n - 1) * 4))
  36. #define DECON_BLENDCON 0x0310
  37. #define DECON_OPE_VIDW0xADD0(n) (0x0400 + ((n) * 4))
  38. #define DECON_OPE_VIDW0xADD1(n) (0x0414 + ((n) * 4))
  39. #define DECON_FRAMEFIFO_REG7 0x051C
  40. #define DECON_FRAMEFIFO_REG8 0x0520
  41. #define DECON_FRAMEFIFO_STATUS 0x0524
  42. #define DECON_CMU 0x1404
  43. #define DECON_UPDATE 0x1410
  44. #define DECON_CRFMID 0x1414
  45. #define DECON_UPDATE_SCHEME 0x1438
  46. #define DECON_VIDCON1 0x2000
  47. #define DECON_VIDCON2 0x2004
  48. #define DECON_VIDCON3 0x2008
  49. #define DECON_VIDCON4 0x200C
  50. #define DECON_VIDTCON2 0x2028
  51. #define DECON_FRAME_SIZE 0x2038
  52. #define DECON_LINECNT_OP_THRESHOLD 0x203C
  53. #define DECON_TRIGCON 0x2040
  54. #define DECON_TRIGSKIP 0x2050
  55. #define DECON_CRCRDATA 0x20B0
  56. #define DECON_CRCCTRL 0x20B4
  57. /* Exynos5430 DECON */
  58. #define DECON_VIDTCON0 0x2020
  59. #define DECON_VIDTCON1 0x2024
  60. /* Exynos5433 DECON */
  61. #define DECON_VIDTCON00 0x2010
  62. #define DECON_VIDTCON01 0x2014
  63. #define DECON_VIDTCON10 0x2018
  64. #define DECON_VIDTCON11 0x201C
  65. /* Exynos543X DECON Internal */
  66. #define DECON_W013DSTREOCON 0x0320
  67. #define DECON_W233DSTREOCON 0x0324
  68. #define DECON_FRAMEFIFO_REG0 0x0500
  69. #define DECON_ENHANCER_CTRL 0x2100
  70. /* Exynos543X DECON TV */
  71. #define DECON_VCLKCON0 0x0014
  72. #define DECON_VIDINTCON2 0x0228
  73. #define DECON_VIDINTCON3 0x022C
  74. /* VIDCON0 */
  75. #define VIDCON0_SWRESET (1 << 28)
  76. #define VIDCON0_CLKVALUP (1 << 14)
  77. #define VIDCON0_VLCKFREE (1 << 5)
  78. #define VIDCON0_STOP_STATUS (1 << 2)
  79. #define VIDCON0_ENVID (1 << 1)
  80. #define VIDCON0_ENVID_F (1 << 0)
  81. /* VIDOUTCON0 */
  82. #define VIDOUT_INTERLACE_FIELD_F (1 << 29)
  83. #define VIDOUT_INTERLACE_EN_F (1 << 28)
  84. #define VIDOUT_LCD_ON (1 << 24)
  85. #define VIDOUT_IF_F_MASK (0x3 << 20)
  86. #define VIDOUT_RGB_IF (0x0 << 20)
  87. #define VIDOUT_COMMAND_IF (0x2 << 20)
  88. /* WINCONx */
  89. #define WINCONx_HAWSWP_F (1 << 16)
  90. #define WINCONx_WSWP_F (1 << 15)
  91. #define WINCONx_BURSTLEN_MASK (0x3 << 10)
  92. #define WINCONx_BURSTLEN_16WORD (0x0 << 10)
  93. #define WINCONx_BURSTLEN_8WORD (0x1 << 10)
  94. #define WINCONx_BURSTLEN_4WORD (0x2 << 10)
  95. #define WINCONx_ALPHA_MUL_F (1 << 7)
  96. #define WINCONx_BLD_PIX_F (1 << 6)
  97. #define WINCONx_BPPMODE_MASK (0xf << 2)
  98. #define WINCONx_BPPMODE_16BPP_565 (0x5 << 2)
  99. #define WINCONx_BPPMODE_16BPP_A1555 (0x6 << 2)
  100. #define WINCONx_BPPMODE_16BPP_I1555 (0x7 << 2)
  101. #define WINCONx_BPPMODE_24BPP_888 (0xb << 2)
  102. #define WINCONx_BPPMODE_24BPP_A1887 (0xc << 2)
  103. #define WINCONx_BPPMODE_25BPP_A1888 (0xd << 2)
  104. #define WINCONx_BPPMODE_32BPP_A8888 (0xd << 2)
  105. #define WINCONx_BPPMODE_16BPP_A4444 (0xe << 2)
  106. #define WINCONx_ALPHA_SEL_F (1 << 1)
  107. #define WINCONx_ENWIN_F (1 << 0)
  108. #define WINCONx_BLEND_MODE_MASK (0xc2)
  109. /* SHADOWCON */
  110. #define SHADOWCON_PROTECT_MASK GENMASK(14, 10)
  111. #define SHADOWCON_Wx_PROTECT(n) (1 << (10 + (n)))
  112. /* VIDOSDxC */
  113. #define VIDOSDxC_ALPHA0_RGB_MASK (0xffffff)
  114. /* VIDOSDxD */
  115. #define VIDOSD_Wx_ALPHA_R_F(n) (((n) & 0xff) << 16)
  116. #define VIDOSD_Wx_ALPHA_G_F(n) (((n) & 0xff) << 8)
  117. #define VIDOSD_Wx_ALPHA_B_F(n) (((n) & 0xff) << 0)
  118. /* VIDINTCON0 */
  119. #define VIDINTCON0_FRAMEDONE (1 << 17)
  120. #define VIDINTCON0_FRAMESEL_BP (0 << 15)
  121. #define VIDINTCON0_FRAMESEL_VS (1 << 15)
  122. #define VIDINTCON0_FRAMESEL_AC (2 << 15)
  123. #define VIDINTCON0_FRAMESEL_FP (3 << 15)
  124. #define VIDINTCON0_INTFRMEN (1 << 12)
  125. #define VIDINTCON0_INTEN (1 << 0)
  126. /* VIDINTCON1 */
  127. #define VIDINTCON1_INTFRMDONEPEND (1 << 2)
  128. #define VIDINTCON1_INTFRMPEND (1 << 1)
  129. #define VIDINTCON1_INTFIFOPEND (1 << 0)
  130. /* DECON_CMU */
  131. #define CMU_CLKGAGE_MODE_SFR_F (1 << 1)
  132. #define CMU_CLKGAGE_MODE_MEM_F (1 << 0)
  133. /* DECON_UPDATE */
  134. #define STANDALONE_UPDATE_F (1 << 0)
  135. /* DECON_VIDCON1 */
  136. #define VIDCON1_LINECNT_MASK (0x0fff << 16)
  137. #define VIDCON1_I80_ACTIVE (1 << 15)
  138. #define VIDCON1_VSTATUS_MASK (0x3 << 13)
  139. #define VIDCON1_VSTATUS_VS (0 << 13)
  140. #define VIDCON1_VSTATUS_BP (1 << 13)
  141. #define VIDCON1_VSTATUS_AC (2 << 13)
  142. #define VIDCON1_VSTATUS_FP (3 << 13)
  143. #define VIDCON1_VCLK_MASK (0x3 << 9)
  144. #define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 << 9)
  145. #define VIDCON1_VCLK_HOLD (0x0 << 9)
  146. #define VIDCON1_VCLK_RUN (0x1 << 9)
  147. /* DECON_VIDTCON00 */
  148. #define VIDTCON00_VBPD_F(x) (((x) & 0xfff) << 16)
  149. #define VIDTCON00_VFPD_F(x) ((x) & 0xfff)
  150. /* DECON_VIDTCON01 */
  151. #define VIDTCON01_VSPW_F(x) (((x) & 0xfff) << 16)
  152. /* DECON_VIDTCON10 */
  153. #define VIDTCON10_HBPD_F(x) (((x) & 0xfff) << 16)
  154. #define VIDTCON10_HFPD_F(x) ((x) & 0xfff)
  155. /* DECON_VIDTCON11 */
  156. #define VIDTCON11_HSPW_F(x) (((x) & 0xfff) << 16)
  157. /* DECON_VIDTCON2 */
  158. #define VIDTCON2_LINEVAL(x) (((x) & 0xfff) << 16)
  159. #define VIDTCON2_HOZVAL(x) ((x) & 0xfff)
  160. /* TRIGCON */
  161. #define TRIGCON_TRIGEN_PER_F (1 << 31)
  162. #define TRIGCON_TRIGEN_F (1 << 30)
  163. #define TRIGCON_TE_AUTO_MASK (1 << 29)
  164. #define TRIGCON_WB_SWTRIGCMD (1 << 28)
  165. #define TRIGCON_SWTRIGCMD_W4BUF (1 << 26)
  166. #define TRIGCON_TRIGMODE_W4BUF (1 << 25)
  167. #define TRIGCON_SWTRIGCMD_W3BUF (1 << 21)
  168. #define TRIGCON_TRIGMODE_W3BUF (1 << 20)
  169. #define TRIGCON_SWTRIGCMD_W2BUF (1 << 16)
  170. #define TRIGCON_TRIGMODE_W2BUF (1 << 15)
  171. #define TRIGCON_SWTRIGCMD_W1BUF (1 << 11)
  172. #define TRIGCON_TRIGMODE_W1BUF (1 << 10)
  173. #define TRIGCON_SWTRIGCMD_W0BUF (1 << 6)
  174. #define TRIGCON_TRIGMODE_W0BUF (1 << 5)
  175. #define TRIGCON_HWTRIGMASK (1 << 4)
  176. #define TRIGCON_HWTRIGEN (1 << 3)
  177. #define TRIGCON_HWTRIG_INV (1 << 2)
  178. #define TRIGCON_SWTRIGCMD (1 << 1)
  179. #define TRIGCON_SWTRIGEN (1 << 0)
  180. /* DECON_CRCCTRL */
  181. #define CRCCTRL_CRCCLKEN (0x1 << 2)
  182. #define CRCCTRL_CRCSTART_F (0x1 << 1)
  183. #define CRCCTRL_CRCEN (0x1 << 0)
  184. #define CRCCTRL_MASK (0x7)
  185. /* BLENDCON */
  186. #define BLEND_NEW (1 << 0)
  187. /* BLENDERQx */
  188. #define BLENDERQ_ZERO 0x0
  189. #define BLENDERQ_ONE 0x1
  190. #define BLENDERQ_ALPHA_A 0x2
  191. #define BLENDERQ_ONE_MINUS_ALPHA_A 0x3
  192. #define BLENDERQ_ALPHA0 0x6
  193. #define BLENDERQ_Q_FUNC_F(n) (n << 18)
  194. #define BLENDERQ_P_FUNC_F(n) (n << 12)
  195. #define BLENDERQ_B_FUNC_F(n) (n << 6)
  196. #define BLENDERQ_A_FUNC_F(n) (n << 0)
  197. /* BLENDCON */
  198. #define BLEND_NEW (1 << 0)
  199. #endif /* EXYNOS_REGS_DECON5433_H */