exynos_hdmi.c 56 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2011 Samsung Electronics Co.Ltd
  4. * Authors:
  5. * Seung-Woo Kim <sw0312.kim@samsung.com>
  6. * Inki Dae <inki.dae@samsung.com>
  7. * Joonyoung Shim <jy0922.shim@samsung.com>
  8. *
  9. * Based on drivers/media/video/s5p-tv/hdmi_drv.c
  10. */
  11. #include <drm/exynos_drm.h>
  12. #include <linux/clk.h>
  13. #include <linux/component.h>
  14. #include <linux/delay.h>
  15. #include <linux/gpio/consumer.h>
  16. #include <linux/hdmi.h>
  17. #include <linux/i2c.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/irq.h>
  21. #include <linux/kernel.h>
  22. #include <linux/mfd/syscon.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_device.h>
  25. #include <linux/of_graph.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/regmap.h>
  29. #include <linux/regulator/consumer.h>
  30. #include <linux/wait.h>
  31. #include <sound/hdmi-codec.h>
  32. #include <media/cec-notifier.h>
  33. #include <drm/drm_atomic_helper.h>
  34. #include <drm/drm_bridge.h>
  35. #include <drm/drm_edid.h>
  36. #include <drm/drm_print.h>
  37. #include <drm/drm_probe_helper.h>
  38. #include <drm/drm_simple_kms_helper.h>
  39. #include "exynos_drm_crtc.h"
  40. #include "regs-hdmi.h"
  41. #define HOTPLUG_DEBOUNCE_MS 1100
  42. enum hdmi_type {
  43. HDMI_TYPE13,
  44. HDMI_TYPE14,
  45. HDMI_TYPE_COUNT
  46. };
  47. #define HDMI_MAPPED_BASE 0xffff0000
  48. enum hdmi_mapped_regs {
  49. HDMI_PHY_STATUS = HDMI_MAPPED_BASE,
  50. HDMI_PHY_RSTOUT,
  51. HDMI_ACR_CON,
  52. HDMI_ACR_MCTS0,
  53. HDMI_ACR_CTS0,
  54. HDMI_ACR_N0
  55. };
  56. static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = {
  57. { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 },
  58. { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT },
  59. { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON },
  60. { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 },
  61. { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 },
  62. { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 },
  63. };
  64. static const char * const supply[] = {
  65. "vdd",
  66. "vdd_osc",
  67. "vdd_pll",
  68. };
  69. struct hdmiphy_config {
  70. int pixel_clock;
  71. u8 conf[32];
  72. };
  73. struct hdmiphy_configs {
  74. int count;
  75. const struct hdmiphy_config *data;
  76. };
  77. struct string_array_spec {
  78. int count;
  79. const char * const *data;
  80. };
  81. #define INIT_ARRAY_SPEC(a) { .count = ARRAY_SIZE(a), .data = a }
  82. struct hdmi_driver_data {
  83. unsigned int type;
  84. unsigned int is_apb_phy:1;
  85. unsigned int has_sysreg:1;
  86. struct hdmiphy_configs phy_confs;
  87. struct string_array_spec clk_gates;
  88. /*
  89. * Array of triplets (p_off, p_on, clock), where p_off and p_on are
  90. * required parents of clock when HDMI-PHY is respectively off or on.
  91. */
  92. struct string_array_spec clk_muxes;
  93. };
  94. struct hdmi_audio {
  95. struct platform_device *pdev;
  96. struct hdmi_audio_infoframe infoframe;
  97. struct hdmi_codec_params params;
  98. bool mute;
  99. };
  100. struct hdmi_context {
  101. struct drm_encoder encoder;
  102. struct device *dev;
  103. struct drm_device *drm_dev;
  104. struct drm_connector connector;
  105. bool dvi_mode;
  106. struct delayed_work hotplug_work;
  107. struct cec_notifier *notifier;
  108. const struct hdmi_driver_data *drv_data;
  109. void __iomem *regs;
  110. void __iomem *regs_hdmiphy;
  111. struct i2c_client *hdmiphy_port;
  112. struct i2c_adapter *ddc_adpt;
  113. struct gpio_desc *hpd_gpio;
  114. int irq;
  115. struct regmap *pmureg;
  116. struct regmap *sysreg;
  117. struct clk **clk_gates;
  118. struct clk **clk_muxes;
  119. struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)];
  120. struct regulator *reg_hdmi_en;
  121. struct exynos_drm_clk phy_clk;
  122. struct drm_bridge *bridge;
  123. /* mutex protecting subsequent fields below */
  124. struct mutex mutex;
  125. struct hdmi_audio audio;
  126. bool powered;
  127. };
  128. static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
  129. {
  130. return container_of(e, struct hdmi_context, encoder);
  131. }
  132. static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c)
  133. {
  134. return container_of(c, struct hdmi_context, connector);
  135. }
  136. static const struct hdmiphy_config hdmiphy_v13_configs[] = {
  137. {
  138. .pixel_clock = 27000000,
  139. .conf = {
  140. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
  141. 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
  142. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  143. 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
  144. },
  145. },
  146. {
  147. .pixel_clock = 27027000,
  148. .conf = {
  149. 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
  150. 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
  151. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  152. 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
  153. },
  154. },
  155. {
  156. .pixel_clock = 74176000,
  157. .conf = {
  158. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
  159. 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
  160. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  161. 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80,
  162. },
  163. },
  164. {
  165. .pixel_clock = 74250000,
  166. .conf = {
  167. 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
  168. 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
  169. 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
  170. 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80,
  171. },
  172. },
  173. {
  174. .pixel_clock = 148500000,
  175. .conf = {
  176. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
  177. 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
  178. 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
  179. 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80,
  180. },
  181. },
  182. };
  183. static const struct hdmiphy_config hdmiphy_v14_configs[] = {
  184. {
  185. .pixel_clock = 25200000,
  186. .conf = {
  187. 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
  188. 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
  189. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  190. 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  191. },
  192. },
  193. {
  194. .pixel_clock = 27000000,
  195. .conf = {
  196. 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
  197. 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
  198. 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  199. 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  200. },
  201. },
  202. {
  203. .pixel_clock = 27027000,
  204. .conf = {
  205. 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
  206. 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  207. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  208. 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  209. },
  210. },
  211. {
  212. .pixel_clock = 36000000,
  213. .conf = {
  214. 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
  215. 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  216. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  217. 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  218. },
  219. },
  220. {
  221. .pixel_clock = 40000000,
  222. .conf = {
  223. 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
  224. 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  225. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  226. 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  227. },
  228. },
  229. {
  230. .pixel_clock = 65000000,
  231. .conf = {
  232. 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
  233. 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  234. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  235. 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  236. },
  237. },
  238. {
  239. .pixel_clock = 71000000,
  240. .conf = {
  241. 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
  242. 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  243. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  244. 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  245. },
  246. },
  247. {
  248. .pixel_clock = 73250000,
  249. .conf = {
  250. 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
  251. 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  252. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  253. 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  254. },
  255. },
  256. {
  257. .pixel_clock = 74176000,
  258. .conf = {
  259. 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
  260. 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  261. 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  262. 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  263. },
  264. },
  265. {
  266. .pixel_clock = 74250000,
  267. .conf = {
  268. 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
  269. 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
  270. 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  271. 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  272. },
  273. },
  274. {
  275. .pixel_clock = 83500000,
  276. .conf = {
  277. 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
  278. 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
  279. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  280. 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  281. },
  282. },
  283. {
  284. .pixel_clock = 85500000,
  285. .conf = {
  286. 0x01, 0xd1, 0x24, 0x11, 0x40, 0x40, 0xd0, 0x08,
  287. 0x84, 0xa0, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80,
  288. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  289. 0x54, 0x90, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  290. },
  291. },
  292. {
  293. .pixel_clock = 106500000,
  294. .conf = {
  295. 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
  296. 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  297. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  298. 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  299. },
  300. },
  301. {
  302. .pixel_clock = 108000000,
  303. .conf = {
  304. 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
  305. 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  306. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  307. 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
  308. },
  309. },
  310. {
  311. .pixel_clock = 115500000,
  312. .conf = {
  313. 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
  314. 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  315. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  316. 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
  317. },
  318. },
  319. {
  320. .pixel_clock = 119000000,
  321. .conf = {
  322. 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
  323. 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  324. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  325. 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
  326. },
  327. },
  328. {
  329. .pixel_clock = 146250000,
  330. .conf = {
  331. 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
  332. 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  333. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  334. 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
  335. },
  336. },
  337. {
  338. .pixel_clock = 148500000,
  339. .conf = {
  340. 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
  341. 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
  342. 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  343. 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
  344. },
  345. },
  346. };
  347. static const struct hdmiphy_config hdmiphy_5420_configs[] = {
  348. {
  349. .pixel_clock = 25200000,
  350. .conf = {
  351. 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
  352. 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  353. 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
  354. 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  355. },
  356. },
  357. {
  358. .pixel_clock = 27000000,
  359. .conf = {
  360. 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
  361. 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  362. 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  363. 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  364. },
  365. },
  366. {
  367. .pixel_clock = 27027000,
  368. .conf = {
  369. 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
  370. 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  371. 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  372. 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  373. },
  374. },
  375. {
  376. .pixel_clock = 36000000,
  377. .conf = {
  378. 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
  379. 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  380. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  381. 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  382. },
  383. },
  384. {
  385. .pixel_clock = 40000000,
  386. .conf = {
  387. 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
  388. 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  389. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  390. 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  391. },
  392. },
  393. {
  394. .pixel_clock = 65000000,
  395. .conf = {
  396. 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
  397. 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  398. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  399. 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  400. },
  401. },
  402. {
  403. .pixel_clock = 71000000,
  404. .conf = {
  405. 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
  406. 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  407. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  408. 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  409. },
  410. },
  411. {
  412. .pixel_clock = 73250000,
  413. .conf = {
  414. 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
  415. 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  416. 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  417. 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  418. },
  419. },
  420. {
  421. .pixel_clock = 74176000,
  422. .conf = {
  423. 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
  424. 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  425. 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  426. 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  427. },
  428. },
  429. {
  430. .pixel_clock = 74250000,
  431. .conf = {
  432. 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
  433. 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  434. 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
  435. 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  436. },
  437. },
  438. {
  439. .pixel_clock = 83500000,
  440. .conf = {
  441. 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
  442. 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  443. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  444. 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  445. },
  446. },
  447. {
  448. .pixel_clock = 88750000,
  449. .conf = {
  450. 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
  451. 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  452. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  453. 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
  454. },
  455. },
  456. {
  457. .pixel_clock = 106500000,
  458. .conf = {
  459. 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
  460. 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  461. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  462. 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  463. },
  464. },
  465. {
  466. .pixel_clock = 108000000,
  467. .conf = {
  468. 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
  469. 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  470. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  471. 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
  472. },
  473. },
  474. {
  475. .pixel_clock = 115500000,
  476. .conf = {
  477. 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
  478. 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  479. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  480. 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  481. },
  482. },
  483. {
  484. .pixel_clock = 146250000,
  485. .conf = {
  486. 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
  487. 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  488. 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
  489. 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
  490. },
  491. },
  492. {
  493. .pixel_clock = 148500000,
  494. .conf = {
  495. 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
  496. 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  497. 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
  498. 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
  499. },
  500. },
  501. };
  502. static const struct hdmiphy_config hdmiphy_5433_configs[] = {
  503. {
  504. .pixel_clock = 27000000,
  505. .conf = {
  506. 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
  507. 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
  508. 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
  509. 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
  510. },
  511. },
  512. {
  513. .pixel_clock = 27027000,
  514. .conf = {
  515. 0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
  516. 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
  517. 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
  518. 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
  519. },
  520. },
  521. {
  522. .pixel_clock = 40000000,
  523. .conf = {
  524. 0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02,
  525. 0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
  526. 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
  527. 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
  528. },
  529. },
  530. {
  531. .pixel_clock = 50000000,
  532. .conf = {
  533. 0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3,
  534. 0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
  535. 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
  536. 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
  537. },
  538. },
  539. {
  540. .pixel_clock = 65000000,
  541. .conf = {
  542. 0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6,
  543. 0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
  544. 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
  545. 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
  546. },
  547. },
  548. {
  549. .pixel_clock = 74176000,
  550. .conf = {
  551. 0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42,
  552. 0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
  553. 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
  554. 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
  555. },
  556. },
  557. {
  558. .pixel_clock = 74250000,
  559. .conf = {
  560. 0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2,
  561. 0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
  562. 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
  563. 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
  564. },
  565. },
  566. {
  567. .pixel_clock = 108000000,
  568. .conf = {
  569. 0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02,
  570. 0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
  571. 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
  572. 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
  573. },
  574. },
  575. {
  576. .pixel_clock = 148500000,
  577. .conf = {
  578. 0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1,
  579. 0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
  580. 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
  581. 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
  582. },
  583. },
  584. {
  585. .pixel_clock = 297000000,
  586. .conf = {
  587. 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2,
  588. 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
  589. 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
  590. 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
  591. },
  592. },
  593. };
  594. static const char * const hdmi_clk_gates4[] = {
  595. "hdmi", "sclk_hdmi"
  596. };
  597. static const char * const hdmi_clk_muxes4[] = {
  598. "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"
  599. };
  600. static const char * const hdmi_clk_gates5433[] = {
  601. "hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk"
  602. };
  603. static const char * const hdmi_clk_muxes5433[] = {
  604. "oscclk", "tmds_clko", "tmds_clko_user",
  605. "oscclk", "pixel_clko", "pixel_clko_user"
  606. };
  607. static const struct hdmi_driver_data exynos4210_hdmi_driver_data = {
  608. .type = HDMI_TYPE13,
  609. .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v13_configs),
  610. .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4),
  611. .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
  612. };
  613. static const struct hdmi_driver_data exynos4212_hdmi_driver_data = {
  614. .type = HDMI_TYPE14,
  615. .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v14_configs),
  616. .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4),
  617. .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
  618. };
  619. static const struct hdmi_driver_data exynos5420_hdmi_driver_data = {
  620. .type = HDMI_TYPE14,
  621. .is_apb_phy = 1,
  622. .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5420_configs),
  623. .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4),
  624. .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
  625. };
  626. static const struct hdmi_driver_data exynos5433_hdmi_driver_data = {
  627. .type = HDMI_TYPE14,
  628. .is_apb_phy = 1,
  629. .has_sysreg = 1,
  630. .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5433_configs),
  631. .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates5433),
  632. .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes5433),
  633. };
  634. static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id)
  635. {
  636. if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE)
  637. return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type];
  638. return reg_id;
  639. }
  640. static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
  641. {
  642. return readl(hdata->regs + hdmi_map_reg(hdata, reg_id));
  643. }
  644. static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
  645. u32 reg_id, u8 value)
  646. {
  647. writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id));
  648. }
  649. static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id,
  650. int bytes, u32 val)
  651. {
  652. reg_id = hdmi_map_reg(hdata, reg_id);
  653. while (--bytes >= 0) {
  654. writel(val & 0xff, hdata->regs + reg_id);
  655. val >>= 8;
  656. reg_id += 4;
  657. }
  658. }
  659. static inline void hdmi_reg_write_buf(struct hdmi_context *hdata, u32 reg_id,
  660. u8 *buf, int size)
  661. {
  662. for (reg_id = hdmi_map_reg(hdata, reg_id); size; --size, reg_id += 4)
  663. writel(*buf++, hdata->regs + reg_id);
  664. }
  665. static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
  666. u32 reg_id, u32 value, u32 mask)
  667. {
  668. u32 old;
  669. reg_id = hdmi_map_reg(hdata, reg_id);
  670. old = readl(hdata->regs + reg_id);
  671. value = (value & mask) | (old & ~mask);
  672. writel(value, hdata->regs + reg_id);
  673. }
  674. static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
  675. u32 reg_offset, const u8 *buf, u32 len)
  676. {
  677. if ((reg_offset + len) > 32)
  678. return -EINVAL;
  679. if (hdata->hdmiphy_port) {
  680. int ret;
  681. ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
  682. if (ret == len)
  683. return 0;
  684. return ret;
  685. } else {
  686. int i;
  687. for (i = 0; i < len; i++)
  688. writel(buf[i], hdata->regs_hdmiphy +
  689. ((reg_offset + i)<<2));
  690. return 0;
  691. }
  692. }
  693. static int hdmi_clk_enable_gates(struct hdmi_context *hdata)
  694. {
  695. int i, ret;
  696. for (i = 0; i < hdata->drv_data->clk_gates.count; ++i) {
  697. ret = clk_prepare_enable(hdata->clk_gates[i]);
  698. if (!ret)
  699. continue;
  700. dev_err(hdata->dev, "Cannot enable clock '%s', %d\n",
  701. hdata->drv_data->clk_gates.data[i], ret);
  702. while (i--)
  703. clk_disable_unprepare(hdata->clk_gates[i]);
  704. return ret;
  705. }
  706. return 0;
  707. }
  708. static void hdmi_clk_disable_gates(struct hdmi_context *hdata)
  709. {
  710. int i = hdata->drv_data->clk_gates.count;
  711. while (i--)
  712. clk_disable_unprepare(hdata->clk_gates[i]);
  713. }
  714. static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy)
  715. {
  716. struct device *dev = hdata->dev;
  717. int ret = 0;
  718. int i;
  719. for (i = 0; i < hdata->drv_data->clk_muxes.count; i += 3) {
  720. struct clk **c = &hdata->clk_muxes[i];
  721. ret = clk_set_parent(c[2], c[to_phy]);
  722. if (!ret)
  723. continue;
  724. dev_err(dev, "Cannot set clock parent of '%s' to '%s', %d\n",
  725. hdata->drv_data->clk_muxes.data[i + 2],
  726. hdata->drv_data->clk_muxes.data[i + to_phy], ret);
  727. }
  728. return ret;
  729. }
  730. static int hdmi_audio_infoframe_apply(struct hdmi_context *hdata)
  731. {
  732. struct hdmi_audio_infoframe *infoframe = &hdata->audio.infoframe;
  733. u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)];
  734. int len;
  735. len = hdmi_audio_infoframe_pack(infoframe, buf, sizeof(buf));
  736. if (len < 0)
  737. return len;
  738. hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC);
  739. hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, len);
  740. return 0;
  741. }
  742. static void hdmi_reg_infoframes(struct hdmi_context *hdata)
  743. {
  744. struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
  745. union hdmi_infoframe frm;
  746. u8 buf[25];
  747. int ret;
  748. if (hdata->dvi_mode) {
  749. hdmi_reg_writeb(hdata, HDMI_AVI_CON,
  750. HDMI_AVI_CON_DO_NOT_TRANSMIT);
  751. hdmi_reg_writeb(hdata, HDMI_VSI_CON,
  752. HDMI_VSI_CON_DO_NOT_TRANSMIT);
  753. hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
  754. return;
  755. }
  756. ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi,
  757. &hdata->connector, m);
  758. if (!ret)
  759. ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf));
  760. if (ret > 0) {
  761. hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
  762. hdmi_reg_write_buf(hdata, HDMI_AVI_HEADER0, buf, ret);
  763. } else {
  764. DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret);
  765. }
  766. ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi,
  767. &hdata->connector, m);
  768. if (!ret)
  769. ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf,
  770. sizeof(buf));
  771. if (ret > 0) {
  772. hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC);
  773. hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3);
  774. hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3);
  775. }
  776. hdmi_audio_infoframe_apply(hdata);
  777. }
  778. static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
  779. bool force)
  780. {
  781. struct hdmi_context *hdata = connector_to_hdmi(connector);
  782. if (gpiod_get_value(hdata->hpd_gpio))
  783. return connector_status_connected;
  784. cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID);
  785. return connector_status_disconnected;
  786. }
  787. static void hdmi_connector_destroy(struct drm_connector *connector)
  788. {
  789. struct hdmi_context *hdata = connector_to_hdmi(connector);
  790. cec_notifier_conn_unregister(hdata->notifier);
  791. drm_connector_unregister(connector);
  792. drm_connector_cleanup(connector);
  793. }
  794. static const struct drm_connector_funcs hdmi_connector_funcs = {
  795. .fill_modes = drm_helper_probe_single_connector_modes,
  796. .detect = hdmi_detect,
  797. .destroy = hdmi_connector_destroy,
  798. .reset = drm_atomic_helper_connector_reset,
  799. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  800. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  801. };
  802. static int hdmi_get_modes(struct drm_connector *connector)
  803. {
  804. struct hdmi_context *hdata = connector_to_hdmi(connector);
  805. struct edid *edid;
  806. int ret;
  807. if (!hdata->ddc_adpt)
  808. return -ENODEV;
  809. edid = drm_get_edid(connector, hdata->ddc_adpt);
  810. if (!edid)
  811. return -ENODEV;
  812. hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
  813. DRM_DEV_DEBUG_KMS(hdata->dev, "%s : width[%d] x height[%d]\n",
  814. (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
  815. edid->width_cm, edid->height_cm);
  816. drm_connector_update_edid_property(connector, edid);
  817. cec_notifier_set_phys_addr_from_edid(hdata->notifier, edid);
  818. ret = drm_add_edid_modes(connector, edid);
  819. kfree(edid);
  820. return ret;
  821. }
  822. static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
  823. {
  824. const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs;
  825. int i;
  826. for (i = 0; i < confs->count; i++)
  827. if (confs->data[i].pixel_clock == pixel_clock)
  828. return i;
  829. DRM_DEV_DEBUG_KMS(hdata->dev, "Could not find phy config for %d\n",
  830. pixel_clock);
  831. return -EINVAL;
  832. }
  833. static int hdmi_mode_valid(struct drm_connector *connector,
  834. struct drm_display_mode *mode)
  835. {
  836. struct hdmi_context *hdata = connector_to_hdmi(connector);
  837. int ret;
  838. DRM_DEV_DEBUG_KMS(hdata->dev,
  839. "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
  840. mode->hdisplay, mode->vdisplay,
  841. drm_mode_vrefresh(mode),
  842. (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
  843. false, mode->clock * 1000);
  844. ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
  845. if (ret < 0)
  846. return MODE_BAD;
  847. return MODE_OK;
  848. }
  849. static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
  850. .get_modes = hdmi_get_modes,
  851. .mode_valid = hdmi_mode_valid,
  852. };
  853. static int hdmi_create_connector(struct drm_encoder *encoder)
  854. {
  855. struct hdmi_context *hdata = encoder_to_hdmi(encoder);
  856. struct drm_connector *connector = &hdata->connector;
  857. struct cec_connector_info conn_info;
  858. int ret;
  859. connector->interlace_allowed = true;
  860. connector->polled = DRM_CONNECTOR_POLL_HPD;
  861. ret = drm_connector_init_with_ddc(hdata->drm_dev, connector,
  862. &hdmi_connector_funcs,
  863. DRM_MODE_CONNECTOR_HDMIA,
  864. hdata->ddc_adpt);
  865. if (ret) {
  866. DRM_DEV_ERROR(hdata->dev,
  867. "Failed to initialize connector with drm\n");
  868. return ret;
  869. }
  870. drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
  871. drm_connector_attach_encoder(connector, encoder);
  872. if (hdata->bridge) {
  873. ret = drm_bridge_attach(encoder, hdata->bridge, NULL, 0);
  874. if (ret)
  875. DRM_DEV_ERROR(hdata->dev, "Failed to attach bridge\n");
  876. }
  877. cec_fill_conn_info_from_drm(&conn_info, connector);
  878. hdata->notifier = cec_notifier_conn_register(hdata->dev, NULL,
  879. &conn_info);
  880. if (!hdata->notifier) {
  881. ret = -ENOMEM;
  882. DRM_DEV_ERROR(hdata->dev, "Failed to allocate CEC notifier\n");
  883. }
  884. return ret;
  885. }
  886. static bool hdmi_mode_fixup(struct drm_encoder *encoder,
  887. const struct drm_display_mode *mode,
  888. struct drm_display_mode *adjusted_mode)
  889. {
  890. struct drm_device *dev = encoder->dev;
  891. struct drm_connector *connector;
  892. struct drm_display_mode *m;
  893. struct drm_connector_list_iter conn_iter;
  894. int mode_ok;
  895. drm_mode_set_crtcinfo(adjusted_mode, 0);
  896. drm_connector_list_iter_begin(dev, &conn_iter);
  897. drm_for_each_connector_iter(connector, &conn_iter) {
  898. if (connector->encoder == encoder)
  899. break;
  900. }
  901. if (connector)
  902. drm_connector_get(connector);
  903. drm_connector_list_iter_end(&conn_iter);
  904. if (!connector)
  905. return true;
  906. mode_ok = hdmi_mode_valid(connector, adjusted_mode);
  907. if (mode_ok == MODE_OK)
  908. goto cleanup;
  909. /*
  910. * Find the most suitable mode and copy it to adjusted_mode.
  911. */
  912. list_for_each_entry(m, &connector->modes, head) {
  913. mode_ok = hdmi_mode_valid(connector, m);
  914. if (mode_ok == MODE_OK) {
  915. DRM_INFO("desired mode doesn't exist so\n");
  916. DRM_INFO("use the most suitable mode among modes.\n");
  917. DRM_DEV_DEBUG_KMS(dev->dev,
  918. "Adjusted Mode: [%d]x[%d] [%d]Hz\n",
  919. m->hdisplay, m->vdisplay,
  920. drm_mode_vrefresh(m));
  921. drm_mode_copy(adjusted_mode, m);
  922. break;
  923. }
  924. }
  925. cleanup:
  926. drm_connector_put(connector);
  927. return true;
  928. }
  929. static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq)
  930. {
  931. u32 n, cts;
  932. cts = (freq % 9) ? 27000 : 30000;
  933. n = 128 * freq / (27000000 / cts);
  934. hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n);
  935. hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts);
  936. hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts);
  937. hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
  938. }
  939. static void hdmi_audio_config(struct hdmi_context *hdata)
  940. {
  941. u32 bit_ch = 1;
  942. u32 data_num, val;
  943. int i;
  944. switch (hdata->audio.params.sample_width) {
  945. case 20:
  946. data_num = 2;
  947. break;
  948. case 24:
  949. data_num = 3;
  950. break;
  951. default:
  952. data_num = 1;
  953. bit_ch = 0;
  954. break;
  955. }
  956. hdmi_reg_acr(hdata, hdata->audio.params.sample_rate);
  957. hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
  958. | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
  959. | HDMI_I2S_MUX_ENABLE);
  960. hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
  961. | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
  962. hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
  963. hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
  964. hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
  965. val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
  966. hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
  967. /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
  968. hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
  969. | HDMI_I2S_SEL_LRCK(6));
  970. hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(3)
  971. | HDMI_I2S_SEL_SDATA0(4));
  972. hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
  973. | HDMI_I2S_SEL_SDATA2(2));
  974. hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
  975. /* I2S_CON_1 & 2 */
  976. hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
  977. | HDMI_I2S_L_CH_LOW_POL);
  978. hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
  979. | HDMI_I2S_SET_BIT_CH(bit_ch)
  980. | HDMI_I2S_SET_SDATA_BIT(data_num)
  981. | HDMI_I2S_BASIC_FORMAT);
  982. /* Configuration of the audio channel status registers */
  983. for (i = 0; i < HDMI_I2S_CH_ST_MAXNUM; i++)
  984. hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST(i),
  985. hdata->audio.params.iec.status[i]);
  986. hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
  987. }
  988. static void hdmi_audio_control(struct hdmi_context *hdata)
  989. {
  990. bool enable = !hdata->audio.mute;
  991. if (hdata->dvi_mode)
  992. return;
  993. hdmi_reg_writeb(hdata, HDMI_AUI_CON, enable ?
  994. HDMI_AVI_CON_EVERY_VSYNC : HDMI_AUI_CON_NO_TRAN);
  995. hdmi_reg_writemask(hdata, HDMI_CON_0, enable ?
  996. HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
  997. }
  998. static void hdmi_start(struct hdmi_context *hdata, bool start)
  999. {
  1000. struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
  1001. u32 val = start ? HDMI_TG_EN : 0;
  1002. if (m->flags & DRM_MODE_FLAG_INTERLACE)
  1003. val |= HDMI_FIELD_EN;
  1004. hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
  1005. hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
  1006. }
  1007. static void hdmi_conf_init(struct hdmi_context *hdata)
  1008. {
  1009. /* disable HPD interrupts from HDMI IP block, use GPIO instead */
  1010. hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
  1011. HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
  1012. /* choose HDMI mode */
  1013. hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
  1014. HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
  1015. /* apply video pre-amble and guard band in HDMI mode only */
  1016. hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
  1017. /* disable bluescreen */
  1018. hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
  1019. if (hdata->dvi_mode) {
  1020. hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
  1021. HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
  1022. hdmi_reg_writeb(hdata, HDMI_CON_2,
  1023. HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
  1024. }
  1025. if (hdata->drv_data->type == HDMI_TYPE13) {
  1026. /* choose bluescreen (fecal) color */
  1027. hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
  1028. hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
  1029. hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
  1030. /* enable AVI packet every vsync, fixes purple line problem */
  1031. hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
  1032. /* force RGB, look to CEA-861-D, table 7 for more detail */
  1033. hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
  1034. hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
  1035. hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
  1036. hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
  1037. hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
  1038. } else {
  1039. hdmi_reg_infoframes(hdata);
  1040. /* enable AVI packet every vsync, fixes purple line problem */
  1041. hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
  1042. }
  1043. }
  1044. static void hdmiphy_wait_for_pll(struct hdmi_context *hdata)
  1045. {
  1046. int tries;
  1047. for (tries = 0; tries < 10; ++tries) {
  1048. u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS);
  1049. if (val & HDMI_PHY_STATUS_READY) {
  1050. DRM_DEV_DEBUG_KMS(hdata->dev,
  1051. "PLL stabilized after %d tries\n",
  1052. tries);
  1053. return;
  1054. }
  1055. usleep_range(10, 20);
  1056. }
  1057. DRM_DEV_ERROR(hdata->dev, "PLL could not reach steady state\n");
  1058. }
  1059. static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
  1060. {
  1061. struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
  1062. unsigned int val;
  1063. hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
  1064. hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3,
  1065. (m->htotal << 12) | m->vtotal);
  1066. val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
  1067. hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val);
  1068. val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
  1069. hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val);
  1070. val = (m->hsync_start - m->hdisplay - 2);
  1071. val |= ((m->hsync_end - m->hdisplay - 2) << 10);
  1072. val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
  1073. hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val);
  1074. /*
  1075. * Quirk requirement for exynos HDMI IP design,
  1076. * 2 pixels less than the actual calculation for hsync_start
  1077. * and end.
  1078. */
  1079. /* Following values & calculations differ for different type of modes */
  1080. if (m->flags & DRM_MODE_FLAG_INTERLACE) {
  1081. val = ((m->vsync_end - m->vdisplay) / 2);
  1082. val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
  1083. hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
  1084. val = m->vtotal / 2;
  1085. val |= ((m->vtotal - m->vdisplay) / 2) << 11;
  1086. hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
  1087. val = (m->vtotal +
  1088. ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
  1089. val |= m->vtotal << 11;
  1090. hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val);
  1091. val = ((m->vtotal / 2) + 7);
  1092. val |= ((m->vtotal / 2) + 2) << 12;
  1093. hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val);
  1094. val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
  1095. val |= ((m->htotal / 2) +
  1096. (m->hsync_start - m->hdisplay)) << 12;
  1097. hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val);
  1098. hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
  1099. (m->vtotal - m->vdisplay) / 2);
  1100. hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
  1101. hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249);
  1102. } else {
  1103. val = m->vtotal;
  1104. val |= (m->vtotal - m->vdisplay) << 11;
  1105. hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
  1106. hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0);
  1107. val = (m->vsync_end - m->vdisplay);
  1108. val |= ((m->vsync_start - m->vdisplay) << 12);
  1109. hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
  1110. hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001);
  1111. hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001);
  1112. hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
  1113. m->vtotal - m->vdisplay);
  1114. hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
  1115. }
  1116. hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
  1117. hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
  1118. hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
  1119. hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
  1120. }
  1121. static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
  1122. {
  1123. struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
  1124. struct drm_display_mode *am =
  1125. &hdata->encoder.crtc->state->adjusted_mode;
  1126. int hquirk = 0;
  1127. /*
  1128. * In case video mode coming from CRTC differs from requested one HDMI
  1129. * sometimes is able to almost properly perform conversion - only
  1130. * first line is distorted.
  1131. */
  1132. if ((m->vdisplay != am->vdisplay) &&
  1133. (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366))
  1134. hquirk = 258;
  1135. hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
  1136. hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal);
  1137. hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal);
  1138. hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1,
  1139. (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
  1140. hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1,
  1141. (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
  1142. hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1,
  1143. (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
  1144. /*
  1145. * Quirk requirement for exynos 5 HDMI IP design,
  1146. * 2 pixels less than the actual calculation for hsync_start
  1147. * and end.
  1148. */
  1149. /* Following values & calculations differ for different type of modes */
  1150. if (m->flags & DRM_MODE_FLAG_INTERLACE) {
  1151. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
  1152. (m->vsync_end - m->vdisplay) / 2);
  1153. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
  1154. (m->vsync_start - m->vdisplay) / 2);
  1155. hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2);
  1156. hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
  1157. (m->vtotal - m->vdisplay) / 2);
  1158. hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2,
  1159. m->vtotal - m->vdisplay / 2);
  1160. hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal);
  1161. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2,
  1162. (m->vtotal / 2) + 7);
  1163. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2,
  1164. (m->vtotal / 2) + 2);
  1165. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2,
  1166. (m->htotal / 2) + (m->hsync_start - m->hdisplay));
  1167. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2,
  1168. (m->htotal / 2) + (m->hsync_start - m->hdisplay));
  1169. hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
  1170. (m->vtotal - m->vdisplay) / 2);
  1171. hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
  1172. hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2,
  1173. m->vtotal - m->vdisplay / 2);
  1174. hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2,
  1175. (m->vtotal / 2) + 1);
  1176. hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2,
  1177. (m->vtotal / 2) + 1);
  1178. hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2,
  1179. (m->vtotal / 2) + 1);
  1180. hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0);
  1181. hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0);
  1182. } else {
  1183. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
  1184. m->vsync_end - m->vdisplay);
  1185. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
  1186. m->vsync_start - m->vdisplay);
  1187. hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal);
  1188. hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
  1189. m->vtotal - m->vdisplay);
  1190. hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff);
  1191. hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff);
  1192. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff);
  1193. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff);
  1194. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff);
  1195. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff);
  1196. hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
  1197. m->vtotal - m->vdisplay);
  1198. hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
  1199. }
  1200. hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2,
  1201. m->hsync_start - m->hdisplay - 2);
  1202. hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2,
  1203. m->hsync_end - m->hdisplay - 2);
  1204. hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff);
  1205. hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff);
  1206. hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff);
  1207. hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff);
  1208. hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff);
  1209. hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff);
  1210. hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff);
  1211. hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff);
  1212. hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff);
  1213. hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff);
  1214. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff);
  1215. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff);
  1216. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff);
  1217. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff);
  1218. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff);
  1219. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff);
  1220. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff);
  1221. hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff);
  1222. hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
  1223. hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2,
  1224. m->htotal - m->hdisplay - hquirk);
  1225. hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay + hquirk);
  1226. hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
  1227. if (hdata->drv_data == &exynos5433_hdmi_driver_data)
  1228. hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1);
  1229. }
  1230. static void hdmi_mode_apply(struct hdmi_context *hdata)
  1231. {
  1232. if (hdata->drv_data->type == HDMI_TYPE13)
  1233. hdmi_v13_mode_apply(hdata);
  1234. else
  1235. hdmi_v14_mode_apply(hdata);
  1236. hdmi_start(hdata, true);
  1237. }
  1238. static void hdmiphy_conf_reset(struct hdmi_context *hdata)
  1239. {
  1240. hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, 1);
  1241. usleep_range(10000, 12000);
  1242. hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, 1);
  1243. usleep_range(10000, 12000);
  1244. hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
  1245. usleep_range(10000, 12000);
  1246. hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
  1247. usleep_range(10000, 12000);
  1248. }
  1249. static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable)
  1250. {
  1251. u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET;
  1252. if (hdata->drv_data == &exynos5433_hdmi_driver_data)
  1253. writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE);
  1254. }
  1255. static void hdmiphy_conf_apply(struct hdmi_context *hdata)
  1256. {
  1257. struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
  1258. int ret;
  1259. const u8 *phy_conf;
  1260. ret = hdmi_find_phy_conf(hdata, m->clock * 1000);
  1261. if (ret < 0) {
  1262. DRM_DEV_ERROR(hdata->dev, "failed to find hdmiphy conf\n");
  1263. return;
  1264. }
  1265. phy_conf = hdata->drv_data->phy_confs.data[ret].conf;
  1266. hdmi_clk_set_parents(hdata, false);
  1267. hdmiphy_conf_reset(hdata);
  1268. hdmiphy_enable_mode_set(hdata, true);
  1269. ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32);
  1270. if (ret) {
  1271. DRM_DEV_ERROR(hdata->dev, "failed to configure hdmiphy\n");
  1272. return;
  1273. }
  1274. hdmiphy_enable_mode_set(hdata, false);
  1275. hdmi_clk_set_parents(hdata, true);
  1276. usleep_range(10000, 12000);
  1277. hdmiphy_wait_for_pll(hdata);
  1278. }
  1279. /* Should be called with hdata->mutex mutex held */
  1280. static void hdmi_conf_apply(struct hdmi_context *hdata)
  1281. {
  1282. hdmi_start(hdata, false);
  1283. hdmi_conf_init(hdata);
  1284. hdmi_audio_config(hdata);
  1285. hdmi_mode_apply(hdata);
  1286. hdmi_audio_control(hdata);
  1287. }
  1288. static void hdmi_set_refclk(struct hdmi_context *hdata, bool on)
  1289. {
  1290. if (!hdata->sysreg)
  1291. return;
  1292. regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY,
  1293. SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
  1294. }
  1295. /* Should be called with hdata->mutex mutex held. */
  1296. static void hdmiphy_enable(struct hdmi_context *hdata)
  1297. {
  1298. if (hdata->powered)
  1299. return;
  1300. pm_runtime_get_sync(hdata->dev);
  1301. if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk))
  1302. DRM_DEV_DEBUG_KMS(hdata->dev,
  1303. "failed to enable regulator bulk\n");
  1304. regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
  1305. PMU_HDMI_PHY_ENABLE_BIT, 1);
  1306. hdmi_set_refclk(hdata, true);
  1307. hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN);
  1308. hdmiphy_conf_apply(hdata);
  1309. hdata->powered = true;
  1310. }
  1311. /* Should be called with hdata->mutex mutex held. */
  1312. static void hdmiphy_disable(struct hdmi_context *hdata)
  1313. {
  1314. if (!hdata->powered)
  1315. return;
  1316. hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
  1317. hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN);
  1318. hdmi_set_refclk(hdata, false);
  1319. regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
  1320. PMU_HDMI_PHY_ENABLE_BIT, 0);
  1321. regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk);
  1322. pm_runtime_put_sync(hdata->dev);
  1323. hdata->powered = false;
  1324. }
  1325. static void hdmi_enable(struct drm_encoder *encoder)
  1326. {
  1327. struct hdmi_context *hdata = encoder_to_hdmi(encoder);
  1328. mutex_lock(&hdata->mutex);
  1329. hdmiphy_enable(hdata);
  1330. hdmi_conf_apply(hdata);
  1331. mutex_unlock(&hdata->mutex);
  1332. }
  1333. static void hdmi_disable(struct drm_encoder *encoder)
  1334. {
  1335. struct hdmi_context *hdata = encoder_to_hdmi(encoder);
  1336. mutex_lock(&hdata->mutex);
  1337. if (hdata->powered) {
  1338. /*
  1339. * The SFRs of VP and Mixer are updated by Vertical Sync of
  1340. * Timing generator which is a part of HDMI so the sequence
  1341. * to disable TV Subsystem should be as following,
  1342. * VP -> Mixer -> HDMI
  1343. *
  1344. * To achieve such sequence HDMI is disabled together with
  1345. * HDMI PHY, via pipe clock callback.
  1346. */
  1347. mutex_unlock(&hdata->mutex);
  1348. cancel_delayed_work(&hdata->hotplug_work);
  1349. if (hdata->notifier)
  1350. cec_notifier_phys_addr_invalidate(hdata->notifier);
  1351. return;
  1352. }
  1353. mutex_unlock(&hdata->mutex);
  1354. }
  1355. static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = {
  1356. .mode_fixup = hdmi_mode_fixup,
  1357. .enable = hdmi_enable,
  1358. .disable = hdmi_disable,
  1359. };
  1360. static void hdmi_audio_shutdown(struct device *dev, void *data)
  1361. {
  1362. struct hdmi_context *hdata = dev_get_drvdata(dev);
  1363. mutex_lock(&hdata->mutex);
  1364. hdata->audio.mute = true;
  1365. if (hdata->powered)
  1366. hdmi_audio_control(hdata);
  1367. mutex_unlock(&hdata->mutex);
  1368. }
  1369. static int hdmi_audio_hw_params(struct device *dev, void *data,
  1370. struct hdmi_codec_daifmt *daifmt,
  1371. struct hdmi_codec_params *params)
  1372. {
  1373. struct hdmi_context *hdata = dev_get_drvdata(dev);
  1374. if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv ||
  1375. daifmt->frame_clk_inv || daifmt->bit_clk_master ||
  1376. daifmt->frame_clk_master) {
  1377. dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
  1378. daifmt->bit_clk_inv, daifmt->frame_clk_inv,
  1379. daifmt->bit_clk_master,
  1380. daifmt->frame_clk_master);
  1381. return -EINVAL;
  1382. }
  1383. mutex_lock(&hdata->mutex);
  1384. hdata->audio.params = *params;
  1385. if (hdata->powered) {
  1386. hdmi_audio_config(hdata);
  1387. hdmi_audio_infoframe_apply(hdata);
  1388. }
  1389. mutex_unlock(&hdata->mutex);
  1390. return 0;
  1391. }
  1392. static int hdmi_audio_mute(struct device *dev, void *data,
  1393. bool mute, int direction)
  1394. {
  1395. struct hdmi_context *hdata = dev_get_drvdata(dev);
  1396. mutex_lock(&hdata->mutex);
  1397. hdata->audio.mute = mute;
  1398. if (hdata->powered)
  1399. hdmi_audio_control(hdata);
  1400. mutex_unlock(&hdata->mutex);
  1401. return 0;
  1402. }
  1403. static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
  1404. size_t len)
  1405. {
  1406. struct hdmi_context *hdata = dev_get_drvdata(dev);
  1407. struct drm_connector *connector = &hdata->connector;
  1408. memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
  1409. return 0;
  1410. }
  1411. static const struct hdmi_codec_ops audio_codec_ops = {
  1412. .hw_params = hdmi_audio_hw_params,
  1413. .audio_shutdown = hdmi_audio_shutdown,
  1414. .mute_stream = hdmi_audio_mute,
  1415. .get_eld = hdmi_audio_get_eld,
  1416. .no_capture_mute = 1,
  1417. };
  1418. static int hdmi_register_audio_device(struct hdmi_context *hdata)
  1419. {
  1420. struct hdmi_codec_pdata codec_data = {
  1421. .ops = &audio_codec_ops,
  1422. .max_i2s_channels = 6,
  1423. .i2s = 1,
  1424. };
  1425. hdata->audio.pdev = platform_device_register_data(
  1426. hdata->dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
  1427. &codec_data, sizeof(codec_data));
  1428. return PTR_ERR_OR_ZERO(hdata->audio.pdev);
  1429. }
  1430. static void hdmi_hotplug_work_func(struct work_struct *work)
  1431. {
  1432. struct hdmi_context *hdata;
  1433. hdata = container_of(work, struct hdmi_context, hotplug_work.work);
  1434. if (hdata->drm_dev)
  1435. drm_helper_hpd_irq_event(hdata->drm_dev);
  1436. }
  1437. static irqreturn_t hdmi_irq_thread(int irq, void *arg)
  1438. {
  1439. struct hdmi_context *hdata = arg;
  1440. mod_delayed_work(system_wq, &hdata->hotplug_work,
  1441. msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
  1442. return IRQ_HANDLED;
  1443. }
  1444. static int hdmi_clks_get(struct hdmi_context *hdata,
  1445. const struct string_array_spec *names,
  1446. struct clk **clks)
  1447. {
  1448. struct device *dev = hdata->dev;
  1449. int i;
  1450. for (i = 0; i < names->count; ++i) {
  1451. struct clk *clk = devm_clk_get(dev, names->data[i]);
  1452. if (IS_ERR(clk)) {
  1453. int ret = PTR_ERR(clk);
  1454. dev_err(dev, "Cannot get clock %s, %d\n",
  1455. names->data[i], ret);
  1456. return ret;
  1457. }
  1458. clks[i] = clk;
  1459. }
  1460. return 0;
  1461. }
  1462. static int hdmi_clk_init(struct hdmi_context *hdata)
  1463. {
  1464. const struct hdmi_driver_data *drv_data = hdata->drv_data;
  1465. int count = drv_data->clk_gates.count + drv_data->clk_muxes.count;
  1466. struct device *dev = hdata->dev;
  1467. struct clk **clks;
  1468. int ret;
  1469. if (!count)
  1470. return 0;
  1471. clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL);
  1472. if (!clks)
  1473. return -ENOMEM;
  1474. hdata->clk_gates = clks;
  1475. hdata->clk_muxes = clks + drv_data->clk_gates.count;
  1476. ret = hdmi_clks_get(hdata, &drv_data->clk_gates, hdata->clk_gates);
  1477. if (ret)
  1478. return ret;
  1479. return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes);
  1480. }
  1481. static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable)
  1482. {
  1483. struct hdmi_context *hdata = container_of(clk, struct hdmi_context,
  1484. phy_clk);
  1485. mutex_lock(&hdata->mutex);
  1486. if (enable)
  1487. hdmiphy_enable(hdata);
  1488. else
  1489. hdmiphy_disable(hdata);
  1490. mutex_unlock(&hdata->mutex);
  1491. }
  1492. static int hdmi_bridge_init(struct hdmi_context *hdata)
  1493. {
  1494. struct device *dev = hdata->dev;
  1495. struct device_node *ep, *np;
  1496. ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
  1497. if (!ep)
  1498. return 0;
  1499. np = of_graph_get_remote_port_parent(ep);
  1500. of_node_put(ep);
  1501. if (!np) {
  1502. DRM_DEV_ERROR(dev, "failed to get remote port parent");
  1503. return -EINVAL;
  1504. }
  1505. hdata->bridge = of_drm_find_bridge(np);
  1506. of_node_put(np);
  1507. if (!hdata->bridge)
  1508. return -EPROBE_DEFER;
  1509. return 0;
  1510. }
  1511. static int hdmi_resources_init(struct hdmi_context *hdata)
  1512. {
  1513. struct device *dev = hdata->dev;
  1514. int i, ret;
  1515. DRM_DEV_DEBUG_KMS(dev, "HDMI resource init\n");
  1516. hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN);
  1517. if (IS_ERR(hdata->hpd_gpio)) {
  1518. DRM_DEV_ERROR(dev, "cannot get hpd gpio property\n");
  1519. return PTR_ERR(hdata->hpd_gpio);
  1520. }
  1521. hdata->irq = gpiod_to_irq(hdata->hpd_gpio);
  1522. if (hdata->irq < 0) {
  1523. DRM_DEV_ERROR(dev, "failed to get GPIO irq\n");
  1524. return hdata->irq;
  1525. }
  1526. ret = hdmi_clk_init(hdata);
  1527. if (ret)
  1528. return ret;
  1529. ret = hdmi_clk_set_parents(hdata, false);
  1530. if (ret)
  1531. return ret;
  1532. for (i = 0; i < ARRAY_SIZE(supply); ++i)
  1533. hdata->regul_bulk[i].supply = supply[i];
  1534. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk);
  1535. if (ret)
  1536. return dev_err_probe(dev, ret, "failed to get regulators\n");
  1537. hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
  1538. if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV)
  1539. if (IS_ERR(hdata->reg_hdmi_en))
  1540. return PTR_ERR(hdata->reg_hdmi_en);
  1541. return hdmi_bridge_init(hdata);
  1542. }
  1543. static const struct of_device_id hdmi_match_types[] = {
  1544. {
  1545. .compatible = "samsung,exynos4210-hdmi",
  1546. .data = &exynos4210_hdmi_driver_data,
  1547. }, {
  1548. .compatible = "samsung,exynos4212-hdmi",
  1549. .data = &exynos4212_hdmi_driver_data,
  1550. }, {
  1551. .compatible = "samsung,exynos5420-hdmi",
  1552. .data = &exynos5420_hdmi_driver_data,
  1553. }, {
  1554. .compatible = "samsung,exynos5433-hdmi",
  1555. .data = &exynos5433_hdmi_driver_data,
  1556. }, {
  1557. /* end node */
  1558. }
  1559. };
  1560. MODULE_DEVICE_TABLE (of, hdmi_match_types);
  1561. static int hdmi_bind(struct device *dev, struct device *master, void *data)
  1562. {
  1563. struct drm_device *drm_dev = data;
  1564. struct hdmi_context *hdata = dev_get_drvdata(dev);
  1565. struct drm_encoder *encoder = &hdata->encoder;
  1566. struct exynos_drm_crtc *crtc;
  1567. int ret;
  1568. hdata->drm_dev = drm_dev;
  1569. hdata->phy_clk.enable = hdmiphy_clk_enable;
  1570. drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS);
  1571. drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs);
  1572. ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_HDMI);
  1573. if (ret < 0)
  1574. return ret;
  1575. crtc = exynos_drm_crtc_get_by_type(drm_dev, EXYNOS_DISPLAY_TYPE_HDMI);
  1576. crtc->pipe_clk = &hdata->phy_clk;
  1577. ret = hdmi_create_connector(encoder);
  1578. if (ret) {
  1579. DRM_DEV_ERROR(dev, "failed to create connector ret = %d\n",
  1580. ret);
  1581. drm_encoder_cleanup(encoder);
  1582. return ret;
  1583. }
  1584. return 0;
  1585. }
  1586. static void hdmi_unbind(struct device *dev, struct device *master, void *data)
  1587. {
  1588. }
  1589. static const struct component_ops hdmi_component_ops = {
  1590. .bind = hdmi_bind,
  1591. .unbind = hdmi_unbind,
  1592. };
  1593. static int hdmi_get_ddc_adapter(struct hdmi_context *hdata)
  1594. {
  1595. const char *compatible_str = "samsung,exynos4210-hdmiddc";
  1596. struct device_node *np;
  1597. struct i2c_adapter *adpt;
  1598. np = of_find_compatible_node(NULL, NULL, compatible_str);
  1599. if (np)
  1600. np = of_get_next_parent(np);
  1601. else
  1602. np = of_parse_phandle(hdata->dev->of_node, "ddc", 0);
  1603. if (!np) {
  1604. DRM_DEV_ERROR(hdata->dev,
  1605. "Failed to find ddc node in device tree\n");
  1606. return -ENODEV;
  1607. }
  1608. adpt = of_find_i2c_adapter_by_node(np);
  1609. of_node_put(np);
  1610. if (!adpt) {
  1611. DRM_INFO("Failed to get ddc i2c adapter by node\n");
  1612. return -EPROBE_DEFER;
  1613. }
  1614. hdata->ddc_adpt = adpt;
  1615. return 0;
  1616. }
  1617. static int hdmi_get_phy_io(struct hdmi_context *hdata)
  1618. {
  1619. const char *compatible_str = "samsung,exynos4212-hdmiphy";
  1620. struct device_node *np;
  1621. int ret = 0;
  1622. np = of_find_compatible_node(NULL, NULL, compatible_str);
  1623. if (!np) {
  1624. np = of_parse_phandle(hdata->dev->of_node, "phy", 0);
  1625. if (!np) {
  1626. DRM_DEV_ERROR(hdata->dev,
  1627. "Failed to find hdmiphy node in device tree\n");
  1628. return -ENODEV;
  1629. }
  1630. }
  1631. if (hdata->drv_data->is_apb_phy) {
  1632. hdata->regs_hdmiphy = of_iomap(np, 0);
  1633. if (!hdata->regs_hdmiphy) {
  1634. DRM_DEV_ERROR(hdata->dev,
  1635. "failed to ioremap hdmi phy\n");
  1636. ret = -ENOMEM;
  1637. goto out;
  1638. }
  1639. } else {
  1640. hdata->hdmiphy_port = of_find_i2c_device_by_node(np);
  1641. if (!hdata->hdmiphy_port) {
  1642. DRM_INFO("Failed to get hdmi phy i2c client\n");
  1643. ret = -EPROBE_DEFER;
  1644. goto out;
  1645. }
  1646. }
  1647. out:
  1648. of_node_put(np);
  1649. return ret;
  1650. }
  1651. static int hdmi_probe(struct platform_device *pdev)
  1652. {
  1653. struct hdmi_audio_infoframe *audio_infoframe;
  1654. struct device *dev = &pdev->dev;
  1655. struct hdmi_context *hdata;
  1656. struct resource *res;
  1657. int ret;
  1658. hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
  1659. if (!hdata)
  1660. return -ENOMEM;
  1661. hdata->drv_data = of_device_get_match_data(dev);
  1662. platform_set_drvdata(pdev, hdata);
  1663. hdata->dev = dev;
  1664. mutex_init(&hdata->mutex);
  1665. ret = hdmi_resources_init(hdata);
  1666. if (ret) {
  1667. if (ret != -EPROBE_DEFER)
  1668. DRM_DEV_ERROR(dev, "hdmi_resources_init failed\n");
  1669. return ret;
  1670. }
  1671. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1672. hdata->regs = devm_ioremap_resource(dev, res);
  1673. if (IS_ERR(hdata->regs)) {
  1674. ret = PTR_ERR(hdata->regs);
  1675. return ret;
  1676. }
  1677. ret = hdmi_get_ddc_adapter(hdata);
  1678. if (ret)
  1679. return ret;
  1680. ret = hdmi_get_phy_io(hdata);
  1681. if (ret)
  1682. goto err_ddc;
  1683. INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
  1684. ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
  1685. hdmi_irq_thread, IRQF_TRIGGER_RISING |
  1686. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  1687. "hdmi", hdata);
  1688. if (ret) {
  1689. DRM_DEV_ERROR(dev, "failed to register hdmi interrupt\n");
  1690. goto err_hdmiphy;
  1691. }
  1692. hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
  1693. "samsung,syscon-phandle");
  1694. if (IS_ERR(hdata->pmureg)) {
  1695. DRM_DEV_ERROR(dev, "syscon regmap lookup failed.\n");
  1696. ret = -EPROBE_DEFER;
  1697. goto err_hdmiphy;
  1698. }
  1699. if (hdata->drv_data->has_sysreg) {
  1700. hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
  1701. "samsung,sysreg-phandle");
  1702. if (IS_ERR(hdata->sysreg)) {
  1703. DRM_DEV_ERROR(dev, "sysreg regmap lookup failed.\n");
  1704. ret = -EPROBE_DEFER;
  1705. goto err_hdmiphy;
  1706. }
  1707. }
  1708. if (!IS_ERR(hdata->reg_hdmi_en)) {
  1709. ret = regulator_enable(hdata->reg_hdmi_en);
  1710. if (ret) {
  1711. DRM_DEV_ERROR(dev,
  1712. "failed to enable hdmi-en regulator\n");
  1713. goto err_hdmiphy;
  1714. }
  1715. }
  1716. pm_runtime_enable(dev);
  1717. audio_infoframe = &hdata->audio.infoframe;
  1718. hdmi_audio_infoframe_init(audio_infoframe);
  1719. audio_infoframe->coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
  1720. audio_infoframe->sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
  1721. audio_infoframe->sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
  1722. audio_infoframe->channels = 2;
  1723. ret = hdmi_register_audio_device(hdata);
  1724. if (ret)
  1725. goto err_rpm_disable;
  1726. ret = component_add(&pdev->dev, &hdmi_component_ops);
  1727. if (ret)
  1728. goto err_unregister_audio;
  1729. return ret;
  1730. err_unregister_audio:
  1731. platform_device_unregister(hdata->audio.pdev);
  1732. err_rpm_disable:
  1733. pm_runtime_disable(dev);
  1734. if (!IS_ERR(hdata->reg_hdmi_en))
  1735. regulator_disable(hdata->reg_hdmi_en);
  1736. err_hdmiphy:
  1737. if (hdata->hdmiphy_port)
  1738. put_device(&hdata->hdmiphy_port->dev);
  1739. if (hdata->regs_hdmiphy)
  1740. iounmap(hdata->regs_hdmiphy);
  1741. err_ddc:
  1742. put_device(&hdata->ddc_adpt->dev);
  1743. return ret;
  1744. }
  1745. static int hdmi_remove(struct platform_device *pdev)
  1746. {
  1747. struct hdmi_context *hdata = platform_get_drvdata(pdev);
  1748. cancel_delayed_work_sync(&hdata->hotplug_work);
  1749. component_del(&pdev->dev, &hdmi_component_ops);
  1750. platform_device_unregister(hdata->audio.pdev);
  1751. pm_runtime_disable(&pdev->dev);
  1752. if (!IS_ERR(hdata->reg_hdmi_en))
  1753. regulator_disable(hdata->reg_hdmi_en);
  1754. if (hdata->hdmiphy_port)
  1755. put_device(&hdata->hdmiphy_port->dev);
  1756. if (hdata->regs_hdmiphy)
  1757. iounmap(hdata->regs_hdmiphy);
  1758. put_device(&hdata->ddc_adpt->dev);
  1759. mutex_destroy(&hdata->mutex);
  1760. return 0;
  1761. }
  1762. static int __maybe_unused exynos_hdmi_suspend(struct device *dev)
  1763. {
  1764. struct hdmi_context *hdata = dev_get_drvdata(dev);
  1765. hdmi_clk_disable_gates(hdata);
  1766. return 0;
  1767. }
  1768. static int __maybe_unused exynos_hdmi_resume(struct device *dev)
  1769. {
  1770. struct hdmi_context *hdata = dev_get_drvdata(dev);
  1771. int ret;
  1772. ret = hdmi_clk_enable_gates(hdata);
  1773. if (ret < 0)
  1774. return ret;
  1775. return 0;
  1776. }
  1777. static const struct dev_pm_ops exynos_hdmi_pm_ops = {
  1778. SET_RUNTIME_PM_OPS(exynos_hdmi_suspend, exynos_hdmi_resume, NULL)
  1779. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1780. pm_runtime_force_resume)
  1781. };
  1782. struct platform_driver hdmi_driver = {
  1783. .probe = hdmi_probe,
  1784. .remove = hdmi_remove,
  1785. .driver = {
  1786. .name = "exynos-hdmi",
  1787. .owner = THIS_MODULE,
  1788. .pm = &exynos_hdmi_pm_ops,
  1789. .of_match_table = hdmi_match_types,
  1790. },
  1791. };