exynos_drm_mic.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Samsung Electronics Co.Ltd
  4. * Authors:
  5. * Hyungwon Hwang <human.hwang@samsung.com>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/component.h>
  9. #include <linux/delay.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/module.h>
  12. #include <linux/mutex.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_graph.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/regmap.h>
  19. #include <video/of_videomode.h>
  20. #include <video/videomode.h>
  21. #include <drm/drm_bridge.h>
  22. #include <drm/drm_encoder.h>
  23. #include <drm/drm_print.h>
  24. #include "exynos_drm_drv.h"
  25. /* Sysreg registers for MIC */
  26. #define DSD_CFG_MUX 0x1004
  27. #define MIC0_RGB_MUX (1 << 0)
  28. #define MIC0_I80_MUX (1 << 1)
  29. #define MIC0_ON_MUX (1 << 5)
  30. /* MIC registers */
  31. #define MIC_OP 0x0
  32. #define MIC_IP_VER 0x0004
  33. #define MIC_V_TIMING_0 0x0008
  34. #define MIC_V_TIMING_1 0x000C
  35. #define MIC_IMG_SIZE 0x0010
  36. #define MIC_INPUT_TIMING_0 0x0014
  37. #define MIC_INPUT_TIMING_1 0x0018
  38. #define MIC_2D_OUTPUT_TIMING_0 0x001C
  39. #define MIC_2D_OUTPUT_TIMING_1 0x0020
  40. #define MIC_2D_OUTPUT_TIMING_2 0x0024
  41. #define MIC_3D_OUTPUT_TIMING_0 0x0028
  42. #define MIC_3D_OUTPUT_TIMING_1 0x002C
  43. #define MIC_3D_OUTPUT_TIMING_2 0x0030
  44. #define MIC_CORE_PARA_0 0x0034
  45. #define MIC_CORE_PARA_1 0x0038
  46. #define MIC_CTC_CTRL 0x0040
  47. #define MIC_RD_DATA 0x0044
  48. #define MIC_UPD_REG (1 << 31)
  49. #define MIC_ON_REG (1 << 30)
  50. #define MIC_TD_ON_REG (1 << 29)
  51. #define MIC_BS_CHG_OUT (1 << 16)
  52. #define MIC_VIDEO_TYPE(x) (((x) & 0xf) << 12)
  53. #define MIC_PSR_EN (1 << 5)
  54. #define MIC_SW_RST (1 << 4)
  55. #define MIC_ALL_RST (1 << 3)
  56. #define MIC_CORE_VER_CONTROL (1 << 2)
  57. #define MIC_MODE_SEL_COMMAND_MODE (1 << 1)
  58. #define MIC_MODE_SEL_MASK (1 << 1)
  59. #define MIC_CORE_EN (1 << 0)
  60. #define MIC_V_PULSE_WIDTH(x) (((x) & 0x3fff) << 16)
  61. #define MIC_V_PERIOD_LINE(x) ((x) & 0x3fff)
  62. #define MIC_VBP_SIZE(x) (((x) & 0x3fff) << 16)
  63. #define MIC_VFP_SIZE(x) ((x) & 0x3fff)
  64. #define MIC_IMG_V_SIZE(x) (((x) & 0x3fff) << 16)
  65. #define MIC_IMG_H_SIZE(x) ((x) & 0x3fff)
  66. #define MIC_H_PULSE_WIDTH_IN(x) (((x) & 0x3fff) << 16)
  67. #define MIC_H_PERIOD_PIXEL_IN(x) ((x) & 0x3fff)
  68. #define MIC_HBP_SIZE_IN(x) (((x) & 0x3fff) << 16)
  69. #define MIC_HFP_SIZE_IN(x) ((x) & 0x3fff)
  70. #define MIC_H_PULSE_WIDTH_2D(x) (((x) & 0x3fff) << 16)
  71. #define MIC_H_PERIOD_PIXEL_2D(x) ((x) & 0x3fff)
  72. #define MIC_HBP_SIZE_2D(x) (((x) & 0x3fff) << 16)
  73. #define MIC_HFP_SIZE_2D(x) ((x) & 0x3fff)
  74. #define MIC_BS_SIZE_2D(x) ((x) & 0x3fff)
  75. static const char *const clk_names[] = { "pclk_mic0", "sclk_rgb_vclk_to_mic0" };
  76. #define NUM_CLKS ARRAY_SIZE(clk_names)
  77. static DEFINE_MUTEX(mic_mutex);
  78. struct exynos_mic {
  79. struct device *dev;
  80. void __iomem *reg;
  81. struct regmap *sysreg;
  82. struct clk *clks[NUM_CLKS];
  83. bool i80_mode;
  84. struct videomode vm;
  85. struct drm_encoder *encoder;
  86. struct drm_bridge bridge;
  87. bool enabled;
  88. };
  89. static void mic_set_path(struct exynos_mic *mic, bool enable)
  90. {
  91. int ret;
  92. unsigned int val;
  93. ret = regmap_read(mic->sysreg, DSD_CFG_MUX, &val);
  94. if (ret) {
  95. DRM_DEV_ERROR(mic->dev,
  96. "mic: Failed to read system register\n");
  97. return;
  98. }
  99. if (enable) {
  100. if (mic->i80_mode)
  101. val |= MIC0_I80_MUX;
  102. else
  103. val |= MIC0_RGB_MUX;
  104. val |= MIC0_ON_MUX;
  105. } else
  106. val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX);
  107. ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val);
  108. if (ret)
  109. DRM_DEV_ERROR(mic->dev,
  110. "mic: Failed to read system register\n");
  111. }
  112. static int mic_sw_reset(struct exynos_mic *mic)
  113. {
  114. unsigned int retry = 100;
  115. int ret;
  116. writel(MIC_SW_RST, mic->reg + MIC_OP);
  117. while (retry-- > 0) {
  118. ret = readl(mic->reg + MIC_OP);
  119. if (!(ret & MIC_SW_RST))
  120. return 0;
  121. udelay(10);
  122. }
  123. return -ETIMEDOUT;
  124. }
  125. static void mic_set_porch_timing(struct exynos_mic *mic)
  126. {
  127. struct videomode vm = mic->vm;
  128. u32 reg;
  129. reg = MIC_V_PULSE_WIDTH(vm.vsync_len) +
  130. MIC_V_PERIOD_LINE(vm.vsync_len + vm.vactive +
  131. vm.vback_porch + vm.vfront_porch);
  132. writel(reg, mic->reg + MIC_V_TIMING_0);
  133. reg = MIC_VBP_SIZE(vm.vback_porch) +
  134. MIC_VFP_SIZE(vm.vfront_porch);
  135. writel(reg, mic->reg + MIC_V_TIMING_1);
  136. reg = MIC_V_PULSE_WIDTH(vm.hsync_len) +
  137. MIC_V_PERIOD_LINE(vm.hsync_len + vm.hactive +
  138. vm.hback_porch + vm.hfront_porch);
  139. writel(reg, mic->reg + MIC_INPUT_TIMING_0);
  140. reg = MIC_VBP_SIZE(vm.hback_porch) +
  141. MIC_VFP_SIZE(vm.hfront_porch);
  142. writel(reg, mic->reg + MIC_INPUT_TIMING_1);
  143. }
  144. static void mic_set_img_size(struct exynos_mic *mic)
  145. {
  146. struct videomode *vm = &mic->vm;
  147. u32 reg;
  148. reg = MIC_IMG_H_SIZE(vm->hactive) +
  149. MIC_IMG_V_SIZE(vm->vactive);
  150. writel(reg, mic->reg + MIC_IMG_SIZE);
  151. }
  152. static void mic_set_output_timing(struct exynos_mic *mic)
  153. {
  154. struct videomode vm = mic->vm;
  155. u32 reg, bs_size_2d;
  156. DRM_DEV_DEBUG(mic->dev, "w: %u, h: %u\n", vm.hactive, vm.vactive);
  157. bs_size_2d = ((vm.hactive >> 2) << 1) + (vm.vactive % 4);
  158. reg = MIC_BS_SIZE_2D(bs_size_2d);
  159. writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2);
  160. if (!mic->i80_mode) {
  161. reg = MIC_H_PULSE_WIDTH_2D(vm.hsync_len) +
  162. MIC_H_PERIOD_PIXEL_2D(vm.hsync_len + bs_size_2d +
  163. vm.hback_porch + vm.hfront_porch);
  164. writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0);
  165. reg = MIC_HBP_SIZE_2D(vm.hback_porch) +
  166. MIC_H_PERIOD_PIXEL_2D(vm.hfront_porch);
  167. writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1);
  168. }
  169. }
  170. static void mic_set_reg_on(struct exynos_mic *mic, bool enable)
  171. {
  172. u32 reg = readl(mic->reg + MIC_OP);
  173. if (enable) {
  174. reg &= ~(MIC_MODE_SEL_MASK | MIC_CORE_VER_CONTROL | MIC_PSR_EN);
  175. reg |= (MIC_CORE_EN | MIC_BS_CHG_OUT | MIC_ON_REG);
  176. reg &= ~MIC_MODE_SEL_COMMAND_MODE;
  177. if (mic->i80_mode)
  178. reg |= MIC_MODE_SEL_COMMAND_MODE;
  179. } else {
  180. reg &= ~MIC_CORE_EN;
  181. }
  182. reg |= MIC_UPD_REG;
  183. writel(reg, mic->reg + MIC_OP);
  184. }
  185. static void mic_disable(struct drm_bridge *bridge) { }
  186. static void mic_post_disable(struct drm_bridge *bridge)
  187. {
  188. struct exynos_mic *mic = bridge->driver_private;
  189. mutex_lock(&mic_mutex);
  190. if (!mic->enabled)
  191. goto already_disabled;
  192. mic_set_path(mic, 0);
  193. pm_runtime_put(mic->dev);
  194. mic->enabled = 0;
  195. already_disabled:
  196. mutex_unlock(&mic_mutex);
  197. }
  198. static void mic_mode_set(struct drm_bridge *bridge,
  199. const struct drm_display_mode *mode,
  200. const struct drm_display_mode *adjusted_mode)
  201. {
  202. struct exynos_mic *mic = bridge->driver_private;
  203. mutex_lock(&mic_mutex);
  204. drm_display_mode_to_videomode(mode, &mic->vm);
  205. mic->i80_mode = to_exynos_crtc(bridge->encoder->crtc)->i80_mode;
  206. mutex_unlock(&mic_mutex);
  207. }
  208. static void mic_pre_enable(struct drm_bridge *bridge)
  209. {
  210. struct exynos_mic *mic = bridge->driver_private;
  211. int ret;
  212. mutex_lock(&mic_mutex);
  213. if (mic->enabled)
  214. goto unlock;
  215. ret = pm_runtime_get_sync(mic->dev);
  216. if (ret < 0) {
  217. pm_runtime_put_noidle(mic->dev);
  218. goto unlock;
  219. }
  220. mic_set_path(mic, 1);
  221. ret = mic_sw_reset(mic);
  222. if (ret) {
  223. DRM_DEV_ERROR(mic->dev, "Failed to reset\n");
  224. goto turn_off;
  225. }
  226. if (!mic->i80_mode)
  227. mic_set_porch_timing(mic);
  228. mic_set_img_size(mic);
  229. mic_set_output_timing(mic);
  230. mic_set_reg_on(mic, 1);
  231. mic->enabled = 1;
  232. mutex_unlock(&mic_mutex);
  233. return;
  234. turn_off:
  235. pm_runtime_put(mic->dev);
  236. unlock:
  237. mutex_unlock(&mic_mutex);
  238. }
  239. static void mic_enable(struct drm_bridge *bridge) { }
  240. static const struct drm_bridge_funcs mic_bridge_funcs = {
  241. .disable = mic_disable,
  242. .post_disable = mic_post_disable,
  243. .mode_set = mic_mode_set,
  244. .pre_enable = mic_pre_enable,
  245. .enable = mic_enable,
  246. };
  247. static int exynos_mic_bind(struct device *dev, struct device *master,
  248. void *data)
  249. {
  250. struct exynos_mic *mic = dev_get_drvdata(dev);
  251. mic->bridge.driver_private = mic;
  252. return 0;
  253. }
  254. static void exynos_mic_unbind(struct device *dev, struct device *master,
  255. void *data)
  256. {
  257. struct exynos_mic *mic = dev_get_drvdata(dev);
  258. mutex_lock(&mic_mutex);
  259. if (!mic->enabled)
  260. goto already_disabled;
  261. pm_runtime_put(mic->dev);
  262. already_disabled:
  263. mutex_unlock(&mic_mutex);
  264. }
  265. static const struct component_ops exynos_mic_component_ops = {
  266. .bind = exynos_mic_bind,
  267. .unbind = exynos_mic_unbind,
  268. };
  269. #ifdef CONFIG_PM
  270. static int exynos_mic_suspend(struct device *dev)
  271. {
  272. struct exynos_mic *mic = dev_get_drvdata(dev);
  273. int i;
  274. for (i = NUM_CLKS - 1; i > -1; i--)
  275. clk_disable_unprepare(mic->clks[i]);
  276. return 0;
  277. }
  278. static int exynos_mic_resume(struct device *dev)
  279. {
  280. struct exynos_mic *mic = dev_get_drvdata(dev);
  281. int ret, i;
  282. for (i = 0; i < NUM_CLKS; i++) {
  283. ret = clk_prepare_enable(mic->clks[i]);
  284. if (ret < 0) {
  285. DRM_DEV_ERROR(dev, "Failed to enable clock (%s)\n",
  286. clk_names[i]);
  287. while (--i > -1)
  288. clk_disable_unprepare(mic->clks[i]);
  289. return ret;
  290. }
  291. }
  292. return 0;
  293. }
  294. #endif
  295. static const struct dev_pm_ops exynos_mic_pm_ops = {
  296. SET_RUNTIME_PM_OPS(exynos_mic_suspend, exynos_mic_resume, NULL)
  297. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  298. pm_runtime_force_resume)
  299. };
  300. static int exynos_mic_probe(struct platform_device *pdev)
  301. {
  302. struct device *dev = &pdev->dev;
  303. struct exynos_mic *mic;
  304. struct resource res;
  305. int ret, i;
  306. mic = devm_kzalloc(dev, sizeof(*mic), GFP_KERNEL);
  307. if (!mic) {
  308. DRM_DEV_ERROR(dev,
  309. "mic: Failed to allocate memory for MIC object\n");
  310. ret = -ENOMEM;
  311. goto err;
  312. }
  313. mic->dev = dev;
  314. ret = of_address_to_resource(dev->of_node, 0, &res);
  315. if (ret) {
  316. DRM_DEV_ERROR(dev, "mic: Failed to get mem region for MIC\n");
  317. goto err;
  318. }
  319. mic->reg = devm_ioremap(dev, res.start, resource_size(&res));
  320. if (!mic->reg) {
  321. DRM_DEV_ERROR(dev, "mic: Failed to remap for MIC\n");
  322. ret = -ENOMEM;
  323. goto err;
  324. }
  325. mic->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
  326. "samsung,disp-syscon");
  327. if (IS_ERR(mic->sysreg)) {
  328. DRM_DEV_ERROR(dev, "mic: Failed to get system register.\n");
  329. ret = PTR_ERR(mic->sysreg);
  330. goto err;
  331. }
  332. for (i = 0; i < NUM_CLKS; i++) {
  333. mic->clks[i] = devm_clk_get(dev, clk_names[i]);
  334. if (IS_ERR(mic->clks[i])) {
  335. DRM_DEV_ERROR(dev, "mic: Failed to get clock (%s)\n",
  336. clk_names[i]);
  337. ret = PTR_ERR(mic->clks[i]);
  338. goto err;
  339. }
  340. }
  341. platform_set_drvdata(pdev, mic);
  342. mic->bridge.funcs = &mic_bridge_funcs;
  343. mic->bridge.of_node = dev->of_node;
  344. drm_bridge_add(&mic->bridge);
  345. pm_runtime_enable(dev);
  346. ret = component_add(dev, &exynos_mic_component_ops);
  347. if (ret)
  348. goto err_pm;
  349. DRM_DEV_DEBUG_KMS(dev, "MIC has been probed\n");
  350. return 0;
  351. err_pm:
  352. pm_runtime_disable(dev);
  353. err:
  354. return ret;
  355. }
  356. static int exynos_mic_remove(struct platform_device *pdev)
  357. {
  358. struct exynos_mic *mic = platform_get_drvdata(pdev);
  359. component_del(&pdev->dev, &exynos_mic_component_ops);
  360. pm_runtime_disable(&pdev->dev);
  361. drm_bridge_remove(&mic->bridge);
  362. return 0;
  363. }
  364. static const struct of_device_id exynos_mic_of_match[] = {
  365. { .compatible = "samsung,exynos5433-mic" },
  366. { }
  367. };
  368. MODULE_DEVICE_TABLE(of, exynos_mic_of_match);
  369. struct platform_driver mic_driver = {
  370. .probe = exynos_mic_probe,
  371. .remove = exynos_mic_remove,
  372. .driver = {
  373. .name = "exynos-mic",
  374. .pm = &exynos_mic_pm_ops,
  375. .owner = THIS_MODULE,
  376. .of_match_table = exynos_mic_of_match,
  377. },
  378. };