exynos_drm_gsc.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  4. * Authors:
  5. * Eunchul Kim <chulspro.kim@samsung.com>
  6. * Jinyoung Jeon <jy0.jeon@samsung.com>
  7. * Sangmin Lee <lsmin.lee@samsung.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/component.h>
  11. #include <linux/kernel.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/regmap.h>
  17. #include <drm/drm_fourcc.h>
  18. #include <drm/drm_print.h>
  19. #include <drm/exynos_drm.h>
  20. #include "exynos_drm_drv.h"
  21. #include "exynos_drm_ipp.h"
  22. #include "regs-gsc.h"
  23. /*
  24. * GSC stands for General SCaler and
  25. * supports image scaler/rotator and input/output DMA operations.
  26. * input DMA reads image data from the memory.
  27. * output DMA writes image data to memory.
  28. * GSC supports image rotation and image effect functions.
  29. */
  30. #define GSC_MAX_CLOCKS 8
  31. #define GSC_MAX_SRC 4
  32. #define GSC_MAX_DST 16
  33. #define GSC_RESET_TIMEOUT 50
  34. #define GSC_BUF_STOP 1
  35. #define GSC_BUF_START 2
  36. #define GSC_REG_SZ 16
  37. #define GSC_WIDTH_ITU_709 1280
  38. #define GSC_SC_UP_MAX_RATIO 65536
  39. #define GSC_SC_DOWN_RATIO_7_8 74898
  40. #define GSC_SC_DOWN_RATIO_6_8 87381
  41. #define GSC_SC_DOWN_RATIO_5_8 104857
  42. #define GSC_SC_DOWN_RATIO_4_8 131072
  43. #define GSC_SC_DOWN_RATIO_3_8 174762
  44. #define GSC_SC_DOWN_RATIO_2_8 262144
  45. #define GSC_CROP_MAX 8192
  46. #define GSC_CROP_MIN 32
  47. #define GSC_SCALE_MAX 4224
  48. #define GSC_SCALE_MIN 32
  49. #define GSC_COEF_RATIO 7
  50. #define GSC_COEF_PHASE 9
  51. #define GSC_COEF_ATTR 16
  52. #define GSC_COEF_H_8T 8
  53. #define GSC_COEF_V_4T 4
  54. #define GSC_COEF_DEPTH 3
  55. #define GSC_AUTOSUSPEND_DELAY 2000
  56. #define get_gsc_context(dev) dev_get_drvdata(dev)
  57. #define gsc_read(offset) readl(ctx->regs + (offset))
  58. #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
  59. /*
  60. * A structure of scaler.
  61. *
  62. * @range: narrow, wide.
  63. * @pre_shfactor: pre sclaer shift factor.
  64. * @pre_hratio: horizontal ratio of the prescaler.
  65. * @pre_vratio: vertical ratio of the prescaler.
  66. * @main_hratio: the main scaler's horizontal ratio.
  67. * @main_vratio: the main scaler's vertical ratio.
  68. */
  69. struct gsc_scaler {
  70. bool range;
  71. u32 pre_shfactor;
  72. u32 pre_hratio;
  73. u32 pre_vratio;
  74. unsigned long main_hratio;
  75. unsigned long main_vratio;
  76. };
  77. /*
  78. * A structure of gsc context.
  79. *
  80. * @regs_res: register resources.
  81. * @regs: memory mapped io registers.
  82. * @gsc_clk: gsc gate clock.
  83. * @sc: scaler infomations.
  84. * @id: gsc id.
  85. * @irq: irq number.
  86. * @rotation: supports rotation of src.
  87. */
  88. struct gsc_context {
  89. struct exynos_drm_ipp ipp;
  90. struct drm_device *drm_dev;
  91. void *dma_priv;
  92. struct device *dev;
  93. struct exynos_drm_ipp_task *task;
  94. struct exynos_drm_ipp_formats *formats;
  95. unsigned int num_formats;
  96. struct resource *regs_res;
  97. void __iomem *regs;
  98. const char **clk_names;
  99. struct clk *clocks[GSC_MAX_CLOCKS];
  100. int num_clocks;
  101. struct gsc_scaler sc;
  102. int id;
  103. int irq;
  104. bool rotation;
  105. };
  106. /**
  107. * struct gsc_driverdata - per device type driver data for init time.
  108. *
  109. * @limits: picture size limits array
  110. * @clk_names: names of clocks needed by this variant
  111. * @num_clocks: the number of clocks needed by this variant
  112. */
  113. struct gsc_driverdata {
  114. const struct drm_exynos_ipp_limit *limits;
  115. int num_limits;
  116. const char *clk_names[GSC_MAX_CLOCKS];
  117. int num_clocks;
  118. };
  119. /* 8-tap Filter Coefficient */
  120. static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
  121. { /* Ratio <= 65536 (~8:8) */
  122. { 0, 0, 0, 128, 0, 0, 0, 0 },
  123. { -1, 2, -6, 127, 7, -2, 1, 0 },
  124. { -1, 4, -12, 125, 16, -5, 1, 0 },
  125. { -1, 5, -15, 120, 25, -8, 2, 0 },
  126. { -1, 6, -18, 114, 35, -10, 3, -1 },
  127. { -1, 6, -20, 107, 46, -13, 4, -1 },
  128. { -2, 7, -21, 99, 57, -16, 5, -1 },
  129. { -1, 6, -20, 89, 68, -18, 5, -1 },
  130. { -1, 6, -20, 79, 79, -20, 6, -1 },
  131. { -1, 5, -18, 68, 89, -20, 6, -1 },
  132. { -1, 5, -16, 57, 99, -21, 7, -2 },
  133. { -1, 4, -13, 46, 107, -20, 6, -1 },
  134. { -1, 3, -10, 35, 114, -18, 6, -1 },
  135. { 0, 2, -8, 25, 120, -15, 5, -1 },
  136. { 0, 1, -5, 16, 125, -12, 4, -1 },
  137. { 0, 1, -2, 7, 127, -6, 2, -1 }
  138. }, { /* 65536 < Ratio <= 74898 (~8:7) */
  139. { 3, -8, 14, 111, 13, -8, 3, 0 },
  140. { 2, -6, 7, 112, 21, -10, 3, -1 },
  141. { 2, -4, 1, 110, 28, -12, 4, -1 },
  142. { 1, -2, -3, 106, 36, -13, 4, -1 },
  143. { 1, -1, -7, 103, 44, -15, 4, -1 },
  144. { 1, 1, -11, 97, 53, -16, 4, -1 },
  145. { 0, 2, -13, 91, 61, -16, 4, -1 },
  146. { 0, 3, -15, 85, 69, -17, 4, -1 },
  147. { 0, 3, -16, 77, 77, -16, 3, 0 },
  148. { -1, 4, -17, 69, 85, -15, 3, 0 },
  149. { -1, 4, -16, 61, 91, -13, 2, 0 },
  150. { -1, 4, -16, 53, 97, -11, 1, 1 },
  151. { -1, 4, -15, 44, 103, -7, -1, 1 },
  152. { -1, 4, -13, 36, 106, -3, -2, 1 },
  153. { -1, 4, -12, 28, 110, 1, -4, 2 },
  154. { -1, 3, -10, 21, 112, 7, -6, 2 }
  155. }, { /* 74898 < Ratio <= 87381 (~8:6) */
  156. { 2, -11, 25, 96, 25, -11, 2, 0 },
  157. { 2, -10, 19, 96, 31, -12, 2, 0 },
  158. { 2, -9, 14, 94, 37, -12, 2, 0 },
  159. { 2, -8, 10, 92, 43, -12, 1, 0 },
  160. { 2, -7, 5, 90, 49, -12, 1, 0 },
  161. { 2, -5, 1, 86, 55, -12, 0, 1 },
  162. { 2, -4, -2, 82, 61, -11, -1, 1 },
  163. { 1, -3, -5, 77, 67, -9, -1, 1 },
  164. { 1, -2, -7, 72, 72, -7, -2, 1 },
  165. { 1, -1, -9, 67, 77, -5, -3, 1 },
  166. { 1, -1, -11, 61, 82, -2, -4, 2 },
  167. { 1, 0, -12, 55, 86, 1, -5, 2 },
  168. { 0, 1, -12, 49, 90, 5, -7, 2 },
  169. { 0, 1, -12, 43, 92, 10, -8, 2 },
  170. { 0, 2, -12, 37, 94, 14, -9, 2 },
  171. { 0, 2, -12, 31, 96, 19, -10, 2 }
  172. }, { /* 87381 < Ratio <= 104857 (~8:5) */
  173. { -1, -8, 33, 80, 33, -8, -1, 0 },
  174. { -1, -8, 28, 80, 37, -7, -2, 1 },
  175. { 0, -8, 24, 79, 41, -7, -2, 1 },
  176. { 0, -8, 20, 78, 46, -6, -3, 1 },
  177. { 0, -8, 16, 76, 50, -4, -3, 1 },
  178. { 0, -7, 13, 74, 54, -3, -4, 1 },
  179. { 1, -7, 10, 71, 58, -1, -5, 1 },
  180. { 1, -6, 6, 68, 62, 1, -5, 1 },
  181. { 1, -6, 4, 65, 65, 4, -6, 1 },
  182. { 1, -5, 1, 62, 68, 6, -6, 1 },
  183. { 1, -5, -1, 58, 71, 10, -7, 1 },
  184. { 1, -4, -3, 54, 74, 13, -7, 0 },
  185. { 1, -3, -4, 50, 76, 16, -8, 0 },
  186. { 1, -3, -6, 46, 78, 20, -8, 0 },
  187. { 1, -2, -7, 41, 79, 24, -8, 0 },
  188. { 1, -2, -7, 37, 80, 28, -8, -1 }
  189. }, { /* 104857 < Ratio <= 131072 (~8:4) */
  190. { -3, 0, 35, 64, 35, 0, -3, 0 },
  191. { -3, -1, 32, 64, 38, 1, -3, 0 },
  192. { -2, -2, 29, 63, 41, 2, -3, 0 },
  193. { -2, -3, 27, 63, 43, 4, -4, 0 },
  194. { -2, -3, 24, 61, 46, 6, -4, 0 },
  195. { -2, -3, 21, 60, 49, 7, -4, 0 },
  196. { -1, -4, 19, 59, 51, 9, -4, -1 },
  197. { -1, -4, 16, 57, 53, 12, -4, -1 },
  198. { -1, -4, 14, 55, 55, 14, -4, -1 },
  199. { -1, -4, 12, 53, 57, 16, -4, -1 },
  200. { -1, -4, 9, 51, 59, 19, -4, -1 },
  201. { 0, -4, 7, 49, 60, 21, -3, -2 },
  202. { 0, -4, 6, 46, 61, 24, -3, -2 },
  203. { 0, -4, 4, 43, 63, 27, -3, -2 },
  204. { 0, -3, 2, 41, 63, 29, -2, -2 },
  205. { 0, -3, 1, 38, 64, 32, -1, -3 }
  206. }, { /* 131072 < Ratio <= 174762 (~8:3) */
  207. { -1, 8, 33, 48, 33, 8, -1, 0 },
  208. { -1, 7, 31, 49, 35, 9, -1, -1 },
  209. { -1, 6, 30, 49, 36, 10, -1, -1 },
  210. { -1, 5, 28, 48, 38, 12, -1, -1 },
  211. { -1, 4, 26, 48, 39, 13, 0, -1 },
  212. { -1, 3, 24, 47, 41, 15, 0, -1 },
  213. { -1, 2, 23, 47, 42, 16, 0, -1 },
  214. { -1, 2, 21, 45, 43, 18, 1, -1 },
  215. { -1, 1, 19, 45, 45, 19, 1, -1 },
  216. { -1, 1, 18, 43, 45, 21, 2, -1 },
  217. { -1, 0, 16, 42, 47, 23, 2, -1 },
  218. { -1, 0, 15, 41, 47, 24, 3, -1 },
  219. { -1, 0, 13, 39, 48, 26, 4, -1 },
  220. { -1, -1, 12, 38, 48, 28, 5, -1 },
  221. { -1, -1, 10, 36, 49, 30, 6, -1 },
  222. { -1, -1, 9, 35, 49, 31, 7, -1 }
  223. }, { /* 174762 < Ratio <= 262144 (~8:2) */
  224. { 2, 13, 30, 38, 30, 13, 2, 0 },
  225. { 2, 12, 29, 38, 30, 14, 3, 0 },
  226. { 2, 11, 28, 38, 31, 15, 3, 0 },
  227. { 2, 10, 26, 38, 32, 16, 4, 0 },
  228. { 1, 10, 26, 37, 33, 17, 4, 0 },
  229. { 1, 9, 24, 37, 34, 18, 5, 0 },
  230. { 1, 8, 24, 37, 34, 19, 5, 0 },
  231. { 1, 7, 22, 36, 35, 20, 6, 1 },
  232. { 1, 6, 21, 36, 36, 21, 6, 1 },
  233. { 1, 6, 20, 35, 36, 22, 7, 1 },
  234. { 0, 5, 19, 34, 37, 24, 8, 1 },
  235. { 0, 5, 18, 34, 37, 24, 9, 1 },
  236. { 0, 4, 17, 33, 37, 26, 10, 1 },
  237. { 0, 4, 16, 32, 38, 26, 10, 2 },
  238. { 0, 3, 15, 31, 38, 28, 11, 2 },
  239. { 0, 3, 14, 30, 38, 29, 12, 2 }
  240. }
  241. };
  242. /* 4-tap Filter Coefficient */
  243. static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
  244. { /* Ratio <= 65536 (~8:8) */
  245. { 0, 128, 0, 0 },
  246. { -4, 127, 5, 0 },
  247. { -6, 124, 11, -1 },
  248. { -8, 118, 19, -1 },
  249. { -8, 111, 27, -2 },
  250. { -8, 102, 37, -3 },
  251. { -8, 92, 48, -4 },
  252. { -7, 81, 59, -5 },
  253. { -6, 70, 70, -6 },
  254. { -5, 59, 81, -7 },
  255. { -4, 48, 92, -8 },
  256. { -3, 37, 102, -8 },
  257. { -2, 27, 111, -8 },
  258. { -1, 19, 118, -8 },
  259. { -1, 11, 124, -6 },
  260. { 0, 5, 127, -4 }
  261. }, { /* 65536 < Ratio <= 74898 (~8:7) */
  262. { 8, 112, 8, 0 },
  263. { 4, 111, 14, -1 },
  264. { 1, 109, 20, -2 },
  265. { -2, 105, 27, -2 },
  266. { -3, 100, 34, -3 },
  267. { -5, 93, 43, -3 },
  268. { -5, 86, 51, -4 },
  269. { -5, 77, 60, -4 },
  270. { -5, 69, 69, -5 },
  271. { -4, 60, 77, -5 },
  272. { -4, 51, 86, -5 },
  273. { -3, 43, 93, -5 },
  274. { -3, 34, 100, -3 },
  275. { -2, 27, 105, -2 },
  276. { -2, 20, 109, 1 },
  277. { -1, 14, 111, 4 }
  278. }, { /* 74898 < Ratio <= 87381 (~8:6) */
  279. { 16, 96, 16, 0 },
  280. { 12, 97, 21, -2 },
  281. { 8, 96, 26, -2 },
  282. { 5, 93, 32, -2 },
  283. { 2, 89, 39, -2 },
  284. { 0, 84, 46, -2 },
  285. { -1, 79, 53, -3 },
  286. { -2, 73, 59, -2 },
  287. { -2, 66, 66, -2 },
  288. { -2, 59, 73, -2 },
  289. { -3, 53, 79, -1 },
  290. { -2, 46, 84, 0 },
  291. { -2, 39, 89, 2 },
  292. { -2, 32, 93, 5 },
  293. { -2, 26, 96, 8 },
  294. { -2, 21, 97, 12 }
  295. }, { /* 87381 < Ratio <= 104857 (~8:5) */
  296. { 22, 84, 22, 0 },
  297. { 18, 85, 26, -1 },
  298. { 14, 84, 31, -1 },
  299. { 11, 82, 36, -1 },
  300. { 8, 79, 42, -1 },
  301. { 6, 76, 47, -1 },
  302. { 4, 72, 52, 0 },
  303. { 2, 68, 58, 0 },
  304. { 1, 63, 63, 1 },
  305. { 0, 58, 68, 2 },
  306. { 0, 52, 72, 4 },
  307. { -1, 47, 76, 6 },
  308. { -1, 42, 79, 8 },
  309. { -1, 36, 82, 11 },
  310. { -1, 31, 84, 14 },
  311. { -1, 26, 85, 18 }
  312. }, { /* 104857 < Ratio <= 131072 (~8:4) */
  313. { 26, 76, 26, 0 },
  314. { 22, 76, 30, 0 },
  315. { 19, 75, 34, 0 },
  316. { 16, 73, 38, 1 },
  317. { 13, 71, 43, 1 },
  318. { 10, 69, 47, 2 },
  319. { 8, 66, 51, 3 },
  320. { 6, 63, 55, 4 },
  321. { 5, 59, 59, 5 },
  322. { 4, 55, 63, 6 },
  323. { 3, 51, 66, 8 },
  324. { 2, 47, 69, 10 },
  325. { 1, 43, 71, 13 },
  326. { 1, 38, 73, 16 },
  327. { 0, 34, 75, 19 },
  328. { 0, 30, 76, 22 }
  329. }, { /* 131072 < Ratio <= 174762 (~8:3) */
  330. { 29, 70, 29, 0 },
  331. { 26, 68, 32, 2 },
  332. { 23, 67, 36, 2 },
  333. { 20, 66, 39, 3 },
  334. { 17, 65, 43, 3 },
  335. { 15, 63, 46, 4 },
  336. { 12, 61, 50, 5 },
  337. { 10, 58, 53, 7 },
  338. { 8, 56, 56, 8 },
  339. { 7, 53, 58, 10 },
  340. { 5, 50, 61, 12 },
  341. { 4, 46, 63, 15 },
  342. { 3, 43, 65, 17 },
  343. { 3, 39, 66, 20 },
  344. { 2, 36, 67, 23 },
  345. { 2, 32, 68, 26 }
  346. }, { /* 174762 < Ratio <= 262144 (~8:2) */
  347. { 32, 64, 32, 0 },
  348. { 28, 63, 34, 3 },
  349. { 25, 62, 37, 4 },
  350. { 22, 62, 40, 4 },
  351. { 19, 61, 43, 5 },
  352. { 17, 59, 46, 6 },
  353. { 15, 58, 48, 7 },
  354. { 13, 55, 51, 9 },
  355. { 11, 53, 53, 11 },
  356. { 9, 51, 55, 13 },
  357. { 7, 48, 58, 15 },
  358. { 6, 46, 59, 17 },
  359. { 5, 43, 61, 19 },
  360. { 4, 40, 62, 22 },
  361. { 4, 37, 62, 25 },
  362. { 3, 34, 63, 28 }
  363. }
  364. };
  365. static int gsc_sw_reset(struct gsc_context *ctx)
  366. {
  367. u32 cfg;
  368. int count = GSC_RESET_TIMEOUT;
  369. /* s/w reset */
  370. cfg = (GSC_SW_RESET_SRESET);
  371. gsc_write(cfg, GSC_SW_RESET);
  372. /* wait s/w reset complete */
  373. while (count--) {
  374. cfg = gsc_read(GSC_SW_RESET);
  375. if (!cfg)
  376. break;
  377. usleep_range(1000, 2000);
  378. }
  379. if (cfg) {
  380. DRM_DEV_ERROR(ctx->dev, "failed to reset gsc h/w.\n");
  381. return -EBUSY;
  382. }
  383. /* reset sequence */
  384. cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
  385. cfg |= (GSC_IN_BASE_ADDR_MASK |
  386. GSC_IN_BASE_ADDR_PINGPONG(0));
  387. gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
  388. gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
  389. gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
  390. cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
  391. cfg |= (GSC_OUT_BASE_ADDR_MASK |
  392. GSC_OUT_BASE_ADDR_PINGPONG(0));
  393. gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
  394. gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
  395. gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
  396. return 0;
  397. }
  398. static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
  399. bool overflow, bool done)
  400. {
  401. u32 cfg;
  402. DRM_DEV_DEBUG_KMS(ctx->dev, "enable[%d]overflow[%d]level[%d]\n",
  403. enable, overflow, done);
  404. cfg = gsc_read(GSC_IRQ);
  405. cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
  406. if (enable)
  407. cfg |= GSC_IRQ_ENABLE;
  408. else
  409. cfg &= ~GSC_IRQ_ENABLE;
  410. if (overflow)
  411. cfg &= ~GSC_IRQ_OR_MASK;
  412. else
  413. cfg |= GSC_IRQ_OR_MASK;
  414. if (done)
  415. cfg &= ~GSC_IRQ_FRMDONE_MASK;
  416. else
  417. cfg |= GSC_IRQ_FRMDONE_MASK;
  418. gsc_write(cfg, GSC_IRQ);
  419. }
  420. static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
  421. {
  422. u32 cfg;
  423. DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
  424. cfg = gsc_read(GSC_IN_CON);
  425. cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
  426. GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
  427. GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
  428. GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
  429. switch (fmt) {
  430. case DRM_FORMAT_RGB565:
  431. cfg |= GSC_IN_RGB565;
  432. break;
  433. case DRM_FORMAT_XRGB8888:
  434. case DRM_FORMAT_ARGB8888:
  435. cfg |= GSC_IN_XRGB8888;
  436. break;
  437. case DRM_FORMAT_BGRX8888:
  438. cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
  439. break;
  440. case DRM_FORMAT_YUYV:
  441. cfg |= (GSC_IN_YUV422_1P |
  442. GSC_IN_YUV422_1P_ORDER_LSB_Y |
  443. GSC_IN_CHROMA_ORDER_CBCR);
  444. break;
  445. case DRM_FORMAT_YVYU:
  446. cfg |= (GSC_IN_YUV422_1P |
  447. GSC_IN_YUV422_1P_ORDER_LSB_Y |
  448. GSC_IN_CHROMA_ORDER_CRCB);
  449. break;
  450. case DRM_FORMAT_UYVY:
  451. cfg |= (GSC_IN_YUV422_1P |
  452. GSC_IN_YUV422_1P_OEDER_LSB_C |
  453. GSC_IN_CHROMA_ORDER_CBCR);
  454. break;
  455. case DRM_FORMAT_VYUY:
  456. cfg |= (GSC_IN_YUV422_1P |
  457. GSC_IN_YUV422_1P_OEDER_LSB_C |
  458. GSC_IN_CHROMA_ORDER_CRCB);
  459. break;
  460. case DRM_FORMAT_NV21:
  461. cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
  462. break;
  463. case DRM_FORMAT_NV61:
  464. cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
  465. break;
  466. case DRM_FORMAT_YUV422:
  467. cfg |= GSC_IN_YUV422_3P;
  468. break;
  469. case DRM_FORMAT_YUV420:
  470. cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
  471. break;
  472. case DRM_FORMAT_YVU420:
  473. cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
  474. break;
  475. case DRM_FORMAT_NV12:
  476. cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
  477. break;
  478. case DRM_FORMAT_NV16:
  479. cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
  480. break;
  481. }
  482. if (tiled)
  483. cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
  484. gsc_write(cfg, GSC_IN_CON);
  485. }
  486. static void gsc_src_set_transf(struct gsc_context *ctx, unsigned int rotation)
  487. {
  488. unsigned int degree = rotation & DRM_MODE_ROTATE_MASK;
  489. u32 cfg;
  490. cfg = gsc_read(GSC_IN_CON);
  491. cfg &= ~GSC_IN_ROT_MASK;
  492. switch (degree) {
  493. case DRM_MODE_ROTATE_0:
  494. if (rotation & DRM_MODE_REFLECT_X)
  495. cfg |= GSC_IN_ROT_XFLIP;
  496. if (rotation & DRM_MODE_REFLECT_Y)
  497. cfg |= GSC_IN_ROT_YFLIP;
  498. break;
  499. case DRM_MODE_ROTATE_90:
  500. cfg |= GSC_IN_ROT_90;
  501. if (rotation & DRM_MODE_REFLECT_X)
  502. cfg |= GSC_IN_ROT_XFLIP;
  503. if (rotation & DRM_MODE_REFLECT_Y)
  504. cfg |= GSC_IN_ROT_YFLIP;
  505. break;
  506. case DRM_MODE_ROTATE_180:
  507. cfg |= GSC_IN_ROT_180;
  508. if (rotation & DRM_MODE_REFLECT_X)
  509. cfg &= ~GSC_IN_ROT_XFLIP;
  510. if (rotation & DRM_MODE_REFLECT_Y)
  511. cfg &= ~GSC_IN_ROT_YFLIP;
  512. break;
  513. case DRM_MODE_ROTATE_270:
  514. cfg |= GSC_IN_ROT_270;
  515. if (rotation & DRM_MODE_REFLECT_X)
  516. cfg &= ~GSC_IN_ROT_XFLIP;
  517. if (rotation & DRM_MODE_REFLECT_Y)
  518. cfg &= ~GSC_IN_ROT_YFLIP;
  519. break;
  520. }
  521. gsc_write(cfg, GSC_IN_CON);
  522. ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
  523. }
  524. static void gsc_src_set_size(struct gsc_context *ctx,
  525. struct exynos_drm_ipp_buffer *buf)
  526. {
  527. struct gsc_scaler *sc = &ctx->sc;
  528. u32 cfg;
  529. /* pixel offset */
  530. cfg = (GSC_SRCIMG_OFFSET_X(buf->rect.x) |
  531. GSC_SRCIMG_OFFSET_Y(buf->rect.y));
  532. gsc_write(cfg, GSC_SRCIMG_OFFSET);
  533. /* cropped size */
  534. cfg = (GSC_CROPPED_WIDTH(buf->rect.w) |
  535. GSC_CROPPED_HEIGHT(buf->rect.h));
  536. gsc_write(cfg, GSC_CROPPED_SIZE);
  537. /* original size */
  538. cfg = gsc_read(GSC_SRCIMG_SIZE);
  539. cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
  540. GSC_SRCIMG_WIDTH_MASK);
  541. cfg |= (GSC_SRCIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
  542. GSC_SRCIMG_HEIGHT(buf->buf.height));
  543. gsc_write(cfg, GSC_SRCIMG_SIZE);
  544. cfg = gsc_read(GSC_IN_CON);
  545. cfg &= ~GSC_IN_RGB_TYPE_MASK;
  546. if (buf->rect.w >= GSC_WIDTH_ITU_709)
  547. if (sc->range)
  548. cfg |= GSC_IN_RGB_HD_WIDE;
  549. else
  550. cfg |= GSC_IN_RGB_HD_NARROW;
  551. else
  552. if (sc->range)
  553. cfg |= GSC_IN_RGB_SD_WIDE;
  554. else
  555. cfg |= GSC_IN_RGB_SD_NARROW;
  556. gsc_write(cfg, GSC_IN_CON);
  557. }
  558. static void gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
  559. bool enqueue)
  560. {
  561. bool masked = !enqueue;
  562. u32 cfg;
  563. u32 mask = 0x00000001 << buf_id;
  564. /* mask register set */
  565. cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
  566. /* sequence id */
  567. cfg &= ~mask;
  568. cfg |= masked << buf_id;
  569. gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
  570. gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
  571. gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
  572. }
  573. static void gsc_src_set_addr(struct gsc_context *ctx, u32 buf_id,
  574. struct exynos_drm_ipp_buffer *buf)
  575. {
  576. /* address register set */
  577. gsc_write(buf->dma_addr[0], GSC_IN_BASE_ADDR_Y(buf_id));
  578. gsc_write(buf->dma_addr[1], GSC_IN_BASE_ADDR_CB(buf_id));
  579. gsc_write(buf->dma_addr[2], GSC_IN_BASE_ADDR_CR(buf_id));
  580. gsc_src_set_buf_seq(ctx, buf_id, true);
  581. }
  582. static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
  583. {
  584. u32 cfg;
  585. DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
  586. cfg = gsc_read(GSC_OUT_CON);
  587. cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
  588. GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
  589. GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
  590. GSC_OUT_GLOBAL_ALPHA_MASK);
  591. switch (fmt) {
  592. case DRM_FORMAT_RGB565:
  593. cfg |= GSC_OUT_RGB565;
  594. break;
  595. case DRM_FORMAT_ARGB8888:
  596. case DRM_FORMAT_XRGB8888:
  597. cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_GLOBAL_ALPHA(0xff));
  598. break;
  599. case DRM_FORMAT_BGRX8888:
  600. cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
  601. break;
  602. case DRM_FORMAT_YUYV:
  603. cfg |= (GSC_OUT_YUV422_1P |
  604. GSC_OUT_YUV422_1P_ORDER_LSB_Y |
  605. GSC_OUT_CHROMA_ORDER_CBCR);
  606. break;
  607. case DRM_FORMAT_YVYU:
  608. cfg |= (GSC_OUT_YUV422_1P |
  609. GSC_OUT_YUV422_1P_ORDER_LSB_Y |
  610. GSC_OUT_CHROMA_ORDER_CRCB);
  611. break;
  612. case DRM_FORMAT_UYVY:
  613. cfg |= (GSC_OUT_YUV422_1P |
  614. GSC_OUT_YUV422_1P_OEDER_LSB_C |
  615. GSC_OUT_CHROMA_ORDER_CBCR);
  616. break;
  617. case DRM_FORMAT_VYUY:
  618. cfg |= (GSC_OUT_YUV422_1P |
  619. GSC_OUT_YUV422_1P_OEDER_LSB_C |
  620. GSC_OUT_CHROMA_ORDER_CRCB);
  621. break;
  622. case DRM_FORMAT_NV21:
  623. cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
  624. break;
  625. case DRM_FORMAT_NV61:
  626. cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
  627. break;
  628. case DRM_FORMAT_YUV422:
  629. cfg |= GSC_OUT_YUV422_3P;
  630. break;
  631. case DRM_FORMAT_YUV420:
  632. cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
  633. break;
  634. case DRM_FORMAT_YVU420:
  635. cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
  636. break;
  637. case DRM_FORMAT_NV12:
  638. cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
  639. break;
  640. case DRM_FORMAT_NV16:
  641. cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
  642. break;
  643. }
  644. if (tiled)
  645. cfg |= (GSC_IN_TILE_C_16x8 | GSC_OUT_TILE_MODE);
  646. gsc_write(cfg, GSC_OUT_CON);
  647. }
  648. static int gsc_get_ratio_shift(struct gsc_context *ctx, u32 src, u32 dst,
  649. u32 *ratio)
  650. {
  651. DRM_DEV_DEBUG_KMS(ctx->dev, "src[%d]dst[%d]\n", src, dst);
  652. if (src >= dst * 8) {
  653. DRM_DEV_ERROR(ctx->dev, "failed to make ratio and shift.\n");
  654. return -EINVAL;
  655. } else if (src >= dst * 4)
  656. *ratio = 4;
  657. else if (src >= dst * 2)
  658. *ratio = 2;
  659. else
  660. *ratio = 1;
  661. return 0;
  662. }
  663. static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
  664. {
  665. if (hratio == 4 && vratio == 4)
  666. *shfactor = 4;
  667. else if ((hratio == 4 && vratio == 2) ||
  668. (hratio == 2 && vratio == 4))
  669. *shfactor = 3;
  670. else if ((hratio == 4 && vratio == 1) ||
  671. (hratio == 1 && vratio == 4) ||
  672. (hratio == 2 && vratio == 2))
  673. *shfactor = 2;
  674. else if (hratio == 1 && vratio == 1)
  675. *shfactor = 0;
  676. else
  677. *shfactor = 1;
  678. }
  679. static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
  680. struct drm_exynos_ipp_task_rect *src,
  681. struct drm_exynos_ipp_task_rect *dst)
  682. {
  683. u32 cfg;
  684. u32 src_w, src_h, dst_w, dst_h;
  685. int ret = 0;
  686. src_w = src->w;
  687. src_h = src->h;
  688. if (ctx->rotation) {
  689. dst_w = dst->h;
  690. dst_h = dst->w;
  691. } else {
  692. dst_w = dst->w;
  693. dst_h = dst->h;
  694. }
  695. ret = gsc_get_ratio_shift(ctx, src_w, dst_w, &sc->pre_hratio);
  696. if (ret) {
  697. DRM_DEV_ERROR(ctx->dev, "failed to get ratio horizontal.\n");
  698. return ret;
  699. }
  700. ret = gsc_get_ratio_shift(ctx, src_h, dst_h, &sc->pre_vratio);
  701. if (ret) {
  702. DRM_DEV_ERROR(ctx->dev, "failed to get ratio vertical.\n");
  703. return ret;
  704. }
  705. DRM_DEV_DEBUG_KMS(ctx->dev, "pre_hratio[%d]pre_vratio[%d]\n",
  706. sc->pre_hratio, sc->pre_vratio);
  707. sc->main_hratio = (src_w << 16) / dst_w;
  708. sc->main_vratio = (src_h << 16) / dst_h;
  709. DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
  710. sc->main_hratio, sc->main_vratio);
  711. gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
  712. &sc->pre_shfactor);
  713. DRM_DEV_DEBUG_KMS(ctx->dev, "pre_shfactor[%d]\n", sc->pre_shfactor);
  714. cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
  715. GSC_PRESC_H_RATIO(sc->pre_hratio) |
  716. GSC_PRESC_V_RATIO(sc->pre_vratio));
  717. gsc_write(cfg, GSC_PRE_SCALE_RATIO);
  718. return ret;
  719. }
  720. static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
  721. {
  722. int i, j, k, sc_ratio;
  723. if (main_hratio <= GSC_SC_UP_MAX_RATIO)
  724. sc_ratio = 0;
  725. else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
  726. sc_ratio = 1;
  727. else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
  728. sc_ratio = 2;
  729. else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
  730. sc_ratio = 3;
  731. else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
  732. sc_ratio = 4;
  733. else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
  734. sc_ratio = 5;
  735. else
  736. sc_ratio = 6;
  737. for (i = 0; i < GSC_COEF_PHASE; i++)
  738. for (j = 0; j < GSC_COEF_H_8T; j++)
  739. for (k = 0; k < GSC_COEF_DEPTH; k++)
  740. gsc_write(h_coef_8t[sc_ratio][i][j],
  741. GSC_HCOEF(i, j, k));
  742. }
  743. static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
  744. {
  745. int i, j, k, sc_ratio;
  746. if (main_vratio <= GSC_SC_UP_MAX_RATIO)
  747. sc_ratio = 0;
  748. else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
  749. sc_ratio = 1;
  750. else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
  751. sc_ratio = 2;
  752. else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
  753. sc_ratio = 3;
  754. else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
  755. sc_ratio = 4;
  756. else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
  757. sc_ratio = 5;
  758. else
  759. sc_ratio = 6;
  760. for (i = 0; i < GSC_COEF_PHASE; i++)
  761. for (j = 0; j < GSC_COEF_V_4T; j++)
  762. for (k = 0; k < GSC_COEF_DEPTH; k++)
  763. gsc_write(v_coef_4t[sc_ratio][i][j],
  764. GSC_VCOEF(i, j, k));
  765. }
  766. static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
  767. {
  768. u32 cfg;
  769. DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
  770. sc->main_hratio, sc->main_vratio);
  771. gsc_set_h_coef(ctx, sc->main_hratio);
  772. cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
  773. gsc_write(cfg, GSC_MAIN_H_RATIO);
  774. gsc_set_v_coef(ctx, sc->main_vratio);
  775. cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
  776. gsc_write(cfg, GSC_MAIN_V_RATIO);
  777. }
  778. static void gsc_dst_set_size(struct gsc_context *ctx,
  779. struct exynos_drm_ipp_buffer *buf)
  780. {
  781. struct gsc_scaler *sc = &ctx->sc;
  782. u32 cfg;
  783. /* pixel offset */
  784. cfg = (GSC_DSTIMG_OFFSET_X(buf->rect.x) |
  785. GSC_DSTIMG_OFFSET_Y(buf->rect.y));
  786. gsc_write(cfg, GSC_DSTIMG_OFFSET);
  787. /* scaled size */
  788. if (ctx->rotation)
  789. cfg = (GSC_SCALED_WIDTH(buf->rect.h) |
  790. GSC_SCALED_HEIGHT(buf->rect.w));
  791. else
  792. cfg = (GSC_SCALED_WIDTH(buf->rect.w) |
  793. GSC_SCALED_HEIGHT(buf->rect.h));
  794. gsc_write(cfg, GSC_SCALED_SIZE);
  795. /* original size */
  796. cfg = gsc_read(GSC_DSTIMG_SIZE);
  797. cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | GSC_DSTIMG_WIDTH_MASK);
  798. cfg |= GSC_DSTIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
  799. GSC_DSTIMG_HEIGHT(buf->buf.height);
  800. gsc_write(cfg, GSC_DSTIMG_SIZE);
  801. cfg = gsc_read(GSC_OUT_CON);
  802. cfg &= ~GSC_OUT_RGB_TYPE_MASK;
  803. if (buf->rect.w >= GSC_WIDTH_ITU_709)
  804. if (sc->range)
  805. cfg |= GSC_OUT_RGB_HD_WIDE;
  806. else
  807. cfg |= GSC_OUT_RGB_HD_NARROW;
  808. else
  809. if (sc->range)
  810. cfg |= GSC_OUT_RGB_SD_WIDE;
  811. else
  812. cfg |= GSC_OUT_RGB_SD_NARROW;
  813. gsc_write(cfg, GSC_OUT_CON);
  814. }
  815. static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
  816. {
  817. u32 cfg, i, buf_num = GSC_REG_SZ;
  818. u32 mask = 0x00000001;
  819. cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
  820. for (i = 0; i < GSC_REG_SZ; i++)
  821. if (cfg & (mask << i))
  822. buf_num--;
  823. DRM_DEV_DEBUG_KMS(ctx->dev, "buf_num[%d]\n", buf_num);
  824. return buf_num;
  825. }
  826. static void gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
  827. bool enqueue)
  828. {
  829. bool masked = !enqueue;
  830. u32 cfg;
  831. u32 mask = 0x00000001 << buf_id;
  832. /* mask register set */
  833. cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
  834. /* sequence id */
  835. cfg &= ~mask;
  836. cfg |= masked << buf_id;
  837. gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
  838. gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
  839. gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
  840. /* interrupt enable */
  841. if (enqueue && gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
  842. gsc_handle_irq(ctx, true, false, true);
  843. /* interrupt disable */
  844. if (!enqueue && gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
  845. gsc_handle_irq(ctx, false, false, true);
  846. }
  847. static void gsc_dst_set_addr(struct gsc_context *ctx,
  848. u32 buf_id, struct exynos_drm_ipp_buffer *buf)
  849. {
  850. /* address register set */
  851. gsc_write(buf->dma_addr[0], GSC_OUT_BASE_ADDR_Y(buf_id));
  852. gsc_write(buf->dma_addr[1], GSC_OUT_BASE_ADDR_CB(buf_id));
  853. gsc_write(buf->dma_addr[2], GSC_OUT_BASE_ADDR_CR(buf_id));
  854. gsc_dst_set_buf_seq(ctx, buf_id, true);
  855. }
  856. static int gsc_get_src_buf_index(struct gsc_context *ctx)
  857. {
  858. u32 cfg, curr_index, i;
  859. u32 buf_id = GSC_MAX_SRC;
  860. DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
  861. cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
  862. curr_index = GSC_IN_CURR_GET_INDEX(cfg);
  863. for (i = curr_index; i < GSC_MAX_SRC; i++) {
  864. if (!((cfg >> i) & 0x1)) {
  865. buf_id = i;
  866. break;
  867. }
  868. }
  869. DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
  870. curr_index, buf_id);
  871. if (buf_id == GSC_MAX_SRC) {
  872. DRM_DEV_ERROR(ctx->dev, "failed to get in buffer index.\n");
  873. return -EINVAL;
  874. }
  875. gsc_src_set_buf_seq(ctx, buf_id, false);
  876. return buf_id;
  877. }
  878. static int gsc_get_dst_buf_index(struct gsc_context *ctx)
  879. {
  880. u32 cfg, curr_index, i;
  881. u32 buf_id = GSC_MAX_DST;
  882. DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
  883. cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
  884. curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
  885. for (i = curr_index; i < GSC_MAX_DST; i++) {
  886. if (!((cfg >> i) & 0x1)) {
  887. buf_id = i;
  888. break;
  889. }
  890. }
  891. if (buf_id == GSC_MAX_DST) {
  892. DRM_DEV_ERROR(ctx->dev, "failed to get out buffer index.\n");
  893. return -EINVAL;
  894. }
  895. gsc_dst_set_buf_seq(ctx, buf_id, false);
  896. DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
  897. curr_index, buf_id);
  898. return buf_id;
  899. }
  900. static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
  901. {
  902. struct gsc_context *ctx = dev_id;
  903. u32 status;
  904. int err = 0;
  905. DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
  906. status = gsc_read(GSC_IRQ);
  907. if (status & GSC_IRQ_STATUS_OR_IRQ) {
  908. dev_err(ctx->dev, "occurred overflow at %d, status 0x%x.\n",
  909. ctx->id, status);
  910. err = -EINVAL;
  911. }
  912. if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
  913. int src_buf_id, dst_buf_id;
  914. dev_dbg(ctx->dev, "occurred frame done at %d, status 0x%x.\n",
  915. ctx->id, status);
  916. src_buf_id = gsc_get_src_buf_index(ctx);
  917. dst_buf_id = gsc_get_dst_buf_index(ctx);
  918. DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id_src[%d]buf_id_dst[%d]\n",
  919. src_buf_id, dst_buf_id);
  920. if (src_buf_id < 0 || dst_buf_id < 0)
  921. err = -EINVAL;
  922. }
  923. if (ctx->task) {
  924. struct exynos_drm_ipp_task *task = ctx->task;
  925. ctx->task = NULL;
  926. pm_runtime_mark_last_busy(ctx->dev);
  927. pm_runtime_put_autosuspend(ctx->dev);
  928. exynos_drm_ipp_task_done(task, err);
  929. }
  930. return IRQ_HANDLED;
  931. }
  932. static int gsc_reset(struct gsc_context *ctx)
  933. {
  934. struct gsc_scaler *sc = &ctx->sc;
  935. int ret;
  936. /* reset h/w block */
  937. ret = gsc_sw_reset(ctx);
  938. if (ret < 0) {
  939. dev_err(ctx->dev, "failed to reset hardware.\n");
  940. return ret;
  941. }
  942. /* scaler setting */
  943. memset(&ctx->sc, 0x0, sizeof(ctx->sc));
  944. sc->range = true;
  945. return 0;
  946. }
  947. static void gsc_start(struct gsc_context *ctx)
  948. {
  949. u32 cfg;
  950. gsc_handle_irq(ctx, true, false, true);
  951. /* enable one shot */
  952. cfg = gsc_read(GSC_ENABLE);
  953. cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
  954. GSC_ENABLE_CLK_GATE_MODE_MASK);
  955. cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
  956. gsc_write(cfg, GSC_ENABLE);
  957. /* src dma memory */
  958. cfg = gsc_read(GSC_IN_CON);
  959. cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
  960. cfg |= GSC_IN_PATH_MEMORY;
  961. gsc_write(cfg, GSC_IN_CON);
  962. /* dst dma memory */
  963. cfg = gsc_read(GSC_OUT_CON);
  964. cfg |= GSC_OUT_PATH_MEMORY;
  965. gsc_write(cfg, GSC_OUT_CON);
  966. gsc_set_scaler(ctx, &ctx->sc);
  967. cfg = gsc_read(GSC_ENABLE);
  968. cfg |= GSC_ENABLE_ON;
  969. gsc_write(cfg, GSC_ENABLE);
  970. }
  971. static int gsc_commit(struct exynos_drm_ipp *ipp,
  972. struct exynos_drm_ipp_task *task)
  973. {
  974. struct gsc_context *ctx = container_of(ipp, struct gsc_context, ipp);
  975. int ret;
  976. pm_runtime_get_sync(ctx->dev);
  977. ctx->task = task;
  978. ret = gsc_reset(ctx);
  979. if (ret) {
  980. pm_runtime_put_autosuspend(ctx->dev);
  981. ctx->task = NULL;
  982. return ret;
  983. }
  984. gsc_src_set_fmt(ctx, task->src.buf.fourcc, task->src.buf.modifier);
  985. gsc_src_set_transf(ctx, task->transform.rotation);
  986. gsc_src_set_size(ctx, &task->src);
  987. gsc_src_set_addr(ctx, 0, &task->src);
  988. gsc_dst_set_fmt(ctx, task->dst.buf.fourcc, task->dst.buf.modifier);
  989. gsc_dst_set_size(ctx, &task->dst);
  990. gsc_dst_set_addr(ctx, 0, &task->dst);
  991. gsc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect);
  992. gsc_start(ctx);
  993. return 0;
  994. }
  995. static void gsc_abort(struct exynos_drm_ipp *ipp,
  996. struct exynos_drm_ipp_task *task)
  997. {
  998. struct gsc_context *ctx =
  999. container_of(ipp, struct gsc_context, ipp);
  1000. gsc_reset(ctx);
  1001. if (ctx->task) {
  1002. struct exynos_drm_ipp_task *task = ctx->task;
  1003. ctx->task = NULL;
  1004. pm_runtime_mark_last_busy(ctx->dev);
  1005. pm_runtime_put_autosuspend(ctx->dev);
  1006. exynos_drm_ipp_task_done(task, -EIO);
  1007. }
  1008. }
  1009. static struct exynos_drm_ipp_funcs ipp_funcs = {
  1010. .commit = gsc_commit,
  1011. .abort = gsc_abort,
  1012. };
  1013. static int gsc_bind(struct device *dev, struct device *master, void *data)
  1014. {
  1015. struct gsc_context *ctx = dev_get_drvdata(dev);
  1016. struct drm_device *drm_dev = data;
  1017. struct exynos_drm_ipp *ipp = &ctx->ipp;
  1018. ctx->drm_dev = drm_dev;
  1019. ctx->drm_dev = drm_dev;
  1020. exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
  1021. exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
  1022. DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
  1023. DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
  1024. ctx->formats, ctx->num_formats, "gsc");
  1025. dev_info(dev, "The exynos gscaler has been probed successfully\n");
  1026. return 0;
  1027. }
  1028. static void gsc_unbind(struct device *dev, struct device *master,
  1029. void *data)
  1030. {
  1031. struct gsc_context *ctx = dev_get_drvdata(dev);
  1032. struct drm_device *drm_dev = data;
  1033. struct exynos_drm_ipp *ipp = &ctx->ipp;
  1034. exynos_drm_ipp_unregister(dev, ipp);
  1035. exynos_drm_unregister_dma(drm_dev, dev, &ctx->dma_priv);
  1036. }
  1037. static const struct component_ops gsc_component_ops = {
  1038. .bind = gsc_bind,
  1039. .unbind = gsc_unbind,
  1040. };
  1041. static const unsigned int gsc_formats[] = {
  1042. DRM_FORMAT_ARGB8888,
  1043. DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_BGRX8888,
  1044. DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61,
  1045. DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
  1046. DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422,
  1047. };
  1048. static const unsigned int gsc_tiled_formats[] = {
  1049. DRM_FORMAT_NV12, DRM_FORMAT_NV21,
  1050. };
  1051. static int gsc_probe(struct platform_device *pdev)
  1052. {
  1053. struct device *dev = &pdev->dev;
  1054. struct gsc_driverdata *driver_data;
  1055. struct exynos_drm_ipp_formats *formats;
  1056. struct gsc_context *ctx;
  1057. struct resource *res;
  1058. int num_formats, ret, i, j;
  1059. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  1060. if (!ctx)
  1061. return -ENOMEM;
  1062. driver_data = (struct gsc_driverdata *)of_device_get_match_data(dev);
  1063. ctx->dev = dev;
  1064. ctx->num_clocks = driver_data->num_clocks;
  1065. ctx->clk_names = driver_data->clk_names;
  1066. /* construct formats/limits array */
  1067. num_formats = ARRAY_SIZE(gsc_formats) + ARRAY_SIZE(gsc_tiled_formats);
  1068. formats = devm_kcalloc(dev, num_formats, sizeof(*formats), GFP_KERNEL);
  1069. if (!formats)
  1070. return -ENOMEM;
  1071. /* linear formats */
  1072. for (i = 0; i < ARRAY_SIZE(gsc_formats); i++) {
  1073. formats[i].fourcc = gsc_formats[i];
  1074. formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
  1075. DRM_EXYNOS_IPP_FORMAT_DESTINATION;
  1076. formats[i].limits = driver_data->limits;
  1077. formats[i].num_limits = driver_data->num_limits;
  1078. }
  1079. /* tiled formats */
  1080. for (j = i, i = 0; i < ARRAY_SIZE(gsc_tiled_formats); j++, i++) {
  1081. formats[j].fourcc = gsc_tiled_formats[i];
  1082. formats[j].modifier = DRM_FORMAT_MOD_SAMSUNG_16_16_TILE;
  1083. formats[j].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
  1084. DRM_EXYNOS_IPP_FORMAT_DESTINATION;
  1085. formats[j].limits = driver_data->limits;
  1086. formats[j].num_limits = driver_data->num_limits;
  1087. }
  1088. ctx->formats = formats;
  1089. ctx->num_formats = num_formats;
  1090. /* clock control */
  1091. for (i = 0; i < ctx->num_clocks; i++) {
  1092. ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]);
  1093. if (IS_ERR(ctx->clocks[i])) {
  1094. dev_err(dev, "failed to get clock: %s\n",
  1095. ctx->clk_names[i]);
  1096. return PTR_ERR(ctx->clocks[i]);
  1097. }
  1098. }
  1099. /* resource memory */
  1100. ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1101. ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
  1102. if (IS_ERR(ctx->regs))
  1103. return PTR_ERR(ctx->regs);
  1104. /* resource irq */
  1105. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1106. if (!res) {
  1107. dev_err(dev, "failed to request irq resource.\n");
  1108. return -ENOENT;
  1109. }
  1110. ctx->irq = res->start;
  1111. ret = devm_request_irq(dev, ctx->irq, gsc_irq_handler, 0,
  1112. dev_name(dev), ctx);
  1113. if (ret < 0) {
  1114. dev_err(dev, "failed to request irq.\n");
  1115. return ret;
  1116. }
  1117. /* context initailization */
  1118. ctx->id = pdev->id;
  1119. platform_set_drvdata(pdev, ctx);
  1120. pm_runtime_use_autosuspend(dev);
  1121. pm_runtime_set_autosuspend_delay(dev, GSC_AUTOSUSPEND_DELAY);
  1122. pm_runtime_enable(dev);
  1123. ret = component_add(dev, &gsc_component_ops);
  1124. if (ret)
  1125. goto err_pm_dis;
  1126. dev_info(dev, "drm gsc registered successfully.\n");
  1127. return 0;
  1128. err_pm_dis:
  1129. pm_runtime_dont_use_autosuspend(dev);
  1130. pm_runtime_disable(dev);
  1131. return ret;
  1132. }
  1133. static int gsc_remove(struct platform_device *pdev)
  1134. {
  1135. struct device *dev = &pdev->dev;
  1136. component_del(dev, &gsc_component_ops);
  1137. pm_runtime_dont_use_autosuspend(dev);
  1138. pm_runtime_disable(dev);
  1139. return 0;
  1140. }
  1141. static int __maybe_unused gsc_runtime_suspend(struct device *dev)
  1142. {
  1143. struct gsc_context *ctx = get_gsc_context(dev);
  1144. int i;
  1145. DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
  1146. for (i = ctx->num_clocks - 1; i >= 0; i--)
  1147. clk_disable_unprepare(ctx->clocks[i]);
  1148. return 0;
  1149. }
  1150. static int __maybe_unused gsc_runtime_resume(struct device *dev)
  1151. {
  1152. struct gsc_context *ctx = get_gsc_context(dev);
  1153. int i, ret;
  1154. DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
  1155. for (i = 0; i < ctx->num_clocks; i++) {
  1156. ret = clk_prepare_enable(ctx->clocks[i]);
  1157. if (ret) {
  1158. while (--i > 0)
  1159. clk_disable_unprepare(ctx->clocks[i]);
  1160. return ret;
  1161. }
  1162. }
  1163. return 0;
  1164. }
  1165. static const struct dev_pm_ops gsc_pm_ops = {
  1166. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1167. pm_runtime_force_resume)
  1168. SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
  1169. };
  1170. static const struct drm_exynos_ipp_limit gsc_5250_limits[] = {
  1171. { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
  1172. { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
  1173. { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2048 }, .v = { 16, 2048 }) },
  1174. { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
  1175. .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
  1176. };
  1177. static const struct drm_exynos_ipp_limit gsc_5420_limits[] = {
  1178. { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
  1179. { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
  1180. { IPP_SIZE_LIMIT(ROTATED, .h = { 16, 2016 }, .v = { 8, 2016 }) },
  1181. { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
  1182. .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
  1183. };
  1184. static const struct drm_exynos_ipp_limit gsc_5433_limits[] = {
  1185. { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191, 16 }, .v = { 16, 8191, 2 }) },
  1186. { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) },
  1187. { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2047 }, .v = { 8, 8191 }) },
  1188. { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
  1189. .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
  1190. };
  1191. static struct gsc_driverdata gsc_exynos5250_drvdata = {
  1192. .clk_names = {"gscl"},
  1193. .num_clocks = 1,
  1194. .limits = gsc_5250_limits,
  1195. .num_limits = ARRAY_SIZE(gsc_5250_limits),
  1196. };
  1197. static struct gsc_driverdata gsc_exynos5420_drvdata = {
  1198. .clk_names = {"gscl"},
  1199. .num_clocks = 1,
  1200. .limits = gsc_5420_limits,
  1201. .num_limits = ARRAY_SIZE(gsc_5420_limits),
  1202. };
  1203. static struct gsc_driverdata gsc_exynos5433_drvdata = {
  1204. .clk_names = {"pclk", "aclk", "aclk_xiu", "aclk_gsclbend"},
  1205. .num_clocks = 4,
  1206. .limits = gsc_5433_limits,
  1207. .num_limits = ARRAY_SIZE(gsc_5433_limits),
  1208. };
  1209. static const struct of_device_id exynos_drm_gsc_of_match[] = {
  1210. {
  1211. .compatible = "samsung,exynos5-gsc",
  1212. .data = &gsc_exynos5250_drvdata,
  1213. }, {
  1214. .compatible = "samsung,exynos5250-gsc",
  1215. .data = &gsc_exynos5250_drvdata,
  1216. }, {
  1217. .compatible = "samsung,exynos5420-gsc",
  1218. .data = &gsc_exynos5420_drvdata,
  1219. }, {
  1220. .compatible = "samsung,exynos5433-gsc",
  1221. .data = &gsc_exynos5433_drvdata,
  1222. }, {
  1223. },
  1224. };
  1225. MODULE_DEVICE_TABLE(of, exynos_drm_gsc_of_match);
  1226. struct platform_driver gsc_driver = {
  1227. .probe = gsc_probe,
  1228. .remove = gsc_remove,
  1229. .driver = {
  1230. .name = "exynos-drm-gsc",
  1231. .owner = THIS_MODULE,
  1232. .pm = &gsc_pm_ops,
  1233. .of_match_table = of_match_ptr(exynos_drm_gsc_of_match),
  1234. },
  1235. };