exynos_drm_fimd.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* exynos_drm_fimd.c
  3. *
  4. * Copyright (C) 2011 Samsung Electronics Co.Ltd
  5. * Authors:
  6. * Joonyoung Shim <jy0922.shim@samsung.com>
  7. * Inki Dae <inki.dae@samsung.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/component.h>
  11. #include <linux/kernel.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <linux/of.h>
  14. #include <linux/of_device.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/regmap.h>
  18. #include <video/of_display_timing.h>
  19. #include <video/of_videomode.h>
  20. #include <video/samsung_fimd.h>
  21. #include <drm/drm_fourcc.h>
  22. #include <drm/drm_vblank.h>
  23. #include <drm/exynos_drm.h>
  24. #include "exynos_drm_crtc.h"
  25. #include "exynos_drm_drv.h"
  26. #include "exynos_drm_fb.h"
  27. #include "exynos_drm_plane.h"
  28. /*
  29. * FIMD stands for Fully Interactive Mobile Display and
  30. * as a display controller, it transfers contents drawn on memory
  31. * to a LCD Panel through Display Interfaces such as RGB or
  32. * CPU Interface.
  33. */
  34. #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  35. /* position control register for hardware window 0, 2 ~ 4.*/
  36. #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
  37. #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
  38. /*
  39. * size control register for hardware windows 0 and alpha control register
  40. * for hardware windows 1 ~ 4
  41. */
  42. #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
  43. /* size control register for hardware windows 1 ~ 2. */
  44. #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
  45. #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
  46. #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
  47. #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
  48. #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
  49. #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
  50. #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
  51. /* color key control register for hardware window 1 ~ 4. */
  52. #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  53. /* color key value register for hardware window 1 ~ 4. */
  54. #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  55. /* I80 trigger control register */
  56. #define TRIGCON 0x1A4
  57. #define TRGMODE_ENABLE (1 << 0)
  58. #define SWTRGCMD_ENABLE (1 << 1)
  59. /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
  60. #define HWTRGEN_ENABLE (1 << 3)
  61. #define HWTRGMASK_ENABLE (1 << 4)
  62. /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
  63. #define HWTRIGEN_PER_ENABLE (1 << 31)
  64. /* display mode change control register except exynos4 */
  65. #define VIDOUT_CON 0x000
  66. #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
  67. /* I80 interface control for main LDI register */
  68. #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
  69. #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
  70. #define LCD_CS_SETUP(x) ((x) << 16)
  71. #define LCD_WR_SETUP(x) ((x) << 12)
  72. #define LCD_WR_ACTIVE(x) ((x) << 8)
  73. #define LCD_WR_HOLD(x) ((x) << 4)
  74. #define I80IFEN_ENABLE (1 << 0)
  75. /* FIMD has totally five hardware windows. */
  76. #define WINDOWS_NR 5
  77. /* HW trigger flag on i80 panel. */
  78. #define I80_HW_TRG (1 << 1)
  79. struct fimd_driver_data {
  80. unsigned int timing_base;
  81. unsigned int lcdblk_offset;
  82. unsigned int lcdblk_vt_shift;
  83. unsigned int lcdblk_bypass_shift;
  84. unsigned int lcdblk_mic_bypass_shift;
  85. unsigned int trg_type;
  86. unsigned int has_shadowcon:1;
  87. unsigned int has_clksel:1;
  88. unsigned int has_limited_fmt:1;
  89. unsigned int has_vidoutcon:1;
  90. unsigned int has_vtsel:1;
  91. unsigned int has_mic_bypass:1;
  92. unsigned int has_dp_clk:1;
  93. unsigned int has_hw_trigger:1;
  94. unsigned int has_trigger_per_te:1;
  95. };
  96. static struct fimd_driver_data s3c64xx_fimd_driver_data = {
  97. .timing_base = 0x0,
  98. .has_clksel = 1,
  99. .has_limited_fmt = 1,
  100. };
  101. static struct fimd_driver_data s5pv210_fimd_driver_data = {
  102. .timing_base = 0x0,
  103. .has_shadowcon = 1,
  104. .has_clksel = 1,
  105. };
  106. static struct fimd_driver_data exynos3_fimd_driver_data = {
  107. .timing_base = 0x20000,
  108. .lcdblk_offset = 0x210,
  109. .lcdblk_bypass_shift = 1,
  110. .has_shadowcon = 1,
  111. .has_vidoutcon = 1,
  112. };
  113. static struct fimd_driver_data exynos4_fimd_driver_data = {
  114. .timing_base = 0x0,
  115. .lcdblk_offset = 0x210,
  116. .lcdblk_vt_shift = 10,
  117. .lcdblk_bypass_shift = 1,
  118. .has_shadowcon = 1,
  119. .has_vtsel = 1,
  120. };
  121. static struct fimd_driver_data exynos5_fimd_driver_data = {
  122. .timing_base = 0x20000,
  123. .lcdblk_offset = 0x214,
  124. .lcdblk_vt_shift = 24,
  125. .lcdblk_bypass_shift = 15,
  126. .has_shadowcon = 1,
  127. .has_vidoutcon = 1,
  128. .has_vtsel = 1,
  129. .has_dp_clk = 1,
  130. };
  131. static struct fimd_driver_data exynos5420_fimd_driver_data = {
  132. .timing_base = 0x20000,
  133. .lcdblk_offset = 0x214,
  134. .lcdblk_vt_shift = 24,
  135. .lcdblk_bypass_shift = 15,
  136. .lcdblk_mic_bypass_shift = 11,
  137. .has_shadowcon = 1,
  138. .has_vidoutcon = 1,
  139. .has_vtsel = 1,
  140. .has_mic_bypass = 1,
  141. .has_dp_clk = 1,
  142. };
  143. struct fimd_context {
  144. struct device *dev;
  145. struct drm_device *drm_dev;
  146. void *dma_priv;
  147. struct exynos_drm_crtc *crtc;
  148. struct exynos_drm_plane planes[WINDOWS_NR];
  149. struct exynos_drm_plane_config configs[WINDOWS_NR];
  150. struct clk *bus_clk;
  151. struct clk *lcd_clk;
  152. void __iomem *regs;
  153. struct regmap *sysreg;
  154. unsigned long irq_flags;
  155. u32 vidcon0;
  156. u32 vidcon1;
  157. u32 vidout_con;
  158. u32 i80ifcon;
  159. bool i80_if;
  160. bool suspended;
  161. wait_queue_head_t wait_vsync_queue;
  162. atomic_t wait_vsync_event;
  163. atomic_t win_updated;
  164. atomic_t triggering;
  165. u32 clkdiv;
  166. const struct fimd_driver_data *driver_data;
  167. struct drm_encoder *encoder;
  168. struct exynos_drm_clk dp_clk;
  169. };
  170. static const struct of_device_id fimd_driver_dt_match[] = {
  171. { .compatible = "samsung,s3c6400-fimd",
  172. .data = &s3c64xx_fimd_driver_data },
  173. { .compatible = "samsung,s5pv210-fimd",
  174. .data = &s5pv210_fimd_driver_data },
  175. { .compatible = "samsung,exynos3250-fimd",
  176. .data = &exynos3_fimd_driver_data },
  177. { .compatible = "samsung,exynos4210-fimd",
  178. .data = &exynos4_fimd_driver_data },
  179. { .compatible = "samsung,exynos5250-fimd",
  180. .data = &exynos5_fimd_driver_data },
  181. { .compatible = "samsung,exynos5420-fimd",
  182. .data = &exynos5420_fimd_driver_data },
  183. {},
  184. };
  185. MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
  186. static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
  187. DRM_PLANE_TYPE_PRIMARY,
  188. DRM_PLANE_TYPE_OVERLAY,
  189. DRM_PLANE_TYPE_OVERLAY,
  190. DRM_PLANE_TYPE_OVERLAY,
  191. DRM_PLANE_TYPE_CURSOR,
  192. };
  193. static const uint32_t fimd_formats[] = {
  194. DRM_FORMAT_C8,
  195. DRM_FORMAT_XRGB1555,
  196. DRM_FORMAT_RGB565,
  197. DRM_FORMAT_XRGB8888,
  198. DRM_FORMAT_ARGB8888,
  199. };
  200. static const unsigned int capabilities[WINDOWS_NR] = {
  201. 0,
  202. EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  203. EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  204. EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  205. EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  206. };
  207. static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
  208. u32 val)
  209. {
  210. val = (val & mask) | (readl(ctx->regs + reg) & ~mask);
  211. writel(val, ctx->regs + reg);
  212. }
  213. static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
  214. {
  215. struct fimd_context *ctx = crtc->ctx;
  216. u32 val;
  217. if (ctx->suspended)
  218. return -EPERM;
  219. if (!test_and_set_bit(0, &ctx->irq_flags)) {
  220. val = readl(ctx->regs + VIDINTCON0);
  221. val |= VIDINTCON0_INT_ENABLE;
  222. if (ctx->i80_if) {
  223. val |= VIDINTCON0_INT_I80IFDONE;
  224. val |= VIDINTCON0_INT_SYSMAINCON;
  225. val &= ~VIDINTCON0_INT_SYSSUBCON;
  226. } else {
  227. val |= VIDINTCON0_INT_FRAME;
  228. val &= ~VIDINTCON0_FRAMESEL0_MASK;
  229. val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
  230. val &= ~VIDINTCON0_FRAMESEL1_MASK;
  231. val |= VIDINTCON0_FRAMESEL1_NONE;
  232. }
  233. writel(val, ctx->regs + VIDINTCON0);
  234. }
  235. return 0;
  236. }
  237. static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
  238. {
  239. struct fimd_context *ctx = crtc->ctx;
  240. u32 val;
  241. if (ctx->suspended)
  242. return;
  243. if (test_and_clear_bit(0, &ctx->irq_flags)) {
  244. val = readl(ctx->regs + VIDINTCON0);
  245. val &= ~VIDINTCON0_INT_ENABLE;
  246. if (ctx->i80_if) {
  247. val &= ~VIDINTCON0_INT_I80IFDONE;
  248. val &= ~VIDINTCON0_INT_SYSMAINCON;
  249. val &= ~VIDINTCON0_INT_SYSSUBCON;
  250. } else
  251. val &= ~VIDINTCON0_INT_FRAME;
  252. writel(val, ctx->regs + VIDINTCON0);
  253. }
  254. }
  255. static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
  256. {
  257. struct fimd_context *ctx = crtc->ctx;
  258. if (ctx->suspended)
  259. return;
  260. atomic_set(&ctx->wait_vsync_event, 1);
  261. /*
  262. * wait for FIMD to signal VSYNC interrupt or return after
  263. * timeout which is set to 50ms (refresh rate of 20).
  264. */
  265. if (!wait_event_timeout(ctx->wait_vsync_queue,
  266. !atomic_read(&ctx->wait_vsync_event),
  267. HZ/20))
  268. DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
  269. }
  270. static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
  271. bool enable)
  272. {
  273. u32 val = readl(ctx->regs + WINCON(win));
  274. if (enable)
  275. val |= WINCONx_ENWIN;
  276. else
  277. val &= ~WINCONx_ENWIN;
  278. writel(val, ctx->regs + WINCON(win));
  279. }
  280. static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
  281. unsigned int win,
  282. bool enable)
  283. {
  284. u32 val = readl(ctx->regs + SHADOWCON);
  285. if (enable)
  286. val |= SHADOWCON_CHx_ENABLE(win);
  287. else
  288. val &= ~SHADOWCON_CHx_ENABLE(win);
  289. writel(val, ctx->regs + SHADOWCON);
  290. }
  291. static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
  292. {
  293. struct fimd_context *ctx = crtc->ctx;
  294. unsigned int win, ch_enabled = 0;
  295. /* Hardware is in unknown state, so ensure it gets enabled properly */
  296. pm_runtime_get_sync(ctx->dev);
  297. clk_prepare_enable(ctx->bus_clk);
  298. clk_prepare_enable(ctx->lcd_clk);
  299. /* Check if any channel is enabled. */
  300. for (win = 0; win < WINDOWS_NR; win++) {
  301. u32 val = readl(ctx->regs + WINCON(win));
  302. if (val & WINCONx_ENWIN) {
  303. fimd_enable_video_output(ctx, win, false);
  304. if (ctx->driver_data->has_shadowcon)
  305. fimd_enable_shadow_channel_path(ctx, win,
  306. false);
  307. ch_enabled = 1;
  308. }
  309. }
  310. /* Wait for vsync, as disable channel takes effect at next vsync */
  311. if (ch_enabled) {
  312. ctx->suspended = false;
  313. fimd_enable_vblank(ctx->crtc);
  314. fimd_wait_for_vblank(ctx->crtc);
  315. fimd_disable_vblank(ctx->crtc);
  316. ctx->suspended = true;
  317. }
  318. clk_disable_unprepare(ctx->lcd_clk);
  319. clk_disable_unprepare(ctx->bus_clk);
  320. pm_runtime_put(ctx->dev);
  321. }
  322. static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
  323. struct drm_crtc_state *state)
  324. {
  325. struct drm_display_mode *mode = &state->adjusted_mode;
  326. struct fimd_context *ctx = crtc->ctx;
  327. unsigned long ideal_clk, lcd_rate;
  328. u32 clkdiv;
  329. if (mode->clock == 0) {
  330. DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n");
  331. return -EINVAL;
  332. }
  333. ideal_clk = mode->clock * 1000;
  334. if (ctx->i80_if) {
  335. /*
  336. * The frame done interrupt should be occurred prior to the
  337. * next TE signal.
  338. */
  339. ideal_clk *= 2;
  340. }
  341. lcd_rate = clk_get_rate(ctx->lcd_clk);
  342. if (2 * lcd_rate < ideal_clk) {
  343. DRM_DEV_ERROR(ctx->dev,
  344. "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
  345. lcd_rate, ideal_clk);
  346. return -EINVAL;
  347. }
  348. /* Find the clock divider value that gets us closest to ideal_clk */
  349. clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
  350. if (clkdiv >= 0x200) {
  351. DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n",
  352. ideal_clk);
  353. return -EINVAL;
  354. }
  355. ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
  356. return 0;
  357. }
  358. static void fimd_setup_trigger(struct fimd_context *ctx)
  359. {
  360. void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
  361. u32 trg_type = ctx->driver_data->trg_type;
  362. u32 val = readl(timing_base + TRIGCON);
  363. val &= ~(TRGMODE_ENABLE);
  364. if (trg_type == I80_HW_TRG) {
  365. if (ctx->driver_data->has_hw_trigger)
  366. val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
  367. if (ctx->driver_data->has_trigger_per_te)
  368. val |= HWTRIGEN_PER_ENABLE;
  369. } else {
  370. val |= TRGMODE_ENABLE;
  371. }
  372. writel(val, timing_base + TRIGCON);
  373. }
  374. static void fimd_commit(struct exynos_drm_crtc *crtc)
  375. {
  376. struct fimd_context *ctx = crtc->ctx;
  377. struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
  378. const struct fimd_driver_data *driver_data = ctx->driver_data;
  379. void *timing_base = ctx->regs + driver_data->timing_base;
  380. u32 val;
  381. if (ctx->suspended)
  382. return;
  383. /* nothing to do if we haven't set the mode yet */
  384. if (mode->htotal == 0 || mode->vtotal == 0)
  385. return;
  386. if (ctx->i80_if) {
  387. val = ctx->i80ifcon | I80IFEN_ENABLE;
  388. writel(val, timing_base + I80IFCONFAx(0));
  389. /* disable auto frame rate */
  390. writel(0, timing_base + I80IFCONFBx(0));
  391. /* set video type selection to I80 interface */
  392. if (driver_data->has_vtsel && ctx->sysreg &&
  393. regmap_update_bits(ctx->sysreg,
  394. driver_data->lcdblk_offset,
  395. 0x3 << driver_data->lcdblk_vt_shift,
  396. 0x1 << driver_data->lcdblk_vt_shift)) {
  397. DRM_DEV_ERROR(ctx->dev,
  398. "Failed to update sysreg for I80 i/f.\n");
  399. return;
  400. }
  401. } else {
  402. int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
  403. u32 vidcon1;
  404. /* setup polarity values */
  405. vidcon1 = ctx->vidcon1;
  406. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  407. vidcon1 |= VIDCON1_INV_VSYNC;
  408. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  409. vidcon1 |= VIDCON1_INV_HSYNC;
  410. writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
  411. /* setup vertical timing values. */
  412. vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  413. vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
  414. vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
  415. val = VIDTCON0_VBPD(vbpd - 1) |
  416. VIDTCON0_VFPD(vfpd - 1) |
  417. VIDTCON0_VSPW(vsync_len - 1);
  418. writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
  419. /* setup horizontal timing values. */
  420. hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  421. hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
  422. hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
  423. val = VIDTCON1_HBPD(hbpd - 1) |
  424. VIDTCON1_HFPD(hfpd - 1) |
  425. VIDTCON1_HSPW(hsync_len - 1);
  426. writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
  427. }
  428. if (driver_data->has_vidoutcon)
  429. writel(ctx->vidout_con, timing_base + VIDOUT_CON);
  430. /* set bypass selection */
  431. if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
  432. driver_data->lcdblk_offset,
  433. 0x1 << driver_data->lcdblk_bypass_shift,
  434. 0x1 << driver_data->lcdblk_bypass_shift)) {
  435. DRM_DEV_ERROR(ctx->dev,
  436. "Failed to update sysreg for bypass setting.\n");
  437. return;
  438. }
  439. /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
  440. * bit should be cleared.
  441. */
  442. if (driver_data->has_mic_bypass && ctx->sysreg &&
  443. regmap_update_bits(ctx->sysreg,
  444. driver_data->lcdblk_offset,
  445. 0x1 << driver_data->lcdblk_mic_bypass_shift,
  446. 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
  447. DRM_DEV_ERROR(ctx->dev,
  448. "Failed to update sysreg for bypass mic.\n");
  449. return;
  450. }
  451. /* setup horizontal and vertical display size. */
  452. val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
  453. VIDTCON2_HOZVAL(mode->hdisplay - 1) |
  454. VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
  455. VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
  456. writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
  457. fimd_setup_trigger(ctx);
  458. /*
  459. * fields of register with prefix '_F' would be updated
  460. * at vsync(same as dma start)
  461. */
  462. val = ctx->vidcon0;
  463. val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
  464. if (ctx->driver_data->has_clksel)
  465. val |= VIDCON0_CLKSEL_LCD;
  466. if (ctx->clkdiv > 1)
  467. val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
  468. writel(val, ctx->regs + VIDCON0);
  469. }
  470. static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
  471. unsigned int alpha, unsigned int pixel_alpha)
  472. {
  473. u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
  474. u32 val = 0;
  475. switch (pixel_alpha) {
  476. case DRM_MODE_BLEND_PIXEL_NONE:
  477. case DRM_MODE_BLEND_COVERAGE:
  478. val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A);
  479. val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
  480. break;
  481. case DRM_MODE_BLEND_PREMULTI:
  482. default:
  483. if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
  484. val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0);
  485. val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
  486. } else {
  487. val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE);
  488. val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
  489. }
  490. break;
  491. }
  492. fimd_set_bits(ctx, BLENDEQx(win), mask, val);
  493. }
  494. static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
  495. unsigned int alpha, unsigned int pixel_alpha)
  496. {
  497. u32 win_alpha_l = (alpha >> 8) & 0xf;
  498. u32 win_alpha_h = alpha >> 12;
  499. u32 val = 0;
  500. switch (pixel_alpha) {
  501. case DRM_MODE_BLEND_PIXEL_NONE:
  502. break;
  503. case DRM_MODE_BLEND_COVERAGE:
  504. case DRM_MODE_BLEND_PREMULTI:
  505. default:
  506. val |= WINCON1_ALPHA_SEL;
  507. val |= WINCON1_BLD_PIX;
  508. val |= WINCON1_ALPHA_MUL;
  509. break;
  510. }
  511. fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
  512. /* OSD alpha */
  513. val = VIDISD14C_ALPHA0_R(win_alpha_h) |
  514. VIDISD14C_ALPHA0_G(win_alpha_h) |
  515. VIDISD14C_ALPHA0_B(win_alpha_h) |
  516. VIDISD14C_ALPHA1_R(0x0) |
  517. VIDISD14C_ALPHA1_G(0x0) |
  518. VIDISD14C_ALPHA1_B(0x0);
  519. writel(val, ctx->regs + VIDOSD_C(win));
  520. val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) |
  521. VIDW_ALPHA_B(win_alpha_l);
  522. writel(val, ctx->regs + VIDWnALPHA0(win));
  523. val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
  524. VIDW_ALPHA_B(0x0);
  525. writel(val, ctx->regs + VIDWnALPHA1(win));
  526. fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK,
  527. BLENDCON_NEW_8BIT_ALPHA_VALUE);
  528. }
  529. static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
  530. struct drm_framebuffer *fb, int width)
  531. {
  532. struct exynos_drm_plane plane = ctx->planes[win];
  533. struct exynos_drm_plane_state *state =
  534. to_exynos_plane_state(plane.base.state);
  535. uint32_t pixel_format = fb->format->format;
  536. unsigned int alpha = state->base.alpha;
  537. u32 val = WINCONx_ENWIN;
  538. unsigned int pixel_alpha;
  539. if (fb->format->has_alpha)
  540. pixel_alpha = state->base.pixel_blend_mode;
  541. else
  542. pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
  543. /*
  544. * In case of s3c64xx, window 0 doesn't support alpha channel.
  545. * So the request format is ARGB8888 then change it to XRGB8888.
  546. */
  547. if (ctx->driver_data->has_limited_fmt && !win) {
  548. if (pixel_format == DRM_FORMAT_ARGB8888)
  549. pixel_format = DRM_FORMAT_XRGB8888;
  550. }
  551. switch (pixel_format) {
  552. case DRM_FORMAT_C8:
  553. val |= WINCON0_BPPMODE_8BPP_PALETTE;
  554. val |= WINCONx_BURSTLEN_8WORD;
  555. val |= WINCONx_BYTSWP;
  556. break;
  557. case DRM_FORMAT_XRGB1555:
  558. val |= WINCON0_BPPMODE_16BPP_1555;
  559. val |= WINCONx_HAWSWP;
  560. val |= WINCONx_BURSTLEN_16WORD;
  561. break;
  562. case DRM_FORMAT_RGB565:
  563. val |= WINCON0_BPPMODE_16BPP_565;
  564. val |= WINCONx_HAWSWP;
  565. val |= WINCONx_BURSTLEN_16WORD;
  566. break;
  567. case DRM_FORMAT_XRGB8888:
  568. val |= WINCON0_BPPMODE_24BPP_888;
  569. val |= WINCONx_WSWP;
  570. val |= WINCONx_BURSTLEN_16WORD;
  571. break;
  572. case DRM_FORMAT_ARGB8888:
  573. default:
  574. val |= WINCON1_BPPMODE_25BPP_A1888;
  575. val |= WINCONx_WSWP;
  576. val |= WINCONx_BURSTLEN_16WORD;
  577. break;
  578. }
  579. /*
  580. * Setting dma-burst to 16Word causes permanent tearing for very small
  581. * buffers, e.g. cursor buffer. Burst Mode switching which based on
  582. * plane size is not recommended as plane size varies alot towards the
  583. * end of the screen and rapid movement causes unstable DMA, but it is
  584. * still better to change dma-burst than displaying garbage.
  585. */
  586. if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
  587. val &= ~WINCONx_BURSTLEN_MASK;
  588. val |= WINCONx_BURSTLEN_4WORD;
  589. }
  590. fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
  591. /* hardware window 0 doesn't support alpha channel. */
  592. if (win != 0) {
  593. fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
  594. fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
  595. }
  596. }
  597. static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
  598. {
  599. unsigned int keycon0 = 0, keycon1 = 0;
  600. keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
  601. WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
  602. keycon1 = WxKEYCON1_COLVAL(0xffffffff);
  603. writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
  604. writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
  605. }
  606. /**
  607. * shadow_protect_win() - disable updating values from shadow registers at vsync
  608. *
  609. * @win: window to protect registers for
  610. * @protect: 1 to protect (disable updates)
  611. */
  612. static void fimd_shadow_protect_win(struct fimd_context *ctx,
  613. unsigned int win, bool protect)
  614. {
  615. u32 reg, bits, val;
  616. /*
  617. * SHADOWCON/PRTCON register is used for enabling timing.
  618. *
  619. * for example, once only width value of a register is set,
  620. * if the dma is started then fimd hardware could malfunction so
  621. * with protect window setting, the register fields with prefix '_F'
  622. * wouldn't be updated at vsync also but updated once unprotect window
  623. * is set.
  624. */
  625. if (ctx->driver_data->has_shadowcon) {
  626. reg = SHADOWCON;
  627. bits = SHADOWCON_WINx_PROTECT(win);
  628. } else {
  629. reg = PRTCON;
  630. bits = PRTCON_PROTECT;
  631. }
  632. val = readl(ctx->regs + reg);
  633. if (protect)
  634. val |= bits;
  635. else
  636. val &= ~bits;
  637. writel(val, ctx->regs + reg);
  638. }
  639. static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
  640. {
  641. struct fimd_context *ctx = crtc->ctx;
  642. int i;
  643. if (ctx->suspended)
  644. return;
  645. for (i = 0; i < WINDOWS_NR; i++)
  646. fimd_shadow_protect_win(ctx, i, true);
  647. }
  648. static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
  649. {
  650. struct fimd_context *ctx = crtc->ctx;
  651. int i;
  652. if (ctx->suspended)
  653. return;
  654. for (i = 0; i < WINDOWS_NR; i++)
  655. fimd_shadow_protect_win(ctx, i, false);
  656. exynos_crtc_handle_event(crtc);
  657. }
  658. static void fimd_update_plane(struct exynos_drm_crtc *crtc,
  659. struct exynos_drm_plane *plane)
  660. {
  661. struct exynos_drm_plane_state *state =
  662. to_exynos_plane_state(plane->base.state);
  663. struct fimd_context *ctx = crtc->ctx;
  664. struct drm_framebuffer *fb = state->base.fb;
  665. dma_addr_t dma_addr;
  666. unsigned long val, size, offset;
  667. unsigned int last_x, last_y, buf_offsize, line_size;
  668. unsigned int win = plane->index;
  669. unsigned int cpp = fb->format->cpp[0];
  670. unsigned int pitch = fb->pitches[0];
  671. if (ctx->suspended)
  672. return;
  673. offset = state->src.x * cpp;
  674. offset += state->src.y * pitch;
  675. /* buffer start address */
  676. dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
  677. val = (unsigned long)dma_addr;
  678. writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
  679. /* buffer end address */
  680. size = pitch * state->crtc.h;
  681. val = (unsigned long)(dma_addr + size);
  682. writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
  683. DRM_DEV_DEBUG_KMS(ctx->dev,
  684. "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
  685. (unsigned long)dma_addr, val, size);
  686. DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
  687. state->crtc.w, state->crtc.h);
  688. /* buffer size */
  689. buf_offsize = pitch - (state->crtc.w * cpp);
  690. line_size = state->crtc.w * cpp;
  691. val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
  692. VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
  693. VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
  694. VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
  695. writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
  696. /* OSD position */
  697. val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
  698. VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
  699. VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
  700. VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
  701. writel(val, ctx->regs + VIDOSD_A(win));
  702. last_x = state->crtc.x + state->crtc.w;
  703. if (last_x)
  704. last_x--;
  705. last_y = state->crtc.y + state->crtc.h;
  706. if (last_y)
  707. last_y--;
  708. val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
  709. VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
  710. writel(val, ctx->regs + VIDOSD_B(win));
  711. DRM_DEV_DEBUG_KMS(ctx->dev,
  712. "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
  713. state->crtc.x, state->crtc.y, last_x, last_y);
  714. /* OSD size */
  715. if (win != 3 && win != 4) {
  716. u32 offset = VIDOSD_D(win);
  717. if (win == 0)
  718. offset = VIDOSD_C(win);
  719. val = state->crtc.w * state->crtc.h;
  720. writel(val, ctx->regs + offset);
  721. DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n",
  722. (unsigned int)val);
  723. }
  724. fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
  725. /* hardware window 0 doesn't support color key. */
  726. if (win != 0)
  727. fimd_win_set_colkey(ctx, win);
  728. fimd_enable_video_output(ctx, win, true);
  729. if (ctx->driver_data->has_shadowcon)
  730. fimd_enable_shadow_channel_path(ctx, win, true);
  731. if (ctx->i80_if)
  732. atomic_set(&ctx->win_updated, 1);
  733. }
  734. static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
  735. struct exynos_drm_plane *plane)
  736. {
  737. struct fimd_context *ctx = crtc->ctx;
  738. unsigned int win = plane->index;
  739. if (ctx->suspended)
  740. return;
  741. fimd_enable_video_output(ctx, win, false);
  742. if (ctx->driver_data->has_shadowcon)
  743. fimd_enable_shadow_channel_path(ctx, win, false);
  744. }
  745. static void fimd_atomic_enable(struct exynos_drm_crtc *crtc)
  746. {
  747. struct fimd_context *ctx = crtc->ctx;
  748. if (!ctx->suspended)
  749. return;
  750. ctx->suspended = false;
  751. pm_runtime_get_sync(ctx->dev);
  752. /* if vblank was enabled status, enable it again. */
  753. if (test_and_clear_bit(0, &ctx->irq_flags))
  754. fimd_enable_vblank(ctx->crtc);
  755. fimd_commit(ctx->crtc);
  756. }
  757. static void fimd_atomic_disable(struct exynos_drm_crtc *crtc)
  758. {
  759. struct fimd_context *ctx = crtc->ctx;
  760. int i;
  761. if (ctx->suspended)
  762. return;
  763. /*
  764. * We need to make sure that all windows are disabled before we
  765. * suspend that connector. Otherwise we might try to scan from
  766. * a destroyed buffer later.
  767. */
  768. for (i = 0; i < WINDOWS_NR; i++)
  769. fimd_disable_plane(crtc, &ctx->planes[i]);
  770. fimd_enable_vblank(crtc);
  771. fimd_wait_for_vblank(crtc);
  772. fimd_disable_vblank(crtc);
  773. writel(0, ctx->regs + VIDCON0);
  774. pm_runtime_put_sync(ctx->dev);
  775. ctx->suspended = true;
  776. }
  777. static void fimd_trigger(struct device *dev)
  778. {
  779. struct fimd_context *ctx = dev_get_drvdata(dev);
  780. const struct fimd_driver_data *driver_data = ctx->driver_data;
  781. void *timing_base = ctx->regs + driver_data->timing_base;
  782. u32 reg;
  783. /*
  784. * Skips triggering if in triggering state, because multiple triggering
  785. * requests can cause panel reset.
  786. */
  787. if (atomic_read(&ctx->triggering))
  788. return;
  789. /* Enters triggering mode */
  790. atomic_set(&ctx->triggering, 1);
  791. reg = readl(timing_base + TRIGCON);
  792. reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
  793. writel(reg, timing_base + TRIGCON);
  794. /*
  795. * Exits triggering mode if vblank is not enabled yet, because when the
  796. * VIDINTCON0 register is not set, it can not exit from triggering mode.
  797. */
  798. if (!test_bit(0, &ctx->irq_flags))
  799. atomic_set(&ctx->triggering, 0);
  800. }
  801. static void fimd_te_handler(struct exynos_drm_crtc *crtc)
  802. {
  803. struct fimd_context *ctx = crtc->ctx;
  804. u32 trg_type = ctx->driver_data->trg_type;
  805. /* Checks the crtc is detached already from encoder */
  806. if (!ctx->drm_dev)
  807. return;
  808. if (trg_type == I80_HW_TRG)
  809. goto out;
  810. /*
  811. * If there is a page flip request, triggers and handles the page flip
  812. * event so that current fb can be updated into panel GRAM.
  813. */
  814. if (atomic_add_unless(&ctx->win_updated, -1, 0))
  815. fimd_trigger(ctx->dev);
  816. out:
  817. /* Wakes up vsync event queue */
  818. if (atomic_read(&ctx->wait_vsync_event)) {
  819. atomic_set(&ctx->wait_vsync_event, 0);
  820. wake_up(&ctx->wait_vsync_queue);
  821. }
  822. if (test_bit(0, &ctx->irq_flags))
  823. drm_crtc_handle_vblank(&ctx->crtc->base);
  824. }
  825. static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
  826. {
  827. struct fimd_context *ctx = container_of(clk, struct fimd_context,
  828. dp_clk);
  829. u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
  830. writel(val, ctx->regs + DP_MIE_CLKCON);
  831. }
  832. static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
  833. .atomic_enable = fimd_atomic_enable,
  834. .atomic_disable = fimd_atomic_disable,
  835. .enable_vblank = fimd_enable_vblank,
  836. .disable_vblank = fimd_disable_vblank,
  837. .atomic_begin = fimd_atomic_begin,
  838. .update_plane = fimd_update_plane,
  839. .disable_plane = fimd_disable_plane,
  840. .atomic_flush = fimd_atomic_flush,
  841. .atomic_check = fimd_atomic_check,
  842. .te_handler = fimd_te_handler,
  843. };
  844. static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
  845. {
  846. struct fimd_context *ctx = (struct fimd_context *)dev_id;
  847. u32 val, clear_bit;
  848. val = readl(ctx->regs + VIDINTCON1);
  849. clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
  850. if (val & clear_bit)
  851. writel(clear_bit, ctx->regs + VIDINTCON1);
  852. /* check the crtc is detached already from encoder */
  853. if (!ctx->drm_dev)
  854. goto out;
  855. if (!ctx->i80_if)
  856. drm_crtc_handle_vblank(&ctx->crtc->base);
  857. if (ctx->i80_if) {
  858. /* Exits triggering mode */
  859. atomic_set(&ctx->triggering, 0);
  860. } else {
  861. /* set wait vsync event to zero and wake up queue. */
  862. if (atomic_read(&ctx->wait_vsync_event)) {
  863. atomic_set(&ctx->wait_vsync_event, 0);
  864. wake_up(&ctx->wait_vsync_queue);
  865. }
  866. }
  867. out:
  868. return IRQ_HANDLED;
  869. }
  870. static int fimd_bind(struct device *dev, struct device *master, void *data)
  871. {
  872. struct fimd_context *ctx = dev_get_drvdata(dev);
  873. struct drm_device *drm_dev = data;
  874. struct exynos_drm_plane *exynos_plane;
  875. unsigned int i;
  876. int ret;
  877. ctx->drm_dev = drm_dev;
  878. for (i = 0; i < WINDOWS_NR; i++) {
  879. ctx->configs[i].pixel_formats = fimd_formats;
  880. ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
  881. ctx->configs[i].zpos = i;
  882. ctx->configs[i].type = fimd_win_types[i];
  883. ctx->configs[i].capabilities = capabilities[i];
  884. ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
  885. &ctx->configs[i]);
  886. if (ret)
  887. return ret;
  888. }
  889. exynos_plane = &ctx->planes[DEFAULT_WIN];
  890. ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
  891. EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
  892. if (IS_ERR(ctx->crtc))
  893. return PTR_ERR(ctx->crtc);
  894. if (ctx->driver_data->has_dp_clk) {
  895. ctx->dp_clk.enable = fimd_dp_clock_enable;
  896. ctx->crtc->pipe_clk = &ctx->dp_clk;
  897. }
  898. if (ctx->encoder)
  899. exynos_dpi_bind(drm_dev, ctx->encoder);
  900. if (is_drm_iommu_supported(drm_dev))
  901. fimd_clear_channels(ctx->crtc);
  902. return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
  903. }
  904. static void fimd_unbind(struct device *dev, struct device *master,
  905. void *data)
  906. {
  907. struct fimd_context *ctx = dev_get_drvdata(dev);
  908. fimd_atomic_disable(ctx->crtc);
  909. exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
  910. if (ctx->encoder)
  911. exynos_dpi_remove(ctx->encoder);
  912. }
  913. static const struct component_ops fimd_component_ops = {
  914. .bind = fimd_bind,
  915. .unbind = fimd_unbind,
  916. };
  917. static int fimd_probe(struct platform_device *pdev)
  918. {
  919. struct device *dev = &pdev->dev;
  920. struct fimd_context *ctx;
  921. struct device_node *i80_if_timings;
  922. struct resource *res;
  923. int ret;
  924. if (!dev->of_node)
  925. return -ENODEV;
  926. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  927. if (!ctx)
  928. return -ENOMEM;
  929. ctx->dev = dev;
  930. ctx->suspended = true;
  931. ctx->driver_data = of_device_get_match_data(dev);
  932. if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
  933. ctx->vidcon1 |= VIDCON1_INV_VDEN;
  934. if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
  935. ctx->vidcon1 |= VIDCON1_INV_VCLK;
  936. i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
  937. if (i80_if_timings) {
  938. u32 val;
  939. ctx->i80_if = true;
  940. if (ctx->driver_data->has_vidoutcon)
  941. ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
  942. else
  943. ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
  944. /*
  945. * The user manual describes that this "DSI_EN" bit is required
  946. * to enable I80 24-bit data interface.
  947. */
  948. ctx->vidcon0 |= VIDCON0_DSI_EN;
  949. if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
  950. val = 0;
  951. ctx->i80ifcon = LCD_CS_SETUP(val);
  952. if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
  953. val = 0;
  954. ctx->i80ifcon |= LCD_WR_SETUP(val);
  955. if (of_property_read_u32(i80_if_timings, "wr-active", &val))
  956. val = 1;
  957. ctx->i80ifcon |= LCD_WR_ACTIVE(val);
  958. if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
  959. val = 0;
  960. ctx->i80ifcon |= LCD_WR_HOLD(val);
  961. }
  962. of_node_put(i80_if_timings);
  963. ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
  964. "samsung,sysreg");
  965. if (IS_ERR(ctx->sysreg)) {
  966. dev_warn(dev, "failed to get system register.\n");
  967. ctx->sysreg = NULL;
  968. }
  969. ctx->bus_clk = devm_clk_get(dev, "fimd");
  970. if (IS_ERR(ctx->bus_clk)) {
  971. dev_err(dev, "failed to get bus clock\n");
  972. return PTR_ERR(ctx->bus_clk);
  973. }
  974. ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
  975. if (IS_ERR(ctx->lcd_clk)) {
  976. dev_err(dev, "failed to get lcd clock\n");
  977. return PTR_ERR(ctx->lcd_clk);
  978. }
  979. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  980. ctx->regs = devm_ioremap_resource(dev, res);
  981. if (IS_ERR(ctx->regs))
  982. return PTR_ERR(ctx->regs);
  983. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
  984. ctx->i80_if ? "lcd_sys" : "vsync");
  985. if (!res) {
  986. dev_err(dev, "irq request failed.\n");
  987. return -ENXIO;
  988. }
  989. ret = devm_request_irq(dev, res->start, fimd_irq_handler,
  990. 0, "drm_fimd", ctx);
  991. if (ret) {
  992. dev_err(dev, "irq request failed.\n");
  993. return ret;
  994. }
  995. init_waitqueue_head(&ctx->wait_vsync_queue);
  996. atomic_set(&ctx->wait_vsync_event, 0);
  997. platform_set_drvdata(pdev, ctx);
  998. ctx->encoder = exynos_dpi_probe(dev);
  999. if (IS_ERR(ctx->encoder))
  1000. return PTR_ERR(ctx->encoder);
  1001. pm_runtime_enable(dev);
  1002. ret = component_add(dev, &fimd_component_ops);
  1003. if (ret)
  1004. goto err_disable_pm_runtime;
  1005. return ret;
  1006. err_disable_pm_runtime:
  1007. pm_runtime_disable(dev);
  1008. return ret;
  1009. }
  1010. static int fimd_remove(struct platform_device *pdev)
  1011. {
  1012. pm_runtime_disable(&pdev->dev);
  1013. component_del(&pdev->dev, &fimd_component_ops);
  1014. return 0;
  1015. }
  1016. #ifdef CONFIG_PM
  1017. static int exynos_fimd_suspend(struct device *dev)
  1018. {
  1019. struct fimd_context *ctx = dev_get_drvdata(dev);
  1020. clk_disable_unprepare(ctx->lcd_clk);
  1021. clk_disable_unprepare(ctx->bus_clk);
  1022. return 0;
  1023. }
  1024. static int exynos_fimd_resume(struct device *dev)
  1025. {
  1026. struct fimd_context *ctx = dev_get_drvdata(dev);
  1027. int ret;
  1028. ret = clk_prepare_enable(ctx->bus_clk);
  1029. if (ret < 0) {
  1030. DRM_DEV_ERROR(dev,
  1031. "Failed to prepare_enable the bus clk [%d]\n",
  1032. ret);
  1033. return ret;
  1034. }
  1035. ret = clk_prepare_enable(ctx->lcd_clk);
  1036. if (ret < 0) {
  1037. DRM_DEV_ERROR(dev,
  1038. "Failed to prepare_enable the lcd clk [%d]\n",
  1039. ret);
  1040. return ret;
  1041. }
  1042. return 0;
  1043. }
  1044. #endif
  1045. static const struct dev_pm_ops exynos_fimd_pm_ops = {
  1046. SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
  1047. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1048. pm_runtime_force_resume)
  1049. };
  1050. struct platform_driver fimd_driver = {
  1051. .probe = fimd_probe,
  1052. .remove = fimd_remove,
  1053. .driver = {
  1054. .name = "exynos4-fb",
  1055. .owner = THIS_MODULE,
  1056. .pm = &exynos_fimd_pm_ops,
  1057. .of_match_table = fimd_driver_dt_match,
  1058. },
  1059. };