exynos_drm_dsi.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Samsung SoC MIPI DSI Master driver.
  4. *
  5. * Copyright (c) 2014 Samsung Electronics Co., Ltd
  6. *
  7. * Contacts: Tomasz Figa <t.figa@samsung.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/component.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/irq.h>
  14. #include <linux/of_device.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/of_graph.h>
  17. #include <linux/phy/phy.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <asm/unaligned.h>
  20. #include <video/mipi_display.h>
  21. #include <video/videomode.h>
  22. #include <drm/drm_atomic_helper.h>
  23. #include <drm/drm_bridge.h>
  24. #include <drm/drm_fb_helper.h>
  25. #include <drm/drm_mipi_dsi.h>
  26. #include <drm/drm_panel.h>
  27. #include <drm/drm_print.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include <drm/drm_simple_kms_helper.h>
  30. #include "exynos_drm_crtc.h"
  31. #include "exynos_drm_drv.h"
  32. /* returns true iff both arguments logically differs */
  33. #define NEQV(a, b) (!(a) ^ !(b))
  34. /* DSIM_STATUS */
  35. #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
  36. #define DSIM_STOP_STATE_CLK (1 << 8)
  37. #define DSIM_TX_READY_HS_CLK (1 << 10)
  38. #define DSIM_PLL_STABLE (1 << 31)
  39. /* DSIM_SWRST */
  40. #define DSIM_FUNCRST (1 << 16)
  41. #define DSIM_SWRST (1 << 0)
  42. /* DSIM_TIMEOUT */
  43. #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
  44. #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
  45. /* DSIM_CLKCTRL */
  46. #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
  47. #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
  48. #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
  49. #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
  50. #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
  51. #define DSIM_BYTE_CLKEN (1 << 24)
  52. #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
  53. #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
  54. #define DSIM_PLL_BYPASS (1 << 27)
  55. #define DSIM_ESC_CLKEN (1 << 28)
  56. #define DSIM_TX_REQUEST_HSCLK (1 << 31)
  57. /* DSIM_CONFIG */
  58. #define DSIM_LANE_EN_CLK (1 << 0)
  59. #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
  60. #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
  61. #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
  62. #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
  63. #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
  64. #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
  65. #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
  66. #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
  67. #define DSIM_SUB_VC (((x) & 0x3) << 16)
  68. #define DSIM_MAIN_VC (((x) & 0x3) << 18)
  69. #define DSIM_HSA_MODE (1 << 20)
  70. #define DSIM_HBP_MODE (1 << 21)
  71. #define DSIM_HFP_MODE (1 << 22)
  72. #define DSIM_HSE_MODE (1 << 23)
  73. #define DSIM_AUTO_MODE (1 << 24)
  74. #define DSIM_VIDEO_MODE (1 << 25)
  75. #define DSIM_BURST_MODE (1 << 26)
  76. #define DSIM_SYNC_INFORM (1 << 27)
  77. #define DSIM_EOT_DISABLE (1 << 28)
  78. #define DSIM_MFLUSH_VS (1 << 29)
  79. /* This flag is valid only for exynos3250/3472/5260/5430 */
  80. #define DSIM_CLKLANE_STOP (1 << 30)
  81. /* DSIM_ESCMODE */
  82. #define DSIM_TX_TRIGGER_RST (1 << 4)
  83. #define DSIM_TX_LPDT_LP (1 << 6)
  84. #define DSIM_CMD_LPDT_LP (1 << 7)
  85. #define DSIM_FORCE_BTA (1 << 16)
  86. #define DSIM_FORCE_STOP_STATE (1 << 20)
  87. #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
  88. #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
  89. /* DSIM_MDRESOL */
  90. #define DSIM_MAIN_STAND_BY (1 << 31)
  91. #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
  92. #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
  93. /* DSIM_MVPORCH */
  94. #define DSIM_CMD_ALLOW(x) ((x) << 28)
  95. #define DSIM_STABLE_VFP(x) ((x) << 16)
  96. #define DSIM_MAIN_VBP(x) ((x) << 0)
  97. #define DSIM_CMD_ALLOW_MASK (0xf << 28)
  98. #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
  99. #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
  100. /* DSIM_MHPORCH */
  101. #define DSIM_MAIN_HFP(x) ((x) << 16)
  102. #define DSIM_MAIN_HBP(x) ((x) << 0)
  103. #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
  104. #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
  105. /* DSIM_MSYNC */
  106. #define DSIM_MAIN_VSA(x) ((x) << 22)
  107. #define DSIM_MAIN_HSA(x) ((x) << 0)
  108. #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
  109. #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
  110. /* DSIM_SDRESOL */
  111. #define DSIM_SUB_STANDY(x) ((x) << 31)
  112. #define DSIM_SUB_VRESOL(x) ((x) << 16)
  113. #define DSIM_SUB_HRESOL(x) ((x) << 0)
  114. #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
  115. #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
  116. #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
  117. /* DSIM_INTSRC */
  118. #define DSIM_INT_PLL_STABLE (1 << 31)
  119. #define DSIM_INT_SW_RST_RELEASE (1 << 30)
  120. #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
  121. #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28)
  122. #define DSIM_INT_BTA (1 << 25)
  123. #define DSIM_INT_FRAME_DONE (1 << 24)
  124. #define DSIM_INT_RX_TIMEOUT (1 << 21)
  125. #define DSIM_INT_BTA_TIMEOUT (1 << 20)
  126. #define DSIM_INT_RX_DONE (1 << 18)
  127. #define DSIM_INT_RX_TE (1 << 17)
  128. #define DSIM_INT_RX_ACK (1 << 16)
  129. #define DSIM_INT_RX_ECC_ERR (1 << 15)
  130. #define DSIM_INT_RX_CRC_ERR (1 << 14)
  131. /* DSIM_FIFOCTRL */
  132. #define DSIM_RX_DATA_FULL (1 << 25)
  133. #define DSIM_RX_DATA_EMPTY (1 << 24)
  134. #define DSIM_SFR_HEADER_FULL (1 << 23)
  135. #define DSIM_SFR_HEADER_EMPTY (1 << 22)
  136. #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
  137. #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
  138. #define DSIM_I80_HEADER_FULL (1 << 19)
  139. #define DSIM_I80_HEADER_EMPTY (1 << 18)
  140. #define DSIM_I80_PAYLOAD_FULL (1 << 17)
  141. #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
  142. #define DSIM_SD_HEADER_FULL (1 << 15)
  143. #define DSIM_SD_HEADER_EMPTY (1 << 14)
  144. #define DSIM_SD_PAYLOAD_FULL (1 << 13)
  145. #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
  146. #define DSIM_MD_HEADER_FULL (1 << 11)
  147. #define DSIM_MD_HEADER_EMPTY (1 << 10)
  148. #define DSIM_MD_PAYLOAD_FULL (1 << 9)
  149. #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
  150. #define DSIM_RX_FIFO (1 << 4)
  151. #define DSIM_SFR_FIFO (1 << 3)
  152. #define DSIM_I80_FIFO (1 << 2)
  153. #define DSIM_SD_FIFO (1 << 1)
  154. #define DSIM_MD_FIFO (1 << 0)
  155. /* DSIM_PHYACCHR */
  156. #define DSIM_AFC_EN (1 << 14)
  157. #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
  158. /* DSIM_PLLCTRL */
  159. #define DSIM_FREQ_BAND(x) ((x) << 24)
  160. #define DSIM_PLL_EN (1 << 23)
  161. #define DSIM_PLL_P(x) ((x) << 13)
  162. #define DSIM_PLL_M(x) ((x) << 4)
  163. #define DSIM_PLL_S(x) ((x) << 1)
  164. /* DSIM_PHYCTRL */
  165. #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
  166. #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30)
  167. #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14)
  168. /* DSIM_PHYTIMING */
  169. #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
  170. #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
  171. /* DSIM_PHYTIMING1 */
  172. #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
  173. #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
  174. #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
  175. #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
  176. /* DSIM_PHYTIMING2 */
  177. #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
  178. #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
  179. #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
  180. #define DSI_MAX_BUS_WIDTH 4
  181. #define DSI_NUM_VIRTUAL_CHANNELS 4
  182. #define DSI_TX_FIFO_SIZE 2048
  183. #define DSI_RX_FIFO_SIZE 256
  184. #define DSI_XFER_TIMEOUT_MS 100
  185. #define DSI_RX_FIFO_EMPTY 0x30800002
  186. #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
  187. static const char *const clk_names[5] = { "bus_clk", "sclk_mipi",
  188. "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
  189. "sclk_rgb_vclk_to_dsim0" };
  190. enum exynos_dsi_transfer_type {
  191. EXYNOS_DSI_TX,
  192. EXYNOS_DSI_RX,
  193. };
  194. struct exynos_dsi_transfer {
  195. struct list_head list;
  196. struct completion completed;
  197. int result;
  198. struct mipi_dsi_packet packet;
  199. u16 flags;
  200. u16 tx_done;
  201. u8 *rx_payload;
  202. u16 rx_len;
  203. u16 rx_done;
  204. };
  205. #define DSIM_STATE_ENABLED BIT(0)
  206. #define DSIM_STATE_INITIALIZED BIT(1)
  207. #define DSIM_STATE_CMD_LPM BIT(2)
  208. #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
  209. struct exynos_dsi_driver_data {
  210. const unsigned int *reg_ofs;
  211. unsigned int plltmr_reg;
  212. unsigned int has_freqband:1;
  213. unsigned int has_clklane_stop:1;
  214. unsigned int num_clks;
  215. unsigned int max_freq;
  216. unsigned int wait_for_reset;
  217. unsigned int num_bits_resol;
  218. const unsigned int *reg_values;
  219. };
  220. struct exynos_dsi {
  221. struct drm_encoder encoder;
  222. struct mipi_dsi_host dsi_host;
  223. struct drm_connector connector;
  224. struct drm_panel *panel;
  225. struct list_head bridge_chain;
  226. struct drm_bridge *out_bridge;
  227. struct device *dev;
  228. void __iomem *reg_base;
  229. struct phy *phy;
  230. struct clk **clks;
  231. struct regulator_bulk_data supplies[2];
  232. int irq;
  233. int te_gpio;
  234. u32 pll_clk_rate;
  235. u32 burst_clk_rate;
  236. u32 esc_clk_rate;
  237. u32 lanes;
  238. u32 mode_flags;
  239. u32 format;
  240. int state;
  241. struct drm_property *brightness;
  242. struct completion completed;
  243. spinlock_t transfer_lock; /* protects transfer_list */
  244. struct list_head transfer_list;
  245. const struct exynos_dsi_driver_data *driver_data;
  246. struct device_node *in_bridge_node;
  247. };
  248. #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
  249. #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
  250. static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e)
  251. {
  252. return container_of(e, struct exynos_dsi, encoder);
  253. }
  254. enum reg_idx {
  255. DSIM_STATUS_REG, /* Status register */
  256. DSIM_SWRST_REG, /* Software reset register */
  257. DSIM_CLKCTRL_REG, /* Clock control register */
  258. DSIM_TIMEOUT_REG, /* Time out register */
  259. DSIM_CONFIG_REG, /* Configuration register */
  260. DSIM_ESCMODE_REG, /* Escape mode register */
  261. DSIM_MDRESOL_REG,
  262. DSIM_MVPORCH_REG, /* Main display Vporch register */
  263. DSIM_MHPORCH_REG, /* Main display Hporch register */
  264. DSIM_MSYNC_REG, /* Main display sync area register */
  265. DSIM_INTSRC_REG, /* Interrupt source register */
  266. DSIM_INTMSK_REG, /* Interrupt mask register */
  267. DSIM_PKTHDR_REG, /* Packet Header FIFO register */
  268. DSIM_PAYLOAD_REG, /* Payload FIFO register */
  269. DSIM_RXFIFO_REG, /* Read FIFO register */
  270. DSIM_FIFOCTRL_REG, /* FIFO status and control register */
  271. DSIM_PLLCTRL_REG, /* PLL control register */
  272. DSIM_PHYCTRL_REG,
  273. DSIM_PHYTIMING_REG,
  274. DSIM_PHYTIMING1_REG,
  275. DSIM_PHYTIMING2_REG,
  276. NUM_REGS
  277. };
  278. static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
  279. u32 val)
  280. {
  281. writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
  282. }
  283. static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
  284. {
  285. return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
  286. }
  287. static const unsigned int exynos_reg_ofs[] = {
  288. [DSIM_STATUS_REG] = 0x00,
  289. [DSIM_SWRST_REG] = 0x04,
  290. [DSIM_CLKCTRL_REG] = 0x08,
  291. [DSIM_TIMEOUT_REG] = 0x0c,
  292. [DSIM_CONFIG_REG] = 0x10,
  293. [DSIM_ESCMODE_REG] = 0x14,
  294. [DSIM_MDRESOL_REG] = 0x18,
  295. [DSIM_MVPORCH_REG] = 0x1c,
  296. [DSIM_MHPORCH_REG] = 0x20,
  297. [DSIM_MSYNC_REG] = 0x24,
  298. [DSIM_INTSRC_REG] = 0x2c,
  299. [DSIM_INTMSK_REG] = 0x30,
  300. [DSIM_PKTHDR_REG] = 0x34,
  301. [DSIM_PAYLOAD_REG] = 0x38,
  302. [DSIM_RXFIFO_REG] = 0x3c,
  303. [DSIM_FIFOCTRL_REG] = 0x44,
  304. [DSIM_PLLCTRL_REG] = 0x4c,
  305. [DSIM_PHYCTRL_REG] = 0x5c,
  306. [DSIM_PHYTIMING_REG] = 0x64,
  307. [DSIM_PHYTIMING1_REG] = 0x68,
  308. [DSIM_PHYTIMING2_REG] = 0x6c,
  309. };
  310. static const unsigned int exynos5433_reg_ofs[] = {
  311. [DSIM_STATUS_REG] = 0x04,
  312. [DSIM_SWRST_REG] = 0x0C,
  313. [DSIM_CLKCTRL_REG] = 0x10,
  314. [DSIM_TIMEOUT_REG] = 0x14,
  315. [DSIM_CONFIG_REG] = 0x18,
  316. [DSIM_ESCMODE_REG] = 0x1C,
  317. [DSIM_MDRESOL_REG] = 0x20,
  318. [DSIM_MVPORCH_REG] = 0x24,
  319. [DSIM_MHPORCH_REG] = 0x28,
  320. [DSIM_MSYNC_REG] = 0x2C,
  321. [DSIM_INTSRC_REG] = 0x34,
  322. [DSIM_INTMSK_REG] = 0x38,
  323. [DSIM_PKTHDR_REG] = 0x3C,
  324. [DSIM_PAYLOAD_REG] = 0x40,
  325. [DSIM_RXFIFO_REG] = 0x44,
  326. [DSIM_FIFOCTRL_REG] = 0x4C,
  327. [DSIM_PLLCTRL_REG] = 0x94,
  328. [DSIM_PHYCTRL_REG] = 0xA4,
  329. [DSIM_PHYTIMING_REG] = 0xB4,
  330. [DSIM_PHYTIMING1_REG] = 0xB8,
  331. [DSIM_PHYTIMING2_REG] = 0xBC,
  332. };
  333. enum reg_value_idx {
  334. RESET_TYPE,
  335. PLL_TIMER,
  336. STOP_STATE_CNT,
  337. PHYCTRL_ULPS_EXIT,
  338. PHYCTRL_VREG_LP,
  339. PHYCTRL_SLEW_UP,
  340. PHYTIMING_LPX,
  341. PHYTIMING_HS_EXIT,
  342. PHYTIMING_CLK_PREPARE,
  343. PHYTIMING_CLK_ZERO,
  344. PHYTIMING_CLK_POST,
  345. PHYTIMING_CLK_TRAIL,
  346. PHYTIMING_HS_PREPARE,
  347. PHYTIMING_HS_ZERO,
  348. PHYTIMING_HS_TRAIL
  349. };
  350. static const unsigned int reg_values[] = {
  351. [RESET_TYPE] = DSIM_SWRST,
  352. [PLL_TIMER] = 500,
  353. [STOP_STATE_CNT] = 0xf,
  354. [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
  355. [PHYCTRL_VREG_LP] = 0,
  356. [PHYCTRL_SLEW_UP] = 0,
  357. [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
  358. [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
  359. [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
  360. [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
  361. [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
  362. [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
  363. [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
  364. [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
  365. [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
  366. };
  367. static const unsigned int exynos5422_reg_values[] = {
  368. [RESET_TYPE] = DSIM_SWRST,
  369. [PLL_TIMER] = 500,
  370. [STOP_STATE_CNT] = 0xf,
  371. [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
  372. [PHYCTRL_VREG_LP] = 0,
  373. [PHYCTRL_SLEW_UP] = 0,
  374. [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
  375. [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
  376. [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
  377. [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
  378. [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
  379. [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
  380. [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
  381. [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
  382. [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
  383. };
  384. static const unsigned int exynos5433_reg_values[] = {
  385. [RESET_TYPE] = DSIM_FUNCRST,
  386. [PLL_TIMER] = 22200,
  387. [STOP_STATE_CNT] = 0xa,
  388. [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
  389. [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
  390. [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
  391. [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
  392. [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
  393. [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
  394. [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
  395. [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
  396. [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
  397. [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
  398. [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
  399. [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
  400. };
  401. static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
  402. .reg_ofs = exynos_reg_ofs,
  403. .plltmr_reg = 0x50,
  404. .has_freqband = 1,
  405. .has_clklane_stop = 1,
  406. .num_clks = 2,
  407. .max_freq = 1000,
  408. .wait_for_reset = 1,
  409. .num_bits_resol = 11,
  410. .reg_values = reg_values,
  411. };
  412. static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
  413. .reg_ofs = exynos_reg_ofs,
  414. .plltmr_reg = 0x50,
  415. .has_freqband = 1,
  416. .has_clklane_stop = 1,
  417. .num_clks = 2,
  418. .max_freq = 1000,
  419. .wait_for_reset = 1,
  420. .num_bits_resol = 11,
  421. .reg_values = reg_values,
  422. };
  423. static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
  424. .reg_ofs = exynos_reg_ofs,
  425. .plltmr_reg = 0x58,
  426. .num_clks = 2,
  427. .max_freq = 1000,
  428. .wait_for_reset = 1,
  429. .num_bits_resol = 11,
  430. .reg_values = reg_values,
  431. };
  432. static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
  433. .reg_ofs = exynos5433_reg_ofs,
  434. .plltmr_reg = 0xa0,
  435. .has_clklane_stop = 1,
  436. .num_clks = 5,
  437. .max_freq = 1500,
  438. .wait_for_reset = 0,
  439. .num_bits_resol = 12,
  440. .reg_values = exynos5433_reg_values,
  441. };
  442. static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
  443. .reg_ofs = exynos5433_reg_ofs,
  444. .plltmr_reg = 0xa0,
  445. .has_clklane_stop = 1,
  446. .num_clks = 2,
  447. .max_freq = 1500,
  448. .wait_for_reset = 1,
  449. .num_bits_resol = 12,
  450. .reg_values = exynos5422_reg_values,
  451. };
  452. static const struct of_device_id exynos_dsi_of_match[] = {
  453. { .compatible = "samsung,exynos3250-mipi-dsi",
  454. .data = &exynos3_dsi_driver_data },
  455. { .compatible = "samsung,exynos4210-mipi-dsi",
  456. .data = &exynos4_dsi_driver_data },
  457. { .compatible = "samsung,exynos5410-mipi-dsi",
  458. .data = &exynos5_dsi_driver_data },
  459. { .compatible = "samsung,exynos5422-mipi-dsi",
  460. .data = &exynos5422_dsi_driver_data },
  461. { .compatible = "samsung,exynos5433-mipi-dsi",
  462. .data = &exynos5433_dsi_driver_data },
  463. { }
  464. };
  465. static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
  466. {
  467. if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
  468. return;
  469. dev_err(dsi->dev, "timeout waiting for reset\n");
  470. }
  471. static void exynos_dsi_reset(struct exynos_dsi *dsi)
  472. {
  473. u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
  474. reinit_completion(&dsi->completed);
  475. exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
  476. }
  477. #ifndef MHZ
  478. #define MHZ (1000*1000)
  479. #endif
  480. static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
  481. unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
  482. {
  483. const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
  484. unsigned long best_freq = 0;
  485. u32 min_delta = 0xffffffff;
  486. u8 p_min, p_max;
  487. u8 _p, best_p;
  488. u16 _m, best_m;
  489. u8 _s, best_s;
  490. p_min = DIV_ROUND_UP(fin, (12 * MHZ));
  491. p_max = fin / (6 * MHZ);
  492. for (_p = p_min; _p <= p_max; ++_p) {
  493. for (_s = 0; _s <= 5; ++_s) {
  494. u64 tmp;
  495. u32 delta;
  496. tmp = (u64)fout * (_p << _s);
  497. do_div(tmp, fin);
  498. _m = tmp;
  499. if (_m < 41 || _m > 125)
  500. continue;
  501. tmp = (u64)_m * fin;
  502. do_div(tmp, _p);
  503. if (tmp < 500 * MHZ ||
  504. tmp > driver_data->max_freq * MHZ)
  505. continue;
  506. tmp = (u64)_m * fin;
  507. do_div(tmp, _p << _s);
  508. delta = abs(fout - tmp);
  509. if (delta < min_delta) {
  510. best_p = _p;
  511. best_m = _m;
  512. best_s = _s;
  513. min_delta = delta;
  514. best_freq = tmp;
  515. }
  516. }
  517. }
  518. if (best_freq) {
  519. *p = best_p;
  520. *m = best_m;
  521. *s = best_s;
  522. }
  523. return best_freq;
  524. }
  525. static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
  526. unsigned long freq)
  527. {
  528. const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
  529. unsigned long fin, fout;
  530. int timeout;
  531. u8 p, s;
  532. u16 m;
  533. u32 reg;
  534. fin = dsi->pll_clk_rate;
  535. fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
  536. if (!fout) {
  537. dev_err(dsi->dev,
  538. "failed to find PLL PMS for requested frequency\n");
  539. return 0;
  540. }
  541. dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
  542. writel(driver_data->reg_values[PLL_TIMER],
  543. dsi->reg_base + driver_data->plltmr_reg);
  544. reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
  545. if (driver_data->has_freqband) {
  546. static const unsigned long freq_bands[] = {
  547. 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
  548. 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
  549. 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
  550. 770 * MHZ, 870 * MHZ, 950 * MHZ,
  551. };
  552. int band;
  553. for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
  554. if (fout < freq_bands[band])
  555. break;
  556. dev_dbg(dsi->dev, "band %d\n", band);
  557. reg |= DSIM_FREQ_BAND(band);
  558. }
  559. exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
  560. timeout = 1000;
  561. do {
  562. if (timeout-- == 0) {
  563. dev_err(dsi->dev, "PLL failed to stabilize\n");
  564. return 0;
  565. }
  566. reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
  567. } while ((reg & DSIM_PLL_STABLE) == 0);
  568. return fout;
  569. }
  570. static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
  571. {
  572. unsigned long hs_clk, byte_clk, esc_clk;
  573. unsigned long esc_div;
  574. u32 reg;
  575. hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
  576. if (!hs_clk) {
  577. dev_err(dsi->dev, "failed to configure DSI PLL\n");
  578. return -EFAULT;
  579. }
  580. byte_clk = hs_clk / 8;
  581. esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
  582. esc_clk = byte_clk / esc_div;
  583. if (esc_clk > 20 * MHZ) {
  584. ++esc_div;
  585. esc_clk = byte_clk / esc_div;
  586. }
  587. dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
  588. hs_clk, byte_clk, esc_clk);
  589. reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
  590. reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
  591. | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
  592. | DSIM_BYTE_CLK_SRC_MASK);
  593. reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
  594. | DSIM_ESC_PRESCALER(esc_div)
  595. | DSIM_LANE_ESC_CLK_EN_CLK
  596. | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
  597. | DSIM_BYTE_CLK_SRC(0)
  598. | DSIM_TX_REQUEST_HSCLK;
  599. exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
  600. return 0;
  601. }
  602. static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
  603. {
  604. const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
  605. const unsigned int *reg_values = driver_data->reg_values;
  606. u32 reg;
  607. if (driver_data->has_freqband)
  608. return;
  609. /* B D-PHY: D-PHY Master & Slave Analog Block control */
  610. reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
  611. reg_values[PHYCTRL_SLEW_UP];
  612. exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
  613. /*
  614. * T LPX: Transmitted length of any Low-Power state period
  615. * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
  616. * burst
  617. */
  618. reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
  619. exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
  620. /*
  621. * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
  622. * Line state immediately before the HS-0 Line state starting the
  623. * HS transmission
  624. * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
  625. * transmitting the Clock.
  626. * T CLK_POST: Time that the transmitter continues to send HS clock
  627. * after the last associated Data Lane has transitioned to LP Mode
  628. * Interval is defined as the period from the end of T HS-TRAIL to
  629. * the beginning of T CLK-TRAIL
  630. * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
  631. * the last payload clock bit of a HS transmission burst
  632. */
  633. reg = reg_values[PHYTIMING_CLK_PREPARE] |
  634. reg_values[PHYTIMING_CLK_ZERO] |
  635. reg_values[PHYTIMING_CLK_POST] |
  636. reg_values[PHYTIMING_CLK_TRAIL];
  637. exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
  638. /*
  639. * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
  640. * Line state immediately before the HS-0 Line state starting the
  641. * HS transmission
  642. * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
  643. * transmitting the Sync sequence.
  644. * T HS-TRAIL: Time that the transmitter drives the flipped differential
  645. * state after last payload data bit of a HS transmission burst
  646. */
  647. reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
  648. reg_values[PHYTIMING_HS_TRAIL];
  649. exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
  650. }
  651. static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
  652. {
  653. u32 reg;
  654. reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
  655. reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
  656. | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
  657. exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
  658. reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
  659. reg &= ~DSIM_PLL_EN;
  660. exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
  661. }
  662. static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
  663. {
  664. u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
  665. reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
  666. DSIM_LANE_EN(lane));
  667. exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
  668. }
  669. static int exynos_dsi_init_link(struct exynos_dsi *dsi)
  670. {
  671. const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
  672. int timeout;
  673. u32 reg;
  674. u32 lanes_mask;
  675. /* Initialize FIFO pointers */
  676. reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
  677. reg &= ~0x1f;
  678. exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
  679. usleep_range(9000, 11000);
  680. reg |= 0x1f;
  681. exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
  682. usleep_range(9000, 11000);
  683. /* DSI configuration */
  684. reg = 0;
  685. /*
  686. * The first bit of mode_flags specifies display configuration.
  687. * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
  688. * mode, otherwise it will support command mode.
  689. */
  690. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  691. reg |= DSIM_VIDEO_MODE;
  692. /*
  693. * The user manual describes that following bits are ignored in
  694. * command mode.
  695. */
  696. if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
  697. reg |= DSIM_MFLUSH_VS;
  698. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  699. reg |= DSIM_SYNC_INFORM;
  700. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  701. reg |= DSIM_BURST_MODE;
  702. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
  703. reg |= DSIM_AUTO_MODE;
  704. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
  705. reg |= DSIM_HSE_MODE;
  706. if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
  707. reg |= DSIM_HFP_MODE;
  708. if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
  709. reg |= DSIM_HBP_MODE;
  710. if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
  711. reg |= DSIM_HSA_MODE;
  712. }
  713. if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
  714. reg |= DSIM_EOT_DISABLE;
  715. switch (dsi->format) {
  716. case MIPI_DSI_FMT_RGB888:
  717. reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
  718. break;
  719. case MIPI_DSI_FMT_RGB666:
  720. reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
  721. break;
  722. case MIPI_DSI_FMT_RGB666_PACKED:
  723. reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
  724. break;
  725. case MIPI_DSI_FMT_RGB565:
  726. reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
  727. break;
  728. default:
  729. dev_err(dsi->dev, "invalid pixel format\n");
  730. return -EINVAL;
  731. }
  732. /*
  733. * Use non-continuous clock mode if the periparal wants and
  734. * host controller supports
  735. *
  736. * In non-continous clock mode, host controller will turn off
  737. * the HS clock between high-speed transmissions to reduce
  738. * power consumption.
  739. */
  740. if (driver_data->has_clklane_stop &&
  741. dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
  742. reg |= DSIM_CLKLANE_STOP;
  743. }
  744. exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
  745. lanes_mask = BIT(dsi->lanes) - 1;
  746. exynos_dsi_enable_lane(dsi, lanes_mask);
  747. /* Check clock and data lane state are stop state */
  748. timeout = 100;
  749. do {
  750. if (timeout-- == 0) {
  751. dev_err(dsi->dev, "waiting for bus lanes timed out\n");
  752. return -EFAULT;
  753. }
  754. reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
  755. if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
  756. != DSIM_STOP_STATE_DAT(lanes_mask))
  757. continue;
  758. } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
  759. reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
  760. reg &= ~DSIM_STOP_STATE_CNT_MASK;
  761. reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
  762. exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
  763. reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
  764. exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
  765. return 0;
  766. }
  767. static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
  768. {
  769. struct drm_display_mode *m = &dsi->encoder.crtc->state->adjusted_mode;
  770. unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
  771. u32 reg;
  772. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  773. reg = DSIM_CMD_ALLOW(0xf)
  774. | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
  775. | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
  776. exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
  777. reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
  778. | DSIM_MAIN_HBP(m->htotal - m->hsync_end);
  779. exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
  780. reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
  781. | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
  782. exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
  783. }
  784. reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
  785. DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
  786. exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
  787. dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
  788. }
  789. static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
  790. {
  791. u32 reg;
  792. reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
  793. if (enable)
  794. reg |= DSIM_MAIN_STAND_BY;
  795. else
  796. reg &= ~DSIM_MAIN_STAND_BY;
  797. exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
  798. }
  799. static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
  800. {
  801. int timeout = 2000;
  802. do {
  803. u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
  804. if (!(reg & DSIM_SFR_HEADER_FULL))
  805. return 0;
  806. if (!cond_resched())
  807. usleep_range(950, 1050);
  808. } while (--timeout);
  809. return -ETIMEDOUT;
  810. }
  811. static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
  812. {
  813. u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
  814. if (lpm)
  815. v |= DSIM_CMD_LPDT_LP;
  816. else
  817. v &= ~DSIM_CMD_LPDT_LP;
  818. exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
  819. }
  820. static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
  821. {
  822. u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
  823. v |= DSIM_FORCE_BTA;
  824. exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
  825. }
  826. static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
  827. struct exynos_dsi_transfer *xfer)
  828. {
  829. struct device *dev = dsi->dev;
  830. struct mipi_dsi_packet *pkt = &xfer->packet;
  831. const u8 *payload = pkt->payload + xfer->tx_done;
  832. u16 length = pkt->payload_length - xfer->tx_done;
  833. bool first = !xfer->tx_done;
  834. u32 reg;
  835. dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
  836. xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
  837. if (length > DSI_TX_FIFO_SIZE)
  838. length = DSI_TX_FIFO_SIZE;
  839. xfer->tx_done += length;
  840. /* Send payload */
  841. while (length >= 4) {
  842. reg = get_unaligned_le32(payload);
  843. exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
  844. payload += 4;
  845. length -= 4;
  846. }
  847. reg = 0;
  848. switch (length) {
  849. case 3:
  850. reg |= payload[2] << 16;
  851. fallthrough;
  852. case 2:
  853. reg |= payload[1] << 8;
  854. fallthrough;
  855. case 1:
  856. reg |= payload[0];
  857. exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
  858. break;
  859. }
  860. /* Send packet header */
  861. if (!first)
  862. return;
  863. reg = get_unaligned_le32(pkt->header);
  864. if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
  865. dev_err(dev, "waiting for header FIFO timed out\n");
  866. return;
  867. }
  868. if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
  869. dsi->state & DSIM_STATE_CMD_LPM)) {
  870. exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
  871. dsi->state ^= DSIM_STATE_CMD_LPM;
  872. }
  873. exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
  874. if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
  875. exynos_dsi_force_bta(dsi);
  876. }
  877. static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
  878. struct exynos_dsi_transfer *xfer)
  879. {
  880. u8 *payload = xfer->rx_payload + xfer->rx_done;
  881. bool first = !xfer->rx_done;
  882. struct device *dev = dsi->dev;
  883. u16 length;
  884. u32 reg;
  885. if (first) {
  886. reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
  887. switch (reg & 0x3f) {
  888. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
  889. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
  890. if (xfer->rx_len >= 2) {
  891. payload[1] = reg >> 16;
  892. ++xfer->rx_done;
  893. }
  894. fallthrough;
  895. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
  896. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
  897. payload[0] = reg >> 8;
  898. ++xfer->rx_done;
  899. xfer->rx_len = xfer->rx_done;
  900. xfer->result = 0;
  901. goto clear_fifo;
  902. case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
  903. dev_err(dev, "DSI Error Report: 0x%04x\n",
  904. (reg >> 8) & 0xffff);
  905. xfer->result = 0;
  906. goto clear_fifo;
  907. }
  908. length = (reg >> 8) & 0xffff;
  909. if (length > xfer->rx_len) {
  910. dev_err(dev,
  911. "response too long (%u > %u bytes), stripping\n",
  912. xfer->rx_len, length);
  913. length = xfer->rx_len;
  914. } else if (length < xfer->rx_len)
  915. xfer->rx_len = length;
  916. }
  917. length = xfer->rx_len - xfer->rx_done;
  918. xfer->rx_done += length;
  919. /* Receive payload */
  920. while (length >= 4) {
  921. reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
  922. payload[0] = (reg >> 0) & 0xff;
  923. payload[1] = (reg >> 8) & 0xff;
  924. payload[2] = (reg >> 16) & 0xff;
  925. payload[3] = (reg >> 24) & 0xff;
  926. payload += 4;
  927. length -= 4;
  928. }
  929. if (length) {
  930. reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
  931. switch (length) {
  932. case 3:
  933. payload[2] = (reg >> 16) & 0xff;
  934. fallthrough;
  935. case 2:
  936. payload[1] = (reg >> 8) & 0xff;
  937. fallthrough;
  938. case 1:
  939. payload[0] = reg & 0xff;
  940. }
  941. }
  942. if (xfer->rx_done == xfer->rx_len)
  943. xfer->result = 0;
  944. clear_fifo:
  945. length = DSI_RX_FIFO_SIZE / 4;
  946. do {
  947. reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
  948. if (reg == DSI_RX_FIFO_EMPTY)
  949. break;
  950. } while (--length);
  951. }
  952. static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
  953. {
  954. unsigned long flags;
  955. struct exynos_dsi_transfer *xfer;
  956. bool start = false;
  957. again:
  958. spin_lock_irqsave(&dsi->transfer_lock, flags);
  959. if (list_empty(&dsi->transfer_list)) {
  960. spin_unlock_irqrestore(&dsi->transfer_lock, flags);
  961. return;
  962. }
  963. xfer = list_first_entry(&dsi->transfer_list,
  964. struct exynos_dsi_transfer, list);
  965. spin_unlock_irqrestore(&dsi->transfer_lock, flags);
  966. if (xfer->packet.payload_length &&
  967. xfer->tx_done == xfer->packet.payload_length)
  968. /* waiting for RX */
  969. return;
  970. exynos_dsi_send_to_fifo(dsi, xfer);
  971. if (xfer->packet.payload_length || xfer->rx_len)
  972. return;
  973. xfer->result = 0;
  974. complete(&xfer->completed);
  975. spin_lock_irqsave(&dsi->transfer_lock, flags);
  976. list_del_init(&xfer->list);
  977. start = !list_empty(&dsi->transfer_list);
  978. spin_unlock_irqrestore(&dsi->transfer_lock, flags);
  979. if (start)
  980. goto again;
  981. }
  982. static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
  983. {
  984. struct exynos_dsi_transfer *xfer;
  985. unsigned long flags;
  986. bool start = true;
  987. spin_lock_irqsave(&dsi->transfer_lock, flags);
  988. if (list_empty(&dsi->transfer_list)) {
  989. spin_unlock_irqrestore(&dsi->transfer_lock, flags);
  990. return false;
  991. }
  992. xfer = list_first_entry(&dsi->transfer_list,
  993. struct exynos_dsi_transfer, list);
  994. spin_unlock_irqrestore(&dsi->transfer_lock, flags);
  995. dev_dbg(dsi->dev,
  996. "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
  997. xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
  998. xfer->rx_done);
  999. if (xfer->tx_done != xfer->packet.payload_length)
  1000. return true;
  1001. if (xfer->rx_done != xfer->rx_len)
  1002. exynos_dsi_read_from_fifo(dsi, xfer);
  1003. if (xfer->rx_done != xfer->rx_len)
  1004. return true;
  1005. spin_lock_irqsave(&dsi->transfer_lock, flags);
  1006. list_del_init(&xfer->list);
  1007. start = !list_empty(&dsi->transfer_list);
  1008. spin_unlock_irqrestore(&dsi->transfer_lock, flags);
  1009. if (!xfer->rx_len)
  1010. xfer->result = 0;
  1011. complete(&xfer->completed);
  1012. return start;
  1013. }
  1014. static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
  1015. struct exynos_dsi_transfer *xfer)
  1016. {
  1017. unsigned long flags;
  1018. bool start;
  1019. spin_lock_irqsave(&dsi->transfer_lock, flags);
  1020. if (!list_empty(&dsi->transfer_list) &&
  1021. xfer == list_first_entry(&dsi->transfer_list,
  1022. struct exynos_dsi_transfer, list)) {
  1023. list_del_init(&xfer->list);
  1024. start = !list_empty(&dsi->transfer_list);
  1025. spin_unlock_irqrestore(&dsi->transfer_lock, flags);
  1026. if (start)
  1027. exynos_dsi_transfer_start(dsi);
  1028. return;
  1029. }
  1030. list_del_init(&xfer->list);
  1031. spin_unlock_irqrestore(&dsi->transfer_lock, flags);
  1032. }
  1033. static int exynos_dsi_transfer(struct exynos_dsi *dsi,
  1034. struct exynos_dsi_transfer *xfer)
  1035. {
  1036. unsigned long flags;
  1037. bool stopped;
  1038. xfer->tx_done = 0;
  1039. xfer->rx_done = 0;
  1040. xfer->result = -ETIMEDOUT;
  1041. init_completion(&xfer->completed);
  1042. spin_lock_irqsave(&dsi->transfer_lock, flags);
  1043. stopped = list_empty(&dsi->transfer_list);
  1044. list_add_tail(&xfer->list, &dsi->transfer_list);
  1045. spin_unlock_irqrestore(&dsi->transfer_lock, flags);
  1046. if (stopped)
  1047. exynos_dsi_transfer_start(dsi);
  1048. wait_for_completion_timeout(&xfer->completed,
  1049. msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
  1050. if (xfer->result == -ETIMEDOUT) {
  1051. struct mipi_dsi_packet *pkt = &xfer->packet;
  1052. exynos_dsi_remove_transfer(dsi, xfer);
  1053. dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
  1054. (int)pkt->payload_length, pkt->payload);
  1055. return -ETIMEDOUT;
  1056. }
  1057. /* Also covers hardware timeout condition */
  1058. return xfer->result;
  1059. }
  1060. static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
  1061. {
  1062. struct exynos_dsi *dsi = dev_id;
  1063. u32 status;
  1064. status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
  1065. if (!status) {
  1066. static unsigned long int j;
  1067. if (printk_timed_ratelimit(&j, 500))
  1068. dev_warn(dsi->dev, "spurious interrupt\n");
  1069. return IRQ_HANDLED;
  1070. }
  1071. exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
  1072. if (status & DSIM_INT_SW_RST_RELEASE) {
  1073. u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
  1074. DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR |
  1075. DSIM_INT_SW_RST_RELEASE);
  1076. exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
  1077. complete(&dsi->completed);
  1078. return IRQ_HANDLED;
  1079. }
  1080. if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
  1081. DSIM_INT_PLL_STABLE)))
  1082. return IRQ_HANDLED;
  1083. if (exynos_dsi_transfer_finish(dsi))
  1084. exynos_dsi_transfer_start(dsi);
  1085. return IRQ_HANDLED;
  1086. }
  1087. static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
  1088. {
  1089. struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
  1090. struct drm_encoder *encoder = &dsi->encoder;
  1091. if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
  1092. exynos_drm_crtc_te_handler(encoder->crtc);
  1093. return IRQ_HANDLED;
  1094. }
  1095. static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
  1096. {
  1097. enable_irq(dsi->irq);
  1098. if (gpio_is_valid(dsi->te_gpio))
  1099. enable_irq(gpio_to_irq(dsi->te_gpio));
  1100. }
  1101. static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
  1102. {
  1103. if (gpio_is_valid(dsi->te_gpio))
  1104. disable_irq(gpio_to_irq(dsi->te_gpio));
  1105. disable_irq(dsi->irq);
  1106. }
  1107. static int exynos_dsi_init(struct exynos_dsi *dsi)
  1108. {
  1109. const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
  1110. exynos_dsi_reset(dsi);
  1111. exynos_dsi_enable_irq(dsi);
  1112. if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
  1113. exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
  1114. exynos_dsi_enable_clock(dsi);
  1115. if (driver_data->wait_for_reset)
  1116. exynos_dsi_wait_for_reset(dsi);
  1117. exynos_dsi_set_phy_ctrl(dsi);
  1118. exynos_dsi_init_link(dsi);
  1119. return 0;
  1120. }
  1121. static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi,
  1122. struct device *panel)
  1123. {
  1124. int ret;
  1125. int te_gpio_irq;
  1126. dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0);
  1127. if (dsi->te_gpio == -ENOENT)
  1128. return 0;
  1129. if (!gpio_is_valid(dsi->te_gpio)) {
  1130. ret = dsi->te_gpio;
  1131. dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret);
  1132. goto out;
  1133. }
  1134. ret = gpio_request(dsi->te_gpio, "te_gpio");
  1135. if (ret) {
  1136. dev_err(dsi->dev, "gpio request failed with %d\n", ret);
  1137. goto out;
  1138. }
  1139. te_gpio_irq = gpio_to_irq(dsi->te_gpio);
  1140. irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
  1141. ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
  1142. IRQF_TRIGGER_RISING, "TE", dsi);
  1143. if (ret) {
  1144. dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
  1145. gpio_free(dsi->te_gpio);
  1146. goto out;
  1147. }
  1148. out:
  1149. return ret;
  1150. }
  1151. static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
  1152. {
  1153. if (gpio_is_valid(dsi->te_gpio)) {
  1154. free_irq(gpio_to_irq(dsi->te_gpio), dsi);
  1155. gpio_free(dsi->te_gpio);
  1156. dsi->te_gpio = -ENOENT;
  1157. }
  1158. }
  1159. static void exynos_dsi_enable(struct drm_encoder *encoder)
  1160. {
  1161. struct exynos_dsi *dsi = encoder_to_dsi(encoder);
  1162. struct drm_bridge *iter;
  1163. int ret;
  1164. if (dsi->state & DSIM_STATE_ENABLED)
  1165. return;
  1166. pm_runtime_get_sync(dsi->dev);
  1167. dsi->state |= DSIM_STATE_ENABLED;
  1168. if (dsi->panel) {
  1169. ret = drm_panel_prepare(dsi->panel);
  1170. if (ret < 0)
  1171. goto err_put_sync;
  1172. } else {
  1173. list_for_each_entry_reverse(iter, &dsi->bridge_chain,
  1174. chain_node) {
  1175. if (iter->funcs->pre_enable)
  1176. iter->funcs->pre_enable(iter);
  1177. }
  1178. }
  1179. exynos_dsi_set_display_mode(dsi);
  1180. exynos_dsi_set_display_enable(dsi, true);
  1181. if (dsi->panel) {
  1182. ret = drm_panel_enable(dsi->panel);
  1183. if (ret < 0)
  1184. goto err_display_disable;
  1185. } else {
  1186. list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
  1187. if (iter->funcs->enable)
  1188. iter->funcs->enable(iter);
  1189. }
  1190. }
  1191. dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
  1192. return;
  1193. err_display_disable:
  1194. exynos_dsi_set_display_enable(dsi, false);
  1195. drm_panel_unprepare(dsi->panel);
  1196. err_put_sync:
  1197. dsi->state &= ~DSIM_STATE_ENABLED;
  1198. pm_runtime_put(dsi->dev);
  1199. }
  1200. static void exynos_dsi_disable(struct drm_encoder *encoder)
  1201. {
  1202. struct exynos_dsi *dsi = encoder_to_dsi(encoder);
  1203. struct drm_bridge *iter;
  1204. if (!(dsi->state & DSIM_STATE_ENABLED))
  1205. return;
  1206. dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
  1207. drm_panel_disable(dsi->panel);
  1208. list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
  1209. if (iter->funcs->disable)
  1210. iter->funcs->disable(iter);
  1211. }
  1212. exynos_dsi_set_display_enable(dsi, false);
  1213. drm_panel_unprepare(dsi->panel);
  1214. list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
  1215. if (iter->funcs->post_disable)
  1216. iter->funcs->post_disable(iter);
  1217. }
  1218. dsi->state &= ~DSIM_STATE_ENABLED;
  1219. pm_runtime_put_sync(dsi->dev);
  1220. }
  1221. static enum drm_connector_status
  1222. exynos_dsi_detect(struct drm_connector *connector, bool force)
  1223. {
  1224. return connector->status;
  1225. }
  1226. static void exynos_dsi_connector_destroy(struct drm_connector *connector)
  1227. {
  1228. drm_connector_unregister(connector);
  1229. drm_connector_cleanup(connector);
  1230. connector->dev = NULL;
  1231. }
  1232. static const struct drm_connector_funcs exynos_dsi_connector_funcs = {
  1233. .detect = exynos_dsi_detect,
  1234. .fill_modes = drm_helper_probe_single_connector_modes,
  1235. .destroy = exynos_dsi_connector_destroy,
  1236. .reset = drm_atomic_helper_connector_reset,
  1237. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  1238. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  1239. };
  1240. static int exynos_dsi_get_modes(struct drm_connector *connector)
  1241. {
  1242. struct exynos_dsi *dsi = connector_to_dsi(connector);
  1243. if (dsi->panel)
  1244. return drm_panel_get_modes(dsi->panel, connector);
  1245. return 0;
  1246. }
  1247. static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
  1248. .get_modes = exynos_dsi_get_modes,
  1249. };
  1250. static int exynos_dsi_create_connector(struct drm_encoder *encoder)
  1251. {
  1252. struct exynos_dsi *dsi = encoder_to_dsi(encoder);
  1253. struct drm_connector *connector = &dsi->connector;
  1254. struct drm_device *drm = encoder->dev;
  1255. int ret;
  1256. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1257. ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs,
  1258. DRM_MODE_CONNECTOR_DSI);
  1259. if (ret) {
  1260. DRM_DEV_ERROR(dsi->dev,
  1261. "Failed to initialize connector with drm\n");
  1262. return ret;
  1263. }
  1264. connector->status = connector_status_disconnected;
  1265. drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
  1266. drm_connector_attach_encoder(connector, encoder);
  1267. if (!drm->registered)
  1268. return 0;
  1269. connector->funcs->reset(connector);
  1270. drm_connector_register(connector);
  1271. return 0;
  1272. }
  1273. static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
  1274. .enable = exynos_dsi_enable,
  1275. .disable = exynos_dsi_disable,
  1276. };
  1277. MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
  1278. static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
  1279. struct mipi_dsi_device *device)
  1280. {
  1281. struct exynos_dsi *dsi = host_to_dsi(host);
  1282. struct drm_encoder *encoder = &dsi->encoder;
  1283. struct drm_device *drm = encoder->dev;
  1284. struct drm_bridge *out_bridge;
  1285. out_bridge = of_drm_find_bridge(device->dev.of_node);
  1286. if (out_bridge) {
  1287. drm_bridge_attach(encoder, out_bridge, NULL, 0);
  1288. dsi->out_bridge = out_bridge;
  1289. list_splice_init(&encoder->bridge_chain, &dsi->bridge_chain);
  1290. } else {
  1291. int ret = exynos_dsi_create_connector(encoder);
  1292. if (ret) {
  1293. DRM_DEV_ERROR(dsi->dev,
  1294. "failed to create connector ret = %d\n",
  1295. ret);
  1296. drm_encoder_cleanup(encoder);
  1297. return ret;
  1298. }
  1299. dsi->panel = of_drm_find_panel(device->dev.of_node);
  1300. if (IS_ERR(dsi->panel))
  1301. dsi->panel = NULL;
  1302. else
  1303. dsi->connector.status = connector_status_connected;
  1304. }
  1305. /*
  1306. * This is a temporary solution and should be made by more generic way.
  1307. *
  1308. * If attached panel device is for command mode one, dsi should register
  1309. * TE interrupt handler.
  1310. */
  1311. if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
  1312. int ret = exynos_dsi_register_te_irq(dsi, &device->dev);
  1313. if (ret)
  1314. return ret;
  1315. }
  1316. mutex_lock(&drm->mode_config.mutex);
  1317. dsi->lanes = device->lanes;
  1318. dsi->format = device->format;
  1319. dsi->mode_flags = device->mode_flags;
  1320. exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode =
  1321. !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO);
  1322. mutex_unlock(&drm->mode_config.mutex);
  1323. if (drm->mode_config.poll_enabled)
  1324. drm_kms_helper_hotplug_event(drm);
  1325. return 0;
  1326. }
  1327. static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
  1328. struct mipi_dsi_device *device)
  1329. {
  1330. struct exynos_dsi *dsi = host_to_dsi(host);
  1331. struct drm_device *drm = dsi->encoder.dev;
  1332. if (dsi->panel) {
  1333. mutex_lock(&drm->mode_config.mutex);
  1334. exynos_dsi_disable(&dsi->encoder);
  1335. dsi->panel = NULL;
  1336. dsi->connector.status = connector_status_disconnected;
  1337. mutex_unlock(&drm->mode_config.mutex);
  1338. } else {
  1339. if (dsi->out_bridge->funcs->detach)
  1340. dsi->out_bridge->funcs->detach(dsi->out_bridge);
  1341. dsi->out_bridge = NULL;
  1342. INIT_LIST_HEAD(&dsi->bridge_chain);
  1343. }
  1344. if (drm->mode_config.poll_enabled)
  1345. drm_kms_helper_hotplug_event(drm);
  1346. exynos_dsi_unregister_te_irq(dsi);
  1347. return 0;
  1348. }
  1349. static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
  1350. const struct mipi_dsi_msg *msg)
  1351. {
  1352. struct exynos_dsi *dsi = host_to_dsi(host);
  1353. struct exynos_dsi_transfer xfer;
  1354. int ret;
  1355. if (!(dsi->state & DSIM_STATE_ENABLED))
  1356. return -EINVAL;
  1357. if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
  1358. ret = exynos_dsi_init(dsi);
  1359. if (ret)
  1360. return ret;
  1361. dsi->state |= DSIM_STATE_INITIALIZED;
  1362. }
  1363. ret = mipi_dsi_create_packet(&xfer.packet, msg);
  1364. if (ret < 0)
  1365. return ret;
  1366. xfer.rx_len = msg->rx_len;
  1367. xfer.rx_payload = msg->rx_buf;
  1368. xfer.flags = msg->flags;
  1369. ret = exynos_dsi_transfer(dsi, &xfer);
  1370. return (ret < 0) ? ret : xfer.rx_done;
  1371. }
  1372. static const struct mipi_dsi_host_ops exynos_dsi_ops = {
  1373. .attach = exynos_dsi_host_attach,
  1374. .detach = exynos_dsi_host_detach,
  1375. .transfer = exynos_dsi_host_transfer,
  1376. };
  1377. static int exynos_dsi_of_read_u32(const struct device_node *np,
  1378. const char *propname, u32 *out_value)
  1379. {
  1380. int ret = of_property_read_u32(np, propname, out_value);
  1381. if (ret < 0)
  1382. pr_err("%pOF: failed to get '%s' property\n", np, propname);
  1383. return ret;
  1384. }
  1385. enum {
  1386. DSI_PORT_IN,
  1387. DSI_PORT_OUT
  1388. };
  1389. static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
  1390. {
  1391. struct device *dev = dsi->dev;
  1392. struct device_node *node = dev->of_node;
  1393. int ret;
  1394. ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
  1395. &dsi->pll_clk_rate);
  1396. if (ret < 0)
  1397. return ret;
  1398. ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",
  1399. &dsi->burst_clk_rate);
  1400. if (ret < 0)
  1401. return ret;
  1402. ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",
  1403. &dsi->esc_clk_rate);
  1404. if (ret < 0)
  1405. return ret;
  1406. dsi->in_bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0);
  1407. return 0;
  1408. }
  1409. static int exynos_dsi_bind(struct device *dev, struct device *master,
  1410. void *data)
  1411. {
  1412. struct drm_encoder *encoder = dev_get_drvdata(dev);
  1413. struct exynos_dsi *dsi = encoder_to_dsi(encoder);
  1414. struct drm_device *drm_dev = data;
  1415. struct drm_bridge *in_bridge;
  1416. int ret;
  1417. drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS);
  1418. drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs);
  1419. ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD);
  1420. if (ret < 0)
  1421. return ret;
  1422. if (dsi->in_bridge_node) {
  1423. in_bridge = of_drm_find_bridge(dsi->in_bridge_node);
  1424. if (in_bridge)
  1425. drm_bridge_attach(encoder, in_bridge, NULL, 0);
  1426. }
  1427. return mipi_dsi_host_register(&dsi->dsi_host);
  1428. }
  1429. static void exynos_dsi_unbind(struct device *dev, struct device *master,
  1430. void *data)
  1431. {
  1432. struct drm_encoder *encoder = dev_get_drvdata(dev);
  1433. struct exynos_dsi *dsi = encoder_to_dsi(encoder);
  1434. exynos_dsi_disable(encoder);
  1435. mipi_dsi_host_unregister(&dsi->dsi_host);
  1436. }
  1437. static const struct component_ops exynos_dsi_component_ops = {
  1438. .bind = exynos_dsi_bind,
  1439. .unbind = exynos_dsi_unbind,
  1440. };
  1441. static int exynos_dsi_probe(struct platform_device *pdev)
  1442. {
  1443. struct device *dev = &pdev->dev;
  1444. struct resource *res;
  1445. struct exynos_dsi *dsi;
  1446. int ret, i;
  1447. dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
  1448. if (!dsi)
  1449. return -ENOMEM;
  1450. /* To be checked as invalid one */
  1451. dsi->te_gpio = -ENOENT;
  1452. init_completion(&dsi->completed);
  1453. spin_lock_init(&dsi->transfer_lock);
  1454. INIT_LIST_HEAD(&dsi->transfer_list);
  1455. INIT_LIST_HEAD(&dsi->bridge_chain);
  1456. dsi->dsi_host.ops = &exynos_dsi_ops;
  1457. dsi->dsi_host.dev = dev;
  1458. dsi->dev = dev;
  1459. dsi->driver_data = of_device_get_match_data(dev);
  1460. dsi->supplies[0].supply = "vddcore";
  1461. dsi->supplies[1].supply = "vddio";
  1462. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
  1463. dsi->supplies);
  1464. if (ret)
  1465. return dev_err_probe(dev, ret, "failed to get regulators\n");
  1466. dsi->clks = devm_kcalloc(dev,
  1467. dsi->driver_data->num_clks, sizeof(*dsi->clks),
  1468. GFP_KERNEL);
  1469. if (!dsi->clks)
  1470. return -ENOMEM;
  1471. for (i = 0; i < dsi->driver_data->num_clks; i++) {
  1472. dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
  1473. if (IS_ERR(dsi->clks[i])) {
  1474. if (strcmp(clk_names[i], "sclk_mipi") == 0) {
  1475. dsi->clks[i] = devm_clk_get(dev,
  1476. OLD_SCLK_MIPI_CLK_NAME);
  1477. if (!IS_ERR(dsi->clks[i]))
  1478. continue;
  1479. }
  1480. dev_info(dev, "failed to get the clock: %s\n",
  1481. clk_names[i]);
  1482. return PTR_ERR(dsi->clks[i]);
  1483. }
  1484. }
  1485. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1486. dsi->reg_base = devm_ioremap_resource(dev, res);
  1487. if (IS_ERR(dsi->reg_base)) {
  1488. dev_err(dev, "failed to remap io region\n");
  1489. return PTR_ERR(dsi->reg_base);
  1490. }
  1491. dsi->phy = devm_phy_get(dev, "dsim");
  1492. if (IS_ERR(dsi->phy)) {
  1493. dev_info(dev, "failed to get dsim phy\n");
  1494. return PTR_ERR(dsi->phy);
  1495. }
  1496. dsi->irq = platform_get_irq(pdev, 0);
  1497. if (dsi->irq < 0)
  1498. return dsi->irq;
  1499. irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
  1500. ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
  1501. exynos_dsi_irq, IRQF_ONESHOT,
  1502. dev_name(dev), dsi);
  1503. if (ret) {
  1504. dev_err(dev, "failed to request dsi irq\n");
  1505. return ret;
  1506. }
  1507. ret = exynos_dsi_parse_dt(dsi);
  1508. if (ret)
  1509. return ret;
  1510. platform_set_drvdata(pdev, &dsi->encoder);
  1511. pm_runtime_enable(dev);
  1512. ret = component_add(dev, &exynos_dsi_component_ops);
  1513. if (ret)
  1514. goto err_disable_runtime;
  1515. return 0;
  1516. err_disable_runtime:
  1517. pm_runtime_disable(dev);
  1518. of_node_put(dsi->in_bridge_node);
  1519. return ret;
  1520. }
  1521. static int exynos_dsi_remove(struct platform_device *pdev)
  1522. {
  1523. struct exynos_dsi *dsi = platform_get_drvdata(pdev);
  1524. of_node_put(dsi->in_bridge_node);
  1525. pm_runtime_disable(&pdev->dev);
  1526. component_del(&pdev->dev, &exynos_dsi_component_ops);
  1527. return 0;
  1528. }
  1529. static int __maybe_unused exynos_dsi_suspend(struct device *dev)
  1530. {
  1531. struct drm_encoder *encoder = dev_get_drvdata(dev);
  1532. struct exynos_dsi *dsi = encoder_to_dsi(encoder);
  1533. const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
  1534. int ret, i;
  1535. usleep_range(10000, 20000);
  1536. if (dsi->state & DSIM_STATE_INITIALIZED) {
  1537. dsi->state &= ~DSIM_STATE_INITIALIZED;
  1538. exynos_dsi_disable_clock(dsi);
  1539. exynos_dsi_disable_irq(dsi);
  1540. }
  1541. dsi->state &= ~DSIM_STATE_CMD_LPM;
  1542. phy_power_off(dsi->phy);
  1543. for (i = driver_data->num_clks - 1; i > -1; i--)
  1544. clk_disable_unprepare(dsi->clks[i]);
  1545. ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
  1546. if (ret < 0)
  1547. dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
  1548. return 0;
  1549. }
  1550. static int __maybe_unused exynos_dsi_resume(struct device *dev)
  1551. {
  1552. struct drm_encoder *encoder = dev_get_drvdata(dev);
  1553. struct exynos_dsi *dsi = encoder_to_dsi(encoder);
  1554. const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
  1555. int ret, i;
  1556. ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
  1557. if (ret < 0) {
  1558. dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
  1559. return ret;
  1560. }
  1561. for (i = 0; i < driver_data->num_clks; i++) {
  1562. ret = clk_prepare_enable(dsi->clks[i]);
  1563. if (ret < 0)
  1564. goto err_clk;
  1565. }
  1566. ret = phy_power_on(dsi->phy);
  1567. if (ret < 0) {
  1568. dev_err(dsi->dev, "cannot enable phy %d\n", ret);
  1569. goto err_clk;
  1570. }
  1571. return 0;
  1572. err_clk:
  1573. while (--i > -1)
  1574. clk_disable_unprepare(dsi->clks[i]);
  1575. regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
  1576. return ret;
  1577. }
  1578. static const struct dev_pm_ops exynos_dsi_pm_ops = {
  1579. SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
  1580. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1581. pm_runtime_force_resume)
  1582. };
  1583. struct platform_driver dsi_driver = {
  1584. .probe = exynos_dsi_probe,
  1585. .remove = exynos_dsi_remove,
  1586. .driver = {
  1587. .name = "exynos-dsi",
  1588. .owner = THIS_MODULE,
  1589. .pm = &exynos_dsi_pm_ops,
  1590. .of_match_table = exynos_dsi_of_match,
  1591. },
  1592. };
  1593. MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
  1594. MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
  1595. MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
  1596. MODULE_LICENSE("GPL v2");