exynos7_drm_decon.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* drivers/gpu/drm/exynos/exynos7_drm_decon.c
  3. *
  4. * Copyright (C) 2014 Samsung Electronics Co.Ltd
  5. * Authors:
  6. * Akshu Agarwal <akshua@gmail.com>
  7. * Ajay Kumar <ajaykumar.rs@samsung.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/component.h>
  11. #include <linux/kernel.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_device.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <video/of_display_timing.h>
  18. #include <video/of_videomode.h>
  19. #include <drm/drm_fourcc.h>
  20. #include <drm/drm_vblank.h>
  21. #include <drm/exynos_drm.h>
  22. #include "exynos_drm_crtc.h"
  23. #include "exynos_drm_drv.h"
  24. #include "exynos_drm_fb.h"
  25. #include "exynos_drm_plane.h"
  26. #include "regs-decon7.h"
  27. /*
  28. * DECON stands for Display and Enhancement controller.
  29. */
  30. #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  31. #define WINDOWS_NR 2
  32. struct decon_context {
  33. struct device *dev;
  34. struct drm_device *drm_dev;
  35. void *dma_priv;
  36. struct exynos_drm_crtc *crtc;
  37. struct exynos_drm_plane planes[WINDOWS_NR];
  38. struct exynos_drm_plane_config configs[WINDOWS_NR];
  39. struct clk *pclk;
  40. struct clk *aclk;
  41. struct clk *eclk;
  42. struct clk *vclk;
  43. void __iomem *regs;
  44. unsigned long irq_flags;
  45. bool i80_if;
  46. bool suspended;
  47. wait_queue_head_t wait_vsync_queue;
  48. atomic_t wait_vsync_event;
  49. struct drm_encoder *encoder;
  50. };
  51. static const struct of_device_id decon_driver_dt_match[] = {
  52. {.compatible = "samsung,exynos7-decon"},
  53. {},
  54. };
  55. MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
  56. static const uint32_t decon_formats[] = {
  57. DRM_FORMAT_RGB565,
  58. DRM_FORMAT_XRGB8888,
  59. DRM_FORMAT_XBGR8888,
  60. DRM_FORMAT_RGBX8888,
  61. DRM_FORMAT_BGRX8888,
  62. DRM_FORMAT_ARGB8888,
  63. DRM_FORMAT_ABGR8888,
  64. DRM_FORMAT_RGBA8888,
  65. DRM_FORMAT_BGRA8888,
  66. };
  67. static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  68. DRM_PLANE_TYPE_PRIMARY,
  69. DRM_PLANE_TYPE_CURSOR,
  70. };
  71. static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
  72. {
  73. struct decon_context *ctx = crtc->ctx;
  74. if (ctx->suspended)
  75. return;
  76. atomic_set(&ctx->wait_vsync_event, 1);
  77. /*
  78. * wait for DECON to signal VSYNC interrupt or return after
  79. * timeout which is set to 50ms (refresh rate of 20).
  80. */
  81. if (!wait_event_timeout(ctx->wait_vsync_queue,
  82. !atomic_read(&ctx->wait_vsync_event),
  83. HZ/20))
  84. DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
  85. }
  86. static void decon_clear_channels(struct exynos_drm_crtc *crtc)
  87. {
  88. struct decon_context *ctx = crtc->ctx;
  89. unsigned int win, ch_enabled = 0;
  90. /* Check if any channel is enabled. */
  91. for (win = 0; win < WINDOWS_NR; win++) {
  92. u32 val = readl(ctx->regs + WINCON(win));
  93. if (val & WINCONx_ENWIN) {
  94. val &= ~WINCONx_ENWIN;
  95. writel(val, ctx->regs + WINCON(win));
  96. ch_enabled = 1;
  97. }
  98. }
  99. /* Wait for vsync, as disable channel takes effect at next vsync */
  100. if (ch_enabled)
  101. decon_wait_for_vblank(ctx->crtc);
  102. }
  103. static int decon_ctx_initialize(struct decon_context *ctx,
  104. struct drm_device *drm_dev)
  105. {
  106. ctx->drm_dev = drm_dev;
  107. decon_clear_channels(ctx->crtc);
  108. return exynos_drm_register_dma(drm_dev, ctx->dev, &ctx->dma_priv);
  109. }
  110. static void decon_ctx_remove(struct decon_context *ctx)
  111. {
  112. /* detach this sub driver from iommu mapping if supported. */
  113. exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
  114. }
  115. static u32 decon_calc_clkdiv(struct decon_context *ctx,
  116. const struct drm_display_mode *mode)
  117. {
  118. unsigned long ideal_clk = mode->clock;
  119. u32 clkdiv;
  120. /* Find the clock divider value that gets us closest to ideal_clk */
  121. clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
  122. return (clkdiv < 0x100) ? clkdiv : 0xff;
  123. }
  124. static void decon_commit(struct exynos_drm_crtc *crtc)
  125. {
  126. struct decon_context *ctx = crtc->ctx;
  127. struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
  128. u32 val, clkdiv;
  129. if (ctx->suspended)
  130. return;
  131. /* nothing to do if we haven't set the mode yet */
  132. if (mode->htotal == 0 || mode->vtotal == 0)
  133. return;
  134. if (!ctx->i80_if) {
  135. int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
  136. /* setup vertical timing values. */
  137. vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  138. vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
  139. vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
  140. val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
  141. writel(val, ctx->regs + VIDTCON0);
  142. val = VIDTCON1_VSPW(vsync_len - 1);
  143. writel(val, ctx->regs + VIDTCON1);
  144. /* setup horizontal timing values. */
  145. hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  146. hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
  147. hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
  148. /* setup horizontal timing values. */
  149. val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
  150. writel(val, ctx->regs + VIDTCON2);
  151. val = VIDTCON3_HSPW(hsync_len - 1);
  152. writel(val, ctx->regs + VIDTCON3);
  153. }
  154. /* setup horizontal and vertical display size. */
  155. val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
  156. VIDTCON4_HOZVAL(mode->hdisplay - 1);
  157. writel(val, ctx->regs + VIDTCON4);
  158. writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
  159. /*
  160. * fields of register with prefix '_F' would be updated
  161. * at vsync(same as dma start)
  162. */
  163. val = VIDCON0_ENVID | VIDCON0_ENVID_F;
  164. writel(val, ctx->regs + VIDCON0);
  165. clkdiv = decon_calc_clkdiv(ctx, mode);
  166. if (clkdiv > 1) {
  167. val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
  168. writel(val, ctx->regs + VCLKCON1);
  169. writel(val, ctx->regs + VCLKCON2);
  170. }
  171. val = readl(ctx->regs + DECON_UPDATE);
  172. val |= DECON_UPDATE_STANDALONE_F;
  173. writel(val, ctx->regs + DECON_UPDATE);
  174. }
  175. static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  176. {
  177. struct decon_context *ctx = crtc->ctx;
  178. u32 val;
  179. if (ctx->suspended)
  180. return -EPERM;
  181. if (!test_and_set_bit(0, &ctx->irq_flags)) {
  182. val = readl(ctx->regs + VIDINTCON0);
  183. val |= VIDINTCON0_INT_ENABLE;
  184. if (!ctx->i80_if) {
  185. val |= VIDINTCON0_INT_FRAME;
  186. val &= ~VIDINTCON0_FRAMESEL0_MASK;
  187. val |= VIDINTCON0_FRAMESEL0_VSYNC;
  188. }
  189. writel(val, ctx->regs + VIDINTCON0);
  190. }
  191. return 0;
  192. }
  193. static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
  194. {
  195. struct decon_context *ctx = crtc->ctx;
  196. u32 val;
  197. if (ctx->suspended)
  198. return;
  199. if (test_and_clear_bit(0, &ctx->irq_flags)) {
  200. val = readl(ctx->regs + VIDINTCON0);
  201. val &= ~VIDINTCON0_INT_ENABLE;
  202. if (!ctx->i80_if)
  203. val &= ~VIDINTCON0_INT_FRAME;
  204. writel(val, ctx->regs + VIDINTCON0);
  205. }
  206. }
  207. static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
  208. struct drm_framebuffer *fb)
  209. {
  210. unsigned long val;
  211. int padding;
  212. val = readl(ctx->regs + WINCON(win));
  213. val &= ~WINCONx_BPPMODE_MASK;
  214. switch (fb->format->format) {
  215. case DRM_FORMAT_RGB565:
  216. val |= WINCONx_BPPMODE_16BPP_565;
  217. val |= WINCONx_BURSTLEN_16WORD;
  218. break;
  219. case DRM_FORMAT_XRGB8888:
  220. val |= WINCONx_BPPMODE_24BPP_xRGB;
  221. val |= WINCONx_BURSTLEN_16WORD;
  222. break;
  223. case DRM_FORMAT_XBGR8888:
  224. val |= WINCONx_BPPMODE_24BPP_xBGR;
  225. val |= WINCONx_BURSTLEN_16WORD;
  226. break;
  227. case DRM_FORMAT_RGBX8888:
  228. val |= WINCONx_BPPMODE_24BPP_RGBx;
  229. val |= WINCONx_BURSTLEN_16WORD;
  230. break;
  231. case DRM_FORMAT_BGRX8888:
  232. val |= WINCONx_BPPMODE_24BPP_BGRx;
  233. val |= WINCONx_BURSTLEN_16WORD;
  234. break;
  235. case DRM_FORMAT_ARGB8888:
  236. val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
  237. WINCONx_ALPHA_SEL;
  238. val |= WINCONx_BURSTLEN_16WORD;
  239. break;
  240. case DRM_FORMAT_ABGR8888:
  241. val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
  242. WINCONx_ALPHA_SEL;
  243. val |= WINCONx_BURSTLEN_16WORD;
  244. break;
  245. case DRM_FORMAT_RGBA8888:
  246. val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
  247. WINCONx_ALPHA_SEL;
  248. val |= WINCONx_BURSTLEN_16WORD;
  249. break;
  250. case DRM_FORMAT_BGRA8888:
  251. default:
  252. val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
  253. WINCONx_ALPHA_SEL;
  254. val |= WINCONx_BURSTLEN_16WORD;
  255. break;
  256. }
  257. DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %d\n", fb->format->cpp[0]);
  258. /*
  259. * In case of exynos, setting dma-burst to 16Word causes permanent
  260. * tearing for very small buffers, e.g. cursor buffer. Burst Mode
  261. * switching which is based on plane size is not recommended as
  262. * plane size varies a lot towards the end of the screen and rapid
  263. * movement causes unstable DMA which results into iommu crash/tear.
  264. */
  265. padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;
  266. if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
  267. val &= ~WINCONx_BURSTLEN_MASK;
  268. val |= WINCONx_BURSTLEN_8WORD;
  269. }
  270. writel(val, ctx->regs + WINCON(win));
  271. }
  272. static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
  273. {
  274. unsigned int keycon0 = 0, keycon1 = 0;
  275. keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
  276. WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
  277. keycon1 = WxKEYCON1_COLVAL(0xffffffff);
  278. writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
  279. writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
  280. }
  281. /**
  282. * shadow_protect_win() - disable updating values from shadow registers at vsync
  283. *
  284. * @win: window to protect registers for
  285. * @protect: 1 to protect (disable updates)
  286. */
  287. static void decon_shadow_protect_win(struct decon_context *ctx,
  288. unsigned int win, bool protect)
  289. {
  290. u32 bits, val;
  291. bits = SHADOWCON_WINx_PROTECT(win);
  292. val = readl(ctx->regs + SHADOWCON);
  293. if (protect)
  294. val |= bits;
  295. else
  296. val &= ~bits;
  297. writel(val, ctx->regs + SHADOWCON);
  298. }
  299. static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
  300. {
  301. struct decon_context *ctx = crtc->ctx;
  302. int i;
  303. if (ctx->suspended)
  304. return;
  305. for (i = 0; i < WINDOWS_NR; i++)
  306. decon_shadow_protect_win(ctx, i, true);
  307. }
  308. static void decon_update_plane(struct exynos_drm_crtc *crtc,
  309. struct exynos_drm_plane *plane)
  310. {
  311. struct exynos_drm_plane_state *state =
  312. to_exynos_plane_state(plane->base.state);
  313. struct decon_context *ctx = crtc->ctx;
  314. struct drm_framebuffer *fb = state->base.fb;
  315. int padding;
  316. unsigned long val, alpha;
  317. unsigned int last_x;
  318. unsigned int last_y;
  319. unsigned int win = plane->index;
  320. unsigned int cpp = fb->format->cpp[0];
  321. unsigned int pitch = fb->pitches[0];
  322. if (ctx->suspended)
  323. return;
  324. /*
  325. * SHADOWCON/PRTCON register is used for enabling timing.
  326. *
  327. * for example, once only width value of a register is set,
  328. * if the dma is started then decon hardware could malfunction so
  329. * with protect window setting, the register fields with prefix '_F'
  330. * wouldn't be updated at vsync also but updated once unprotect window
  331. * is set.
  332. */
  333. /* buffer start address */
  334. val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
  335. writel(val, ctx->regs + VIDW_BUF_START(win));
  336. padding = (pitch / cpp) - fb->width;
  337. /* buffer size */
  338. writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
  339. writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
  340. /* offset from the start of the buffer to read */
  341. writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
  342. writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
  343. DRM_DEV_DEBUG_KMS(ctx->dev, "start addr = 0x%lx\n",
  344. (unsigned long)val);
  345. DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
  346. state->crtc.w, state->crtc.h);
  347. val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
  348. VIDOSDxA_TOPLEFT_Y(state->crtc.y);
  349. writel(val, ctx->regs + VIDOSD_A(win));
  350. last_x = state->crtc.x + state->crtc.w;
  351. if (last_x)
  352. last_x--;
  353. last_y = state->crtc.y + state->crtc.h;
  354. if (last_y)
  355. last_y--;
  356. val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
  357. writel(val, ctx->regs + VIDOSD_B(win));
  358. DRM_DEV_DEBUG_KMS(ctx->dev, "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
  359. state->crtc.x, state->crtc.y, last_x, last_y);
  360. /* OSD alpha */
  361. alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
  362. VIDOSDxC_ALPHA0_G_F(0x0) |
  363. VIDOSDxC_ALPHA0_B_F(0x0);
  364. writel(alpha, ctx->regs + VIDOSD_C(win));
  365. alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
  366. VIDOSDxD_ALPHA1_G_F(0xff) |
  367. VIDOSDxD_ALPHA1_B_F(0xff);
  368. writel(alpha, ctx->regs + VIDOSD_D(win));
  369. decon_win_set_pixfmt(ctx, win, fb);
  370. /* hardware window 0 doesn't support color key. */
  371. if (win != 0)
  372. decon_win_set_colkey(ctx, win);
  373. /* wincon */
  374. val = readl(ctx->regs + WINCON(win));
  375. val |= WINCONx_TRIPLE_BUF_MODE;
  376. val |= WINCONx_ENWIN;
  377. writel(val, ctx->regs + WINCON(win));
  378. /* Enable DMA channel and unprotect windows */
  379. decon_shadow_protect_win(ctx, win, false);
  380. val = readl(ctx->regs + DECON_UPDATE);
  381. val |= DECON_UPDATE_STANDALONE_F;
  382. writel(val, ctx->regs + DECON_UPDATE);
  383. }
  384. static void decon_disable_plane(struct exynos_drm_crtc *crtc,
  385. struct exynos_drm_plane *plane)
  386. {
  387. struct decon_context *ctx = crtc->ctx;
  388. unsigned int win = plane->index;
  389. u32 val;
  390. if (ctx->suspended)
  391. return;
  392. /* protect windows */
  393. decon_shadow_protect_win(ctx, win, true);
  394. /* wincon */
  395. val = readl(ctx->regs + WINCON(win));
  396. val &= ~WINCONx_ENWIN;
  397. writel(val, ctx->regs + WINCON(win));
  398. val = readl(ctx->regs + DECON_UPDATE);
  399. val |= DECON_UPDATE_STANDALONE_F;
  400. writel(val, ctx->regs + DECON_UPDATE);
  401. }
  402. static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
  403. {
  404. struct decon_context *ctx = crtc->ctx;
  405. int i;
  406. if (ctx->suspended)
  407. return;
  408. for (i = 0; i < WINDOWS_NR; i++)
  409. decon_shadow_protect_win(ctx, i, false);
  410. exynos_crtc_handle_event(crtc);
  411. }
  412. static void decon_init(struct decon_context *ctx)
  413. {
  414. u32 val;
  415. writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
  416. val = VIDOUTCON0_DISP_IF_0_ON;
  417. if (!ctx->i80_if)
  418. val |= VIDOUTCON0_RGBIF;
  419. writel(val, ctx->regs + VIDOUTCON0);
  420. writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
  421. if (!ctx->i80_if)
  422. writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
  423. }
  424. static void decon_atomic_enable(struct exynos_drm_crtc *crtc)
  425. {
  426. struct decon_context *ctx = crtc->ctx;
  427. if (!ctx->suspended)
  428. return;
  429. pm_runtime_get_sync(ctx->dev);
  430. decon_init(ctx);
  431. /* if vblank was enabled status, enable it again. */
  432. if (test_and_clear_bit(0, &ctx->irq_flags))
  433. decon_enable_vblank(ctx->crtc);
  434. decon_commit(ctx->crtc);
  435. ctx->suspended = false;
  436. }
  437. static void decon_atomic_disable(struct exynos_drm_crtc *crtc)
  438. {
  439. struct decon_context *ctx = crtc->ctx;
  440. int i;
  441. if (ctx->suspended)
  442. return;
  443. /*
  444. * We need to make sure that all windows are disabled before we
  445. * suspend that connector. Otherwise we might try to scan from
  446. * a destroyed buffer later.
  447. */
  448. for (i = 0; i < WINDOWS_NR; i++)
  449. decon_disable_plane(crtc, &ctx->planes[i]);
  450. pm_runtime_put_sync(ctx->dev);
  451. ctx->suspended = true;
  452. }
  453. static const struct exynos_drm_crtc_ops decon_crtc_ops = {
  454. .atomic_enable = decon_atomic_enable,
  455. .atomic_disable = decon_atomic_disable,
  456. .enable_vblank = decon_enable_vblank,
  457. .disable_vblank = decon_disable_vblank,
  458. .atomic_begin = decon_atomic_begin,
  459. .update_plane = decon_update_plane,
  460. .disable_plane = decon_disable_plane,
  461. .atomic_flush = decon_atomic_flush,
  462. };
  463. static irqreturn_t decon_irq_handler(int irq, void *dev_id)
  464. {
  465. struct decon_context *ctx = (struct decon_context *)dev_id;
  466. u32 val, clear_bit;
  467. val = readl(ctx->regs + VIDINTCON1);
  468. clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
  469. if (val & clear_bit)
  470. writel(clear_bit, ctx->regs + VIDINTCON1);
  471. /* check the crtc is detached already from encoder */
  472. if (!ctx->drm_dev)
  473. goto out;
  474. if (!ctx->i80_if) {
  475. drm_crtc_handle_vblank(&ctx->crtc->base);
  476. /* set wait vsync event to zero and wake up queue. */
  477. if (atomic_read(&ctx->wait_vsync_event)) {
  478. atomic_set(&ctx->wait_vsync_event, 0);
  479. wake_up(&ctx->wait_vsync_queue);
  480. }
  481. }
  482. out:
  483. return IRQ_HANDLED;
  484. }
  485. static int decon_bind(struct device *dev, struct device *master, void *data)
  486. {
  487. struct decon_context *ctx = dev_get_drvdata(dev);
  488. struct drm_device *drm_dev = data;
  489. struct exynos_drm_plane *exynos_plane;
  490. unsigned int i;
  491. int ret;
  492. ret = decon_ctx_initialize(ctx, drm_dev);
  493. if (ret) {
  494. DRM_DEV_ERROR(dev, "decon_ctx_initialize failed.\n");
  495. return ret;
  496. }
  497. for (i = 0; i < WINDOWS_NR; i++) {
  498. ctx->configs[i].pixel_formats = decon_formats;
  499. ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
  500. ctx->configs[i].zpos = i;
  501. ctx->configs[i].type = decon_win_types[i];
  502. ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
  503. &ctx->configs[i]);
  504. if (ret)
  505. return ret;
  506. }
  507. exynos_plane = &ctx->planes[DEFAULT_WIN];
  508. ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
  509. EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx);
  510. if (IS_ERR(ctx->crtc)) {
  511. decon_ctx_remove(ctx);
  512. return PTR_ERR(ctx->crtc);
  513. }
  514. if (ctx->encoder)
  515. exynos_dpi_bind(drm_dev, ctx->encoder);
  516. return 0;
  517. }
  518. static void decon_unbind(struct device *dev, struct device *master,
  519. void *data)
  520. {
  521. struct decon_context *ctx = dev_get_drvdata(dev);
  522. decon_atomic_disable(ctx->crtc);
  523. if (ctx->encoder)
  524. exynos_dpi_remove(ctx->encoder);
  525. decon_ctx_remove(ctx);
  526. }
  527. static const struct component_ops decon_component_ops = {
  528. .bind = decon_bind,
  529. .unbind = decon_unbind,
  530. };
  531. static int decon_probe(struct platform_device *pdev)
  532. {
  533. struct device *dev = &pdev->dev;
  534. struct decon_context *ctx;
  535. struct device_node *i80_if_timings;
  536. struct resource *res;
  537. int ret;
  538. if (!dev->of_node)
  539. return -ENODEV;
  540. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  541. if (!ctx)
  542. return -ENOMEM;
  543. ctx->dev = dev;
  544. ctx->suspended = true;
  545. i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
  546. if (i80_if_timings)
  547. ctx->i80_if = true;
  548. of_node_put(i80_if_timings);
  549. ctx->regs = of_iomap(dev->of_node, 0);
  550. if (!ctx->regs)
  551. return -ENOMEM;
  552. ctx->pclk = devm_clk_get(dev, "pclk_decon0");
  553. if (IS_ERR(ctx->pclk)) {
  554. dev_err(dev, "failed to get bus clock pclk\n");
  555. ret = PTR_ERR(ctx->pclk);
  556. goto err_iounmap;
  557. }
  558. ctx->aclk = devm_clk_get(dev, "aclk_decon0");
  559. if (IS_ERR(ctx->aclk)) {
  560. dev_err(dev, "failed to get bus clock aclk\n");
  561. ret = PTR_ERR(ctx->aclk);
  562. goto err_iounmap;
  563. }
  564. ctx->eclk = devm_clk_get(dev, "decon0_eclk");
  565. if (IS_ERR(ctx->eclk)) {
  566. dev_err(dev, "failed to get eclock\n");
  567. ret = PTR_ERR(ctx->eclk);
  568. goto err_iounmap;
  569. }
  570. ctx->vclk = devm_clk_get(dev, "decon0_vclk");
  571. if (IS_ERR(ctx->vclk)) {
  572. dev_err(dev, "failed to get vclock\n");
  573. ret = PTR_ERR(ctx->vclk);
  574. goto err_iounmap;
  575. }
  576. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
  577. ctx->i80_if ? "lcd_sys" : "vsync");
  578. if (!res) {
  579. dev_err(dev, "irq request failed.\n");
  580. ret = -ENXIO;
  581. goto err_iounmap;
  582. }
  583. ret = devm_request_irq(dev, res->start, decon_irq_handler,
  584. 0, "drm_decon", ctx);
  585. if (ret) {
  586. dev_err(dev, "irq request failed.\n");
  587. goto err_iounmap;
  588. }
  589. init_waitqueue_head(&ctx->wait_vsync_queue);
  590. atomic_set(&ctx->wait_vsync_event, 0);
  591. platform_set_drvdata(pdev, ctx);
  592. ctx->encoder = exynos_dpi_probe(dev);
  593. if (IS_ERR(ctx->encoder)) {
  594. ret = PTR_ERR(ctx->encoder);
  595. goto err_iounmap;
  596. }
  597. pm_runtime_enable(dev);
  598. ret = component_add(dev, &decon_component_ops);
  599. if (ret)
  600. goto err_disable_pm_runtime;
  601. return ret;
  602. err_disable_pm_runtime:
  603. pm_runtime_disable(dev);
  604. err_iounmap:
  605. iounmap(ctx->regs);
  606. return ret;
  607. }
  608. static int decon_remove(struct platform_device *pdev)
  609. {
  610. struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
  611. pm_runtime_disable(&pdev->dev);
  612. iounmap(ctx->regs);
  613. component_del(&pdev->dev, &decon_component_ops);
  614. return 0;
  615. }
  616. #ifdef CONFIG_PM
  617. static int exynos7_decon_suspend(struct device *dev)
  618. {
  619. struct decon_context *ctx = dev_get_drvdata(dev);
  620. clk_disable_unprepare(ctx->vclk);
  621. clk_disable_unprepare(ctx->eclk);
  622. clk_disable_unprepare(ctx->aclk);
  623. clk_disable_unprepare(ctx->pclk);
  624. return 0;
  625. }
  626. static int exynos7_decon_resume(struct device *dev)
  627. {
  628. struct decon_context *ctx = dev_get_drvdata(dev);
  629. int ret;
  630. ret = clk_prepare_enable(ctx->pclk);
  631. if (ret < 0) {
  632. DRM_DEV_ERROR(dev, "Failed to prepare_enable the pclk [%d]\n",
  633. ret);
  634. return ret;
  635. }
  636. ret = clk_prepare_enable(ctx->aclk);
  637. if (ret < 0) {
  638. DRM_DEV_ERROR(dev, "Failed to prepare_enable the aclk [%d]\n",
  639. ret);
  640. return ret;
  641. }
  642. ret = clk_prepare_enable(ctx->eclk);
  643. if (ret < 0) {
  644. DRM_DEV_ERROR(dev, "Failed to prepare_enable the eclk [%d]\n",
  645. ret);
  646. return ret;
  647. }
  648. ret = clk_prepare_enable(ctx->vclk);
  649. if (ret < 0) {
  650. DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n",
  651. ret);
  652. return ret;
  653. }
  654. return 0;
  655. }
  656. #endif
  657. static const struct dev_pm_ops exynos7_decon_pm_ops = {
  658. SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
  659. NULL)
  660. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  661. pm_runtime_force_resume)
  662. };
  663. struct platform_driver decon_driver = {
  664. .probe = decon_probe,
  665. .remove = decon_remove,
  666. .driver = {
  667. .name = "exynos-decon",
  668. .pm = &exynos7_decon_pm_ops,
  669. .of_match_table = decon_driver_dt_match,
  670. },
  671. };