exynos5433_drm_decon.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* drivers/gpu/drm/exynos5433_drm_decon.c
  3. *
  4. * Copyright (C) 2015 Samsung Electronics Co.Ltd
  5. * Authors:
  6. * Joonyoung Shim <jy0922.shim@samsung.com>
  7. * Hyungwon Hwang <human.hwang@samsung.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/component.h>
  11. #include <linux/iopoll.h>
  12. #include <linux/irq.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/of_device.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/regmap.h>
  19. #include <drm/drm_fourcc.h>
  20. #include <drm/drm_vblank.h>
  21. #include "exynos_drm_crtc.h"
  22. #include "exynos_drm_drv.h"
  23. #include "exynos_drm_fb.h"
  24. #include "exynos_drm_plane.h"
  25. #include "regs-decon5433.h"
  26. #define DSD_CFG_MUX 0x1004
  27. #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  28. #define WINDOWS_NR 5
  29. #define PRIMARY_WIN 2
  30. #define CURSON_WIN 4
  31. #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  32. #define I80_HW_TRG (1 << 0)
  33. #define IFTYPE_HDMI (1 << 1)
  34. static const char * const decon_clks_name[] = {
  35. "pclk",
  36. "aclk_decon",
  37. "aclk_smmu_decon0x",
  38. "aclk_xiu_decon0x",
  39. "pclk_smmu_decon0x",
  40. "aclk_smmu_decon1x",
  41. "aclk_xiu_decon1x",
  42. "pclk_smmu_decon1x",
  43. "sclk_decon_vclk",
  44. "sclk_decon_eclk",
  45. };
  46. struct decon_context {
  47. struct device *dev;
  48. struct drm_device *drm_dev;
  49. void *dma_priv;
  50. struct exynos_drm_crtc *crtc;
  51. struct exynos_drm_plane planes[WINDOWS_NR];
  52. struct exynos_drm_plane_config configs[WINDOWS_NR];
  53. void __iomem *addr;
  54. struct regmap *sysreg;
  55. struct clk *clks[ARRAY_SIZE(decon_clks_name)];
  56. unsigned int irq;
  57. unsigned int irq_vsync;
  58. unsigned int irq_lcd_sys;
  59. unsigned int te_irq;
  60. unsigned long out_type;
  61. int first_win;
  62. spinlock_t vblank_lock;
  63. u32 frame_id;
  64. };
  65. static const uint32_t decon_formats[] = {
  66. DRM_FORMAT_XRGB1555,
  67. DRM_FORMAT_RGB565,
  68. DRM_FORMAT_XRGB8888,
  69. DRM_FORMAT_ARGB8888,
  70. };
  71. static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  72. [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
  73. [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
  74. };
  75. static const unsigned int capabilities[WINDOWS_NR] = {
  76. 0,
  77. EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  78. EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  79. EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  80. EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  81. };
  82. static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  83. u32 val)
  84. {
  85. val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  86. writel(val, ctx->addr + reg);
  87. }
  88. static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  89. {
  90. struct decon_context *ctx = crtc->ctx;
  91. u32 val;
  92. val = VIDINTCON0_INTEN;
  93. if (crtc->i80_mode)
  94. val |= VIDINTCON0_FRAMEDONE;
  95. else
  96. val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
  97. writel(val, ctx->addr + DECON_VIDINTCON0);
  98. enable_irq(ctx->irq);
  99. if (!(ctx->out_type & I80_HW_TRG))
  100. enable_irq(ctx->te_irq);
  101. return 0;
  102. }
  103. static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
  104. {
  105. struct decon_context *ctx = crtc->ctx;
  106. if (!(ctx->out_type & I80_HW_TRG))
  107. disable_irq_nosync(ctx->te_irq);
  108. disable_irq_nosync(ctx->irq);
  109. writel(0, ctx->addr + DECON_VIDINTCON0);
  110. }
  111. /* return number of starts/ends of frame transmissions since reset */
  112. static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
  113. {
  114. u32 frm, pfrm, status, cnt = 2;
  115. /* To get consistent result repeat read until frame id is stable.
  116. * Usually the loop will be executed once, in rare cases when the loop
  117. * is executed at frame change time 2nd pass will be needed.
  118. */
  119. frm = readl(ctx->addr + DECON_CRFMID);
  120. do {
  121. status = readl(ctx->addr + DECON_VIDCON1);
  122. pfrm = frm;
  123. frm = readl(ctx->addr + DECON_CRFMID);
  124. } while (frm != pfrm && --cnt);
  125. /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
  126. * of RGB, it should be taken into account.
  127. */
  128. if (!frm)
  129. return 0;
  130. switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
  131. case VIDCON1_VSTATUS_VS:
  132. if (!(ctx->crtc->i80_mode))
  133. --frm;
  134. break;
  135. case VIDCON1_VSTATUS_BP:
  136. --frm;
  137. break;
  138. case VIDCON1_I80_ACTIVE:
  139. case VIDCON1_VSTATUS_AC:
  140. if (end)
  141. --frm;
  142. break;
  143. default:
  144. break;
  145. }
  146. return frm;
  147. }
  148. static void decon_setup_trigger(struct decon_context *ctx)
  149. {
  150. if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
  151. return;
  152. if (!(ctx->out_type & I80_HW_TRG)) {
  153. writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
  154. TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
  155. ctx->addr + DECON_TRIGCON);
  156. return;
  157. }
  158. writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
  159. | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
  160. if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
  161. DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
  162. DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n");
  163. }
  164. static void decon_commit(struct exynos_drm_crtc *crtc)
  165. {
  166. struct decon_context *ctx = crtc->ctx;
  167. struct drm_display_mode *m = &crtc->base.mode;
  168. bool interlaced = false;
  169. u32 val;
  170. if (ctx->out_type & IFTYPE_HDMI) {
  171. m->crtc_hsync_start = m->crtc_hdisplay + 10;
  172. m->crtc_hsync_end = m->crtc_htotal - 92;
  173. m->crtc_vsync_start = m->crtc_vdisplay + 1;
  174. m->crtc_vsync_end = m->crtc_vsync_start + 1;
  175. if (m->flags & DRM_MODE_FLAG_INTERLACE)
  176. interlaced = true;
  177. }
  178. decon_setup_trigger(ctx);
  179. /* lcd on and use command if */
  180. val = VIDOUT_LCD_ON;
  181. if (interlaced)
  182. val |= VIDOUT_INTERLACE_EN_F;
  183. if (crtc->i80_mode) {
  184. val |= VIDOUT_COMMAND_IF;
  185. } else {
  186. val |= VIDOUT_RGB_IF;
  187. }
  188. writel(val, ctx->addr + DECON_VIDOUTCON0);
  189. if (interlaced)
  190. val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
  191. VIDTCON2_HOZVAL(m->hdisplay - 1);
  192. else
  193. val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
  194. VIDTCON2_HOZVAL(m->hdisplay - 1);
  195. writel(val, ctx->addr + DECON_VIDTCON2);
  196. if (!crtc->i80_mode) {
  197. int vbp = m->crtc_vtotal - m->crtc_vsync_end;
  198. int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
  199. if (interlaced)
  200. vbp = vbp / 2 - 1;
  201. val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
  202. writel(val, ctx->addr + DECON_VIDTCON00);
  203. val = VIDTCON01_VSPW_F(
  204. m->crtc_vsync_end - m->crtc_vsync_start - 1);
  205. writel(val, ctx->addr + DECON_VIDTCON01);
  206. val = VIDTCON10_HBPD_F(
  207. m->crtc_htotal - m->crtc_hsync_end - 1) |
  208. VIDTCON10_HFPD_F(
  209. m->crtc_hsync_start - m->crtc_hdisplay - 1);
  210. writel(val, ctx->addr + DECON_VIDTCON10);
  211. val = VIDTCON11_HSPW_F(
  212. m->crtc_hsync_end - m->crtc_hsync_start - 1);
  213. writel(val, ctx->addr + DECON_VIDTCON11);
  214. }
  215. /* enable output and display signal */
  216. decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
  217. decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
  218. }
  219. static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win,
  220. unsigned int alpha, unsigned int pixel_alpha)
  221. {
  222. u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf);
  223. u32 val = 0;
  224. switch (pixel_alpha) {
  225. case DRM_MODE_BLEND_PIXEL_NONE:
  226. case DRM_MODE_BLEND_COVERAGE:
  227. val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A);
  228. val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
  229. break;
  230. case DRM_MODE_BLEND_PREMULTI:
  231. default:
  232. if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
  233. val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0);
  234. val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
  235. } else {
  236. val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE);
  237. val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
  238. }
  239. break;
  240. }
  241. decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val);
  242. }
  243. static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
  244. unsigned int alpha, unsigned int pixel_alpha)
  245. {
  246. u32 win_alpha = alpha >> 8;
  247. u32 val = 0;
  248. switch (pixel_alpha) {
  249. case DRM_MODE_BLEND_PIXEL_NONE:
  250. break;
  251. case DRM_MODE_BLEND_COVERAGE:
  252. case DRM_MODE_BLEND_PREMULTI:
  253. default:
  254. val |= WINCONx_ALPHA_SEL_F;
  255. val |= WINCONx_BLD_PIX_F;
  256. val |= WINCONx_ALPHA_MUL_F;
  257. break;
  258. }
  259. decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val);
  260. if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
  261. val = VIDOSD_Wx_ALPHA_R_F(win_alpha) |
  262. VIDOSD_Wx_ALPHA_G_F(win_alpha) |
  263. VIDOSD_Wx_ALPHA_B_F(win_alpha);
  264. decon_set_bits(ctx, DECON_VIDOSDxC(win),
  265. VIDOSDxC_ALPHA0_RGB_MASK, val);
  266. decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW);
  267. }
  268. }
  269. static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
  270. struct drm_framebuffer *fb)
  271. {
  272. struct exynos_drm_plane plane = ctx->planes[win];
  273. struct exynos_drm_plane_state *state =
  274. to_exynos_plane_state(plane.base.state);
  275. unsigned int alpha = state->base.alpha;
  276. unsigned int pixel_alpha;
  277. unsigned long val;
  278. if (fb->format->has_alpha)
  279. pixel_alpha = state->base.pixel_blend_mode;
  280. else
  281. pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
  282. val = readl(ctx->addr + DECON_WINCONx(win));
  283. val &= WINCONx_ENWIN_F;
  284. switch (fb->format->format) {
  285. case DRM_FORMAT_XRGB1555:
  286. val |= WINCONx_BPPMODE_16BPP_I1555;
  287. val |= WINCONx_HAWSWP_F;
  288. val |= WINCONx_BURSTLEN_16WORD;
  289. break;
  290. case DRM_FORMAT_RGB565:
  291. val |= WINCONx_BPPMODE_16BPP_565;
  292. val |= WINCONx_HAWSWP_F;
  293. val |= WINCONx_BURSTLEN_16WORD;
  294. break;
  295. case DRM_FORMAT_XRGB8888:
  296. val |= WINCONx_BPPMODE_24BPP_888;
  297. val |= WINCONx_WSWP_F;
  298. val |= WINCONx_BURSTLEN_16WORD;
  299. break;
  300. case DRM_FORMAT_ARGB8888:
  301. default:
  302. val |= WINCONx_BPPMODE_32BPP_A8888;
  303. val |= WINCONx_WSWP_F;
  304. val |= WINCONx_BURSTLEN_16WORD;
  305. break;
  306. }
  307. DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]);
  308. /*
  309. * In case of exynos, setting dma-burst to 16Word causes permanent
  310. * tearing for very small buffers, e.g. cursor buffer. Burst Mode
  311. * switching which is based on plane size is not recommended as
  312. * plane size varies a lot towards the end of the screen and rapid
  313. * movement causes unstable DMA which results into iommu crash/tear.
  314. */
  315. if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
  316. val &= ~WINCONx_BURSTLEN_MASK;
  317. val |= WINCONx_BURSTLEN_8WORD;
  318. }
  319. decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val);
  320. if (win > 0) {
  321. decon_win_set_bldmod(ctx, win, alpha, pixel_alpha);
  322. decon_win_set_bldeq(ctx, win, alpha, pixel_alpha);
  323. }
  324. }
  325. static void decon_shadow_protect(struct decon_context *ctx, bool protect)
  326. {
  327. decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
  328. protect ? ~0 : 0);
  329. }
  330. static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
  331. {
  332. struct decon_context *ctx = crtc->ctx;
  333. decon_shadow_protect(ctx, true);
  334. }
  335. #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
  336. #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
  337. #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
  338. static void decon_update_plane(struct exynos_drm_crtc *crtc,
  339. struct exynos_drm_plane *plane)
  340. {
  341. struct exynos_drm_plane_state *state =
  342. to_exynos_plane_state(plane->base.state);
  343. struct decon_context *ctx = crtc->ctx;
  344. struct drm_framebuffer *fb = state->base.fb;
  345. unsigned int win = plane->index;
  346. unsigned int cpp = fb->format->cpp[0];
  347. unsigned int pitch = fb->pitches[0];
  348. dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
  349. u32 val;
  350. if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
  351. val = COORDINATE_X(state->crtc.x) |
  352. COORDINATE_Y(state->crtc.y / 2);
  353. writel(val, ctx->addr + DECON_VIDOSDxA(win));
  354. val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
  355. COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
  356. writel(val, ctx->addr + DECON_VIDOSDxB(win));
  357. } else {
  358. val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
  359. writel(val, ctx->addr + DECON_VIDOSDxA(win));
  360. val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
  361. COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
  362. writel(val, ctx->addr + DECON_VIDOSDxB(win));
  363. }
  364. val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
  365. VIDOSD_Wx_ALPHA_B_F(0xff);
  366. writel(val, ctx->addr + DECON_VIDOSDxC(win));
  367. val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
  368. VIDOSD_Wx_ALPHA_B_F(0x0);
  369. writel(val, ctx->addr + DECON_VIDOSDxD(win));
  370. writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
  371. val = dma_addr + pitch * state->src.h;
  372. writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
  373. if (!(ctx->out_type & IFTYPE_HDMI))
  374. val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
  375. | BIT_VAL(state->crtc.w * cpp, 13, 0);
  376. else
  377. val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
  378. | BIT_VAL(state->crtc.w * cpp, 14, 0);
  379. writel(val, ctx->addr + DECON_VIDW0xADD2(win));
  380. decon_win_set_pixfmt(ctx, win, fb);
  381. /* window enable */
  382. decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
  383. }
  384. static void decon_disable_plane(struct exynos_drm_crtc *crtc,
  385. struct exynos_drm_plane *plane)
  386. {
  387. struct decon_context *ctx = crtc->ctx;
  388. unsigned int win = plane->index;
  389. decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
  390. }
  391. static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
  392. {
  393. struct decon_context *ctx = crtc->ctx;
  394. unsigned long flags;
  395. spin_lock_irqsave(&ctx->vblank_lock, flags);
  396. decon_shadow_protect(ctx, false);
  397. decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
  398. ctx->frame_id = decon_get_frame_count(ctx, true);
  399. exynos_crtc_handle_event(crtc);
  400. spin_unlock_irqrestore(&ctx->vblank_lock, flags);
  401. }
  402. static void decon_swreset(struct decon_context *ctx)
  403. {
  404. unsigned long flags;
  405. u32 val;
  406. int ret;
  407. writel(0, ctx->addr + DECON_VIDCON0);
  408. readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
  409. ~val & VIDCON0_STOP_STATUS, 12, 20000);
  410. writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
  411. ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
  412. ~val & VIDCON0_SWRESET, 12, 20000);
  413. WARN(ret < 0, "failed to software reset DECON\n");
  414. spin_lock_irqsave(&ctx->vblank_lock, flags);
  415. ctx->frame_id = 0;
  416. spin_unlock_irqrestore(&ctx->vblank_lock, flags);
  417. if (!(ctx->out_type & IFTYPE_HDMI))
  418. return;
  419. writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
  420. decon_set_bits(ctx, DECON_CMU,
  421. CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
  422. writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
  423. writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
  424. ctx->addr + DECON_CRCCTRL);
  425. }
  426. static void decon_atomic_enable(struct exynos_drm_crtc *crtc)
  427. {
  428. struct decon_context *ctx = crtc->ctx;
  429. pm_runtime_get_sync(ctx->dev);
  430. exynos_drm_pipe_clk_enable(crtc, true);
  431. decon_swreset(ctx);
  432. decon_commit(ctx->crtc);
  433. }
  434. static void decon_atomic_disable(struct exynos_drm_crtc *crtc)
  435. {
  436. struct decon_context *ctx = crtc->ctx;
  437. int i;
  438. if (!(ctx->out_type & I80_HW_TRG))
  439. synchronize_irq(ctx->te_irq);
  440. synchronize_irq(ctx->irq);
  441. /*
  442. * We need to make sure that all windows are disabled before we
  443. * suspend that connector. Otherwise we might try to scan from
  444. * a destroyed buffer later.
  445. */
  446. for (i = ctx->first_win; i < WINDOWS_NR; i++)
  447. decon_disable_plane(crtc, &ctx->planes[i]);
  448. decon_swreset(ctx);
  449. exynos_drm_pipe_clk_enable(crtc, false);
  450. pm_runtime_put_sync(ctx->dev);
  451. }
  452. static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
  453. {
  454. struct decon_context *ctx = dev_id;
  455. decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
  456. return IRQ_HANDLED;
  457. }
  458. static void decon_clear_channels(struct exynos_drm_crtc *crtc)
  459. {
  460. struct decon_context *ctx = crtc->ctx;
  461. int win, i, ret;
  462. for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
  463. ret = clk_prepare_enable(ctx->clks[i]);
  464. if (ret < 0)
  465. goto err;
  466. }
  467. decon_shadow_protect(ctx, true);
  468. for (win = 0; win < WINDOWS_NR; win++)
  469. decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
  470. decon_shadow_protect(ctx, false);
  471. decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
  472. /* TODO: wait for possible vsync */
  473. msleep(50);
  474. err:
  475. while (--i >= 0)
  476. clk_disable_unprepare(ctx->clks[i]);
  477. }
  478. static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
  479. const struct drm_display_mode *mode)
  480. {
  481. struct decon_context *ctx = crtc->ctx;
  482. ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
  483. if (ctx->irq)
  484. return MODE_OK;
  485. dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
  486. crtc->i80_mode ? "command" : "video");
  487. return MODE_BAD;
  488. }
  489. static const struct exynos_drm_crtc_ops decon_crtc_ops = {
  490. .atomic_enable = decon_atomic_enable,
  491. .atomic_disable = decon_atomic_disable,
  492. .enable_vblank = decon_enable_vblank,
  493. .disable_vblank = decon_disable_vblank,
  494. .atomic_begin = decon_atomic_begin,
  495. .update_plane = decon_update_plane,
  496. .disable_plane = decon_disable_plane,
  497. .mode_valid = decon_mode_valid,
  498. .atomic_flush = decon_atomic_flush,
  499. };
  500. static int decon_bind(struct device *dev, struct device *master, void *data)
  501. {
  502. struct decon_context *ctx = dev_get_drvdata(dev);
  503. struct drm_device *drm_dev = data;
  504. struct exynos_drm_plane *exynos_plane;
  505. enum exynos_drm_output_type out_type;
  506. unsigned int win;
  507. int ret;
  508. ctx->drm_dev = drm_dev;
  509. for (win = ctx->first_win; win < WINDOWS_NR; win++) {
  510. ctx->configs[win].pixel_formats = decon_formats;
  511. ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
  512. ctx->configs[win].zpos = win - ctx->first_win;
  513. ctx->configs[win].type = decon_win_types[win];
  514. ctx->configs[win].capabilities = capabilities[win];
  515. ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
  516. &ctx->configs[win]);
  517. if (ret)
  518. return ret;
  519. }
  520. exynos_plane = &ctx->planes[PRIMARY_WIN];
  521. out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
  522. : EXYNOS_DISPLAY_TYPE_LCD;
  523. ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
  524. out_type, &decon_crtc_ops, ctx);
  525. if (IS_ERR(ctx->crtc))
  526. return PTR_ERR(ctx->crtc);
  527. decon_clear_channels(ctx->crtc);
  528. return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
  529. }
  530. static void decon_unbind(struct device *dev, struct device *master, void *data)
  531. {
  532. struct decon_context *ctx = dev_get_drvdata(dev);
  533. decon_atomic_disable(ctx->crtc);
  534. /* detach this sub driver from iommu mapping if supported. */
  535. exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
  536. }
  537. static const struct component_ops decon_component_ops = {
  538. .bind = decon_bind,
  539. .unbind = decon_unbind,
  540. };
  541. static void decon_handle_vblank(struct decon_context *ctx)
  542. {
  543. u32 frm;
  544. spin_lock(&ctx->vblank_lock);
  545. frm = decon_get_frame_count(ctx, true);
  546. if (frm != ctx->frame_id) {
  547. /* handle only if incremented, take care of wrap-around */
  548. if ((s32)(frm - ctx->frame_id) > 0)
  549. drm_crtc_handle_vblank(&ctx->crtc->base);
  550. ctx->frame_id = frm;
  551. }
  552. spin_unlock(&ctx->vblank_lock);
  553. }
  554. static irqreturn_t decon_irq_handler(int irq, void *dev_id)
  555. {
  556. struct decon_context *ctx = dev_id;
  557. u32 val;
  558. val = readl(ctx->addr + DECON_VIDINTCON1);
  559. val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
  560. if (val) {
  561. writel(val, ctx->addr + DECON_VIDINTCON1);
  562. if (ctx->out_type & IFTYPE_HDMI) {
  563. val = readl(ctx->addr + DECON_VIDOUTCON0);
  564. val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
  565. if (val ==
  566. (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
  567. return IRQ_HANDLED;
  568. }
  569. decon_handle_vblank(ctx);
  570. }
  571. return IRQ_HANDLED;
  572. }
  573. #ifdef CONFIG_PM
  574. static int exynos5433_decon_suspend(struct device *dev)
  575. {
  576. struct decon_context *ctx = dev_get_drvdata(dev);
  577. int i = ARRAY_SIZE(decon_clks_name);
  578. while (--i >= 0)
  579. clk_disable_unprepare(ctx->clks[i]);
  580. return 0;
  581. }
  582. static int exynos5433_decon_resume(struct device *dev)
  583. {
  584. struct decon_context *ctx = dev_get_drvdata(dev);
  585. int i, ret;
  586. for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
  587. ret = clk_prepare_enable(ctx->clks[i]);
  588. if (ret < 0)
  589. goto err;
  590. }
  591. return 0;
  592. err:
  593. while (--i >= 0)
  594. clk_disable_unprepare(ctx->clks[i]);
  595. return ret;
  596. }
  597. #endif
  598. static const struct dev_pm_ops exynos5433_decon_pm_ops = {
  599. SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
  600. NULL)
  601. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  602. pm_runtime_force_resume)
  603. };
  604. static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
  605. {
  606. .compatible = "samsung,exynos5433-decon",
  607. .data = (void *)I80_HW_TRG
  608. },
  609. {
  610. .compatible = "samsung,exynos5433-decon-tv",
  611. .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
  612. },
  613. {},
  614. };
  615. MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
  616. static int decon_conf_irq(struct decon_context *ctx, const char *name,
  617. irq_handler_t handler, unsigned long int flags)
  618. {
  619. struct platform_device *pdev = to_platform_device(ctx->dev);
  620. int ret, irq = platform_get_irq_byname(pdev, name);
  621. if (irq < 0) {
  622. switch (irq) {
  623. case -EPROBE_DEFER:
  624. return irq;
  625. case -ENODATA:
  626. case -ENXIO:
  627. return 0;
  628. default:
  629. dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
  630. return irq;
  631. }
  632. }
  633. irq_set_status_flags(irq, IRQ_NOAUTOEN);
  634. ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx);
  635. if (ret < 0) {
  636. dev_err(ctx->dev, "IRQ %s request failed\n", name);
  637. return ret;
  638. }
  639. return irq;
  640. }
  641. static int exynos5433_decon_probe(struct platform_device *pdev)
  642. {
  643. struct device *dev = &pdev->dev;
  644. struct decon_context *ctx;
  645. struct resource *res;
  646. int ret;
  647. int i;
  648. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  649. if (!ctx)
  650. return -ENOMEM;
  651. ctx->dev = dev;
  652. ctx->out_type = (unsigned long)of_device_get_match_data(dev);
  653. spin_lock_init(&ctx->vblank_lock);
  654. if (ctx->out_type & IFTYPE_HDMI)
  655. ctx->first_win = 1;
  656. for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
  657. struct clk *clk;
  658. clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
  659. if (IS_ERR(clk))
  660. return PTR_ERR(clk);
  661. ctx->clks[i] = clk;
  662. }
  663. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  664. ctx->addr = devm_ioremap_resource(dev, res);
  665. if (IS_ERR(ctx->addr)) {
  666. dev_err(dev, "ioremap failed\n");
  667. return PTR_ERR(ctx->addr);
  668. }
  669. ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
  670. if (ret < 0)
  671. return ret;
  672. ctx->irq_vsync = ret;
  673. ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
  674. if (ret < 0)
  675. return ret;
  676. ctx->irq_lcd_sys = ret;
  677. ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
  678. IRQF_TRIGGER_RISING);
  679. if (ret < 0)
  680. return ret;
  681. if (ret) {
  682. ctx->te_irq = ret;
  683. ctx->out_type &= ~I80_HW_TRG;
  684. }
  685. if (ctx->out_type & I80_HW_TRG) {
  686. ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
  687. "samsung,disp-sysreg");
  688. if (IS_ERR(ctx->sysreg)) {
  689. dev_err(dev, "failed to get system register\n");
  690. return PTR_ERR(ctx->sysreg);
  691. }
  692. }
  693. platform_set_drvdata(pdev, ctx);
  694. pm_runtime_enable(dev);
  695. ret = component_add(dev, &decon_component_ops);
  696. if (ret)
  697. goto err_disable_pm_runtime;
  698. return 0;
  699. err_disable_pm_runtime:
  700. pm_runtime_disable(dev);
  701. return ret;
  702. }
  703. static int exynos5433_decon_remove(struct platform_device *pdev)
  704. {
  705. pm_runtime_disable(&pdev->dev);
  706. component_del(&pdev->dev, &decon_component_ops);
  707. return 0;
  708. }
  709. struct platform_driver exynos5433_decon_driver = {
  710. .probe = exynos5433_decon_probe,
  711. .remove = exynos5433_decon_remove,
  712. .driver = {
  713. .name = "exynos5433-decon",
  714. .pm = &exynos5433_decon_pm_ops,
  715. .of_match_table = exynos5433_decon_driver_dt_match,
  716. },
  717. };