state_hi.xml.h 28 KB

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  1. #ifndef STATE_HI_XML
  2. #define STATE_HI_XML
  3. /* Autogenerated file, DO NOT EDIT manually!
  4. This file was generated by the rules-ng-ng headergen tool in this git repository:
  5. http://0x04.net/cgit/index.cgi/rules-ng-ng
  6. git clone git://0x04.net/rules-ng-ng
  7. The rules-ng-ng source files this header was generated from are:
  8. - state.xml ( 26666 bytes, from 2019-12-20 21:20:35)
  9. - common.xml ( 35468 bytes, from 2018-02-10 13:09:26)
  10. - common_3d.xml ( 15058 bytes, from 2019-12-28 20:02:03)
  11. - state_hi.xml ( 30552 bytes, from 2019-12-28 20:02:48)
  12. - copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26)
  13. - state_2d.xml ( 51552 bytes, from 2018-02-10 13:09:26)
  14. - state_3d.xml ( 83098 bytes, from 2019-12-28 20:02:03)
  15. - state_blt.xml ( 14252 bytes, from 2019-10-20 19:59:15)
  16. - state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26)
  17. Copyright (C) 2012-2019 by the following authors:
  18. - Wladimir J. van der Laan <laanwj@gmail.com>
  19. - Christian Gmeiner <christian.gmeiner@gmail.com>
  20. - Lucas Stach <l.stach@pengutronix.de>
  21. - Russell King <rmk@arm.linux.org.uk>
  22. Permission is hereby granted, free of charge, to any person obtaining a
  23. copy of this software and associated documentation files (the "Software"),
  24. to deal in the Software without restriction, including without limitation
  25. the rights to use, copy, modify, merge, publish, distribute, sub license,
  26. and/or sell copies of the Software, and to permit persons to whom the
  27. Software is furnished to do so, subject to the following conditions:
  28. The above copyright notice and this permission notice (including the
  29. next paragraph) shall be included in all copies or substantial portions
  30. of the Software.
  31. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  32. IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  33. FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  34. THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  35. LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  36. FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  37. DEALINGS IN THE SOFTWARE.
  38. */
  39. #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
  40. #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
  41. #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
  42. #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004
  43. #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005
  44. #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006
  45. #define VIVS_HI 0x00000000
  46. #define VIVS_HI_CLOCK_CONTROL 0x00000000
  47. #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS 0x00000001
  48. #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS 0x00000002
  49. #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK 0x000001fc
  50. #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT 2
  51. #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x) (((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK)
  52. #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD 0x00000200
  53. #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING 0x00000400
  54. #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS 0x00000800
  55. #define VIVS_HI_CLOCK_CONTROL_SOFT_RESET 0x00001000
  56. #define VIVS_HI_CLOCK_CONTROL_IDLE_3D 0x00010000
  57. #define VIVS_HI_CLOCK_CONTROL_IDLE_2D 0x00020000
  58. #define VIVS_HI_CLOCK_CONTROL_IDLE_VG 0x00040000
  59. #define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU 0x00080000
  60. #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK 0x00f00000
  61. #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT 20
  62. #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x) (((x) << VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT) & VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK)
  63. #define VIVS_HI_IDLE_STATE 0x00000004
  64. #define VIVS_HI_IDLE_STATE_FE 0x00000001
  65. #define VIVS_HI_IDLE_STATE_DE 0x00000002
  66. #define VIVS_HI_IDLE_STATE_PE 0x00000004
  67. #define VIVS_HI_IDLE_STATE_SH 0x00000008
  68. #define VIVS_HI_IDLE_STATE_PA 0x00000010
  69. #define VIVS_HI_IDLE_STATE_SE 0x00000020
  70. #define VIVS_HI_IDLE_STATE_RA 0x00000040
  71. #define VIVS_HI_IDLE_STATE_TX 0x00000080
  72. #define VIVS_HI_IDLE_STATE_VG 0x00000100
  73. #define VIVS_HI_IDLE_STATE_IM 0x00000200
  74. #define VIVS_HI_IDLE_STATE_FP 0x00000400
  75. #define VIVS_HI_IDLE_STATE_TS 0x00000800
  76. #define VIVS_HI_IDLE_STATE_BL 0x00001000
  77. #define VIVS_HI_IDLE_STATE_ASYNCFE 0x00002000
  78. #define VIVS_HI_IDLE_STATE_MC 0x00004000
  79. #define VIVS_HI_IDLE_STATE_PPA 0x00008000
  80. #define VIVS_HI_IDLE_STATE_WD 0x00010000
  81. #define VIVS_HI_IDLE_STATE_NN 0x00020000
  82. #define VIVS_HI_IDLE_STATE_TP 0x00040000
  83. #define VIVS_HI_IDLE_STATE_AXI_LP 0x80000000
  84. #define VIVS_HI_AXI_CONFIG 0x00000008
  85. #define VIVS_HI_AXI_CONFIG_AWID__MASK 0x0000000f
  86. #define VIVS_HI_AXI_CONFIG_AWID__SHIFT 0
  87. #define VIVS_HI_AXI_CONFIG_AWID(x) (((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK)
  88. #define VIVS_HI_AXI_CONFIG_ARID__MASK 0x000000f0
  89. #define VIVS_HI_AXI_CONFIG_ARID__SHIFT 4
  90. #define VIVS_HI_AXI_CONFIG_ARID(x) (((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK)
  91. #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK 0x00000f00
  92. #define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT 8
  93. #define VIVS_HI_AXI_CONFIG_AWCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK)
  94. #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK 0x0000f000
  95. #define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT 12
  96. #define VIVS_HI_AXI_CONFIG_ARCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK)
  97. #define VIVS_HI_AXI_STATUS 0x0000000c
  98. #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK 0x0000000f
  99. #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT 0
  100. #define VIVS_HI_AXI_STATUS_WR_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK)
  101. #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK 0x000000f0
  102. #define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT 4
  103. #define VIVS_HI_AXI_STATUS_RD_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK)
  104. #define VIVS_HI_AXI_STATUS_DET_WR_ERR 0x00000100
  105. #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200
  106. #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010
  107. #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff
  108. #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0
  109. #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK)
  110. #define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000
  111. #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000
  112. #define VIVS_HI_INTR_ENBL 0x00000014
  113. #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK 0xffffffff
  114. #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT 0
  115. #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x) (((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK)
  116. #define VIVS_HI_CHIP_IDENTITY 0x00000018
  117. #define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK 0xff000000
  118. #define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT 24
  119. #define VIVS_HI_CHIP_IDENTITY_FAMILY(x) (((x) << VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK)
  120. #define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK 0x00ff0000
  121. #define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT 16
  122. #define VIVS_HI_CHIP_IDENTITY_PRODUCT(x) (((x) << VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT) & VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK)
  123. #define VIVS_HI_CHIP_IDENTITY_REVISION__MASK 0x0000f000
  124. #define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT 12
  125. #define VIVS_HI_CHIP_IDENTITY_REVISION(x) (((x) << VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT) & VIVS_HI_CHIP_IDENTITY_REVISION__MASK)
  126. #define VIVS_HI_CHIP_FEATURE 0x0000001c
  127. #define VIVS_HI_CHIP_MODEL 0x00000020
  128. #define VIVS_HI_CHIP_REV 0x00000024
  129. #define VIVS_HI_CHIP_DATE 0x00000028
  130. #define VIVS_HI_CHIP_TIME 0x0000002c
  131. #define VIVS_HI_CHIP_CUSTOMER_ID 0x00000030
  132. #define VIVS_HI_CHIP_MINOR_FEATURE_0 0x00000034
  133. #define VIVS_HI_CACHE_CONTROL 0x00000038
  134. #define VIVS_HI_MEMORY_COUNTER_RESET 0x0000003c
  135. #define VIVS_HI_PROFILE_READ_BYTES8 0x00000040
  136. #define VIVS_HI_PROFILE_WRITE_BYTES8 0x00000044
  137. #define VIVS_HI_CHIP_SPECS 0x00000048
  138. #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK 0x0000000f
  139. #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT 0
  140. #define VIVS_HI_CHIP_SPECS_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK)
  141. #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK 0x000000f0
  142. #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT 4
  143. #define VIVS_HI_CHIP_SPECS_REGISTER_MAX(x) (((x) << VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT) & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK)
  144. #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK 0x00000f00
  145. #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT 8
  146. #define VIVS_HI_CHIP_SPECS_THREAD_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK)
  147. #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK 0x0001f000
  148. #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT 12
  149. #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK)
  150. #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK 0x01f00000
  151. #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT 20
  152. #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK)
  153. #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK 0x0e000000
  154. #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT 25
  155. #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES(x) (((x) << VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT) & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK)
  156. #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK 0xf0000000
  157. #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT 28
  158. #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK)
  159. #define VIVS_HI_PROFILE_WRITE_BURSTS 0x0000004c
  160. #define VIVS_HI_PROFILE_WRITE_REQUESTS 0x00000050
  161. #define VIVS_HI_PROFILE_READ_BURSTS 0x00000058
  162. #define VIVS_HI_PROFILE_READ_REQUESTS 0x0000005c
  163. #define VIVS_HI_PROFILE_READ_LASTS 0x00000060
  164. #define VIVS_HI_GP_OUT0 0x00000064
  165. #define VIVS_HI_GP_OUT1 0x00000068
  166. #define VIVS_HI_GP_OUT2 0x0000006c
  167. #define VIVS_HI_AXI_CONTROL 0x00000070
  168. #define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE 0x00000001
  169. #define VIVS_HI_CHIP_MINOR_FEATURE_1 0x00000074
  170. #define VIVS_HI_PROFILE_TOTAL_CYCLES 0x00000078
  171. #define VIVS_HI_PROFILE_IDLE_CYCLES 0x0000007c
  172. #define VIVS_HI_CHIP_SPECS_2 0x00000080
  173. #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK 0x000000ff
  174. #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT 0
  175. #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK)
  176. #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK 0x0000ff00
  177. #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT 8
  178. #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK)
  179. #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK 0xffff0000
  180. #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT 16
  181. #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS(x) (((x) << VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT) & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK)
  182. #define VIVS_HI_CHIP_MINOR_FEATURE_2 0x00000084
  183. #define VIVS_HI_CHIP_MINOR_FEATURE_3 0x00000088
  184. #define VIVS_HI_CHIP_SPECS_3 0x0000008c
  185. #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK 0x000001f0
  186. #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT 4
  187. #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK)
  188. #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK 0x00000007
  189. #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0
  190. #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK)
  191. #define VIVS_HI_COMPRESSION_FLAGS 0x00000090
  192. #define VIVS_HI_COMPRESSION_FLAGS_DEC300 0x00000040
  193. #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094
  194. #define VIVS_HI_CHIP_SPECS_4 0x0000009c
  195. #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK 0x0001f000
  196. #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT 12
  197. #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK)
  198. #define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0
  199. #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8
  200. #define VIVS_HI_BLT_INTR 0x000000d4
  201. #define VIVS_HI_CHIP_ECO_ID 0x000000e8
  202. #define VIVS_HI_AUXBIT 0x000000ec
  203. #define VIVS_PM 0x00000000
  204. #define VIVS_PM_POWER_CONTROLS 0x00000100
  205. #define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING 0x00000001
  206. #define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING 0x00000002
  207. #define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING 0x00000004
  208. #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK 0x000000f0
  209. #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT 4
  210. #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK)
  211. #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK 0xffff0000
  212. #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT 16
  213. #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK)
  214. #define VIVS_PM_MODULE_CONTROLS 0x00000104
  215. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE 0x00000001
  216. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE 0x00000002
  217. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE 0x00000004
  218. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH 0x00000008
  219. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA 0x00000010
  220. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020
  221. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040
  222. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080
  223. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000
  224. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000
  225. #define VIVS_PM_MODULE_STATUS 0x00000108
  226. #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001
  227. #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE 0x00000002
  228. #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE 0x00000004
  229. #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH 0x00000008
  230. #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA 0x00000010
  231. #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE 0x00000020
  232. #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA 0x00000040
  233. #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080
  234. #define VIVS_PM_PULSE_EATER 0x0000010c
  235. #define VIVS_PM_PULSE_EATER_DISABLE 0x00000001
  236. #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK 0x0000ff00
  237. #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT 8
  238. #define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x) (((x) << VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT) & VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK)
  239. #define VIVS_PM_PULSE_EATER_UNK16 0x00010000
  240. #define VIVS_PM_PULSE_EATER_UNK17 0x00020000
  241. #define VIVS_PM_PULSE_EATER_INTERNAL_DFS 0x00040000
  242. #define VIVS_PM_PULSE_EATER_UNK19 0x00080000
  243. #define VIVS_PM_PULSE_EATER_UNK20 0x00100000
  244. #define VIVS_PM_PULSE_EATER_UNK22 0x00400000
  245. #define VIVS_PM_PULSE_EATER_UNK23 0x00800000
  246. #define VIVS_MMUv2 0x00000000
  247. #define VIVS_MMUv2_SAFE_ADDRESS 0x00000180
  248. #define VIVS_MMUv2_CONFIGURATION 0x00000184
  249. #define VIVS_MMUv2_CONFIGURATION_MODE__MASK 0x00000001
  250. #define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT 0
  251. #define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K 0x00000000
  252. #define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K 0x00000001
  253. #define VIVS_MMUv2_CONFIGURATION_MODE_MASK 0x00000008
  254. #define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK 0x00000010
  255. #define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT 4
  256. #define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH 0x00000010
  257. #define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK 0x00000080
  258. #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK 0x00000100
  259. #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK 0xfffffc00
  260. #define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT 10
  261. #define VIVS_MMUv2_CONFIGURATION_ADDRESS(x) (((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK)
  262. #define VIVS_MMUv2_STATUS 0x00000188
  263. #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x00000003
  264. #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT 0
  265. #define VIVS_MMUv2_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK)
  266. #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x00000030
  267. #define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT 4
  268. #define VIVS_MMUv2_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK)
  269. #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000300
  270. #define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT 8
  271. #define VIVS_MMUv2_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK)
  272. #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x00003000
  273. #define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT 12
  274. #define VIVS_MMUv2_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK)
  275. #define VIVS_MMUv2_CONTROL 0x0000018c
  276. #define VIVS_MMUv2_CONTROL_ENABLE 0x00000001
  277. #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0))
  278. #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004
  279. #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004
  280. #define VIVS_MMUv2_PROFILE_BLT_READ 0x000001a4
  281. #define VIVS_MMUv2_PTA_CONFIG 0x000001ac
  282. #define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK 0x0000ffff
  283. #define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT 0
  284. #define VIVS_MMUv2_PTA_CONFIG_INDEX(x) (((x) << VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT) & VIVS_MMUv2_PTA_CONFIG_INDEX__MASK)
  285. #define VIVS_MMUv2_PTA_CONFIG_UNK16 0x00010000
  286. #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0))
  287. #define VIVS_MMUv2_AXI_POLICY__ESIZE 0x00000004
  288. #define VIVS_MMUv2_AXI_POLICY__LEN 0x00000008
  289. #define VIVS_MMUv2_SEC_EXCEPTION_ADDR 0x00000380
  290. #define VIVS_MMUv2_SEC_STATUS 0x00000384
  291. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK 0x00000003
  292. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT 0
  293. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK)
  294. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK 0x00000030
  295. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT 4
  296. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK)
  297. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK 0x00000300
  298. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT 8
  299. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK)
  300. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK 0x00003000
  301. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT 12
  302. #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK)
  303. #define VIVS_MMUv2_SEC_CONTROL 0x00000388
  304. #define VIVS_MMUv2_SEC_CONTROL_ENABLE 0x00000001
  305. #define VIVS_MMUv2_PTA_ADDRESS_LOW 0x0000038c
  306. #define VIVS_MMUv2_PTA_ADDRESS_HIGH 0x00000390
  307. #define VIVS_MMUv2_PTA_CONTROL 0x00000394
  308. #define VIVS_MMUv2_PTA_CONTROL_ENABLE 0x00000001
  309. #define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW 0x00000398
  310. #define VIVS_MMUv2_SEC_SAFE_ADDR_LOW 0x0000039c
  311. #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG 0x000003a0
  312. #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK 0x000000ff
  313. #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT 0
  314. #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK)
  315. #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15 0x00008000
  316. #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000
  317. #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT 16
  318. #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK)
  319. #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31 0x80000000
  320. #define VIVS_MMUv2_SEC_COMMAND_CONTROL 0x000003a4
  321. #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff
  322. #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT 0
  323. #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK)
  324. #define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE 0x00010000
  325. #define VIVS_MMUv2_AHB_CONTROL 0x000003a8
  326. #define VIVS_MMUv2_AHB_CONTROL_RESET 0x00000001
  327. #define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS 0x00000002
  328. #define VIVS_MC 0x00000000
  329. #define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400
  330. #define VIVS_MC_MMU_TX_PAGE_TABLE 0x00000404
  331. #define VIVS_MC_MMU_PE_PAGE_TABLE 0x00000408
  332. #define VIVS_MC_MMU_PEZ_PAGE_TABLE 0x0000040c
  333. #define VIVS_MC_MMU_RA_PAGE_TABLE 0x00000410
  334. #define VIVS_MC_DEBUG_MEMORY 0x00000414
  335. #define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320 0x00000008
  336. #define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS 0x00100000
  337. #define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS 0x00200000
  338. #define VIVS_MC_MEMORY_BASE_ADDR_RA 0x00000418
  339. #define VIVS_MC_MEMORY_BASE_ADDR_FE 0x0000041c
  340. #define VIVS_MC_MEMORY_BASE_ADDR_TX 0x00000420
  341. #define VIVS_MC_MEMORY_BASE_ADDR_PEZ 0x00000424
  342. #define VIVS_MC_MEMORY_BASE_ADDR_PE 0x00000428
  343. #define VIVS_MC_MEMORY_TIMING_CONTROL 0x0000042c
  344. #define VIVS_MC_MEMORY_FLUSH 0x00000430
  345. #define VIVS_MC_PROFILE_CYCLE_COUNTER 0x00000438
  346. #define VIVS_MC_DEBUG_READ0 0x0000043c
  347. #define VIVS_MC_DEBUG_READ1 0x00000440
  348. #define VIVS_MC_DEBUG_WRITE 0x00000444
  349. #define VIVS_MC_PROFILE_RA_READ 0x00000448
  350. #define VIVS_MC_PROFILE_TX_READ 0x0000044c
  351. #define VIVS_MC_PROFILE_FE_READ 0x00000450
  352. #define VIVS_MC_PROFILE_PE_READ 0x00000454
  353. #define VIVS_MC_PROFILE_DE_READ 0x00000458
  354. #define VIVS_MC_PROFILE_SH_READ 0x0000045c
  355. #define VIVS_MC_PROFILE_PA_READ 0x00000460
  356. #define VIVS_MC_PROFILE_SE_READ 0x00000464
  357. #define VIVS_MC_PROFILE_MC_READ 0x00000468
  358. #define VIVS_MC_PROFILE_HI_READ 0x0000046c
  359. #define VIVS_MC_PROFILE_CONFIG0 0x00000470
  360. #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff
  361. #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0
  362. #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f
  363. #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x0000ff00
  364. #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8
  365. #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00
  366. #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x00ff0000
  367. #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16
  368. #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000
  369. #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000
  370. #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE 0x00020000
  371. #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000
  372. #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000
  373. #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000
  374. #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0xff000000
  375. #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24
  376. #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000
  377. #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000
  378. #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER 0x08000000
  379. #define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER 0x09000000
  380. #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER 0x0a000000
  381. #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER 0x0b000000
  382. #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER 0x0c000000
  383. #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER 0x0d000000
  384. #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER 0x0e000000
  385. #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000
  386. #define VIVS_MC_PROFILE_CONFIG1 0x00000474
  387. #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x000000ff
  388. #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0
  389. #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003
  390. #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004
  391. #define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER 0x00000005
  392. #define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER 0x00000006
  393. #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007
  394. #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008
  395. #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f
  396. #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x0000ff00
  397. #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8
  398. #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000
  399. #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100
  400. #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00
  401. #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x00ff0000
  402. #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16
  403. #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000
  404. #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000
  405. #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z 0x00020000
  406. #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT 0x00030000
  407. #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER 0x00090000
  408. #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000
  409. #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000
  410. #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000
  411. #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0xff000000
  412. #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24
  413. #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000
  414. #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000
  415. #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS 0x02000000
  416. #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS 0x03000000
  417. #define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN 0x04000000
  418. #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT 0x05000000
  419. #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT 0x06000000
  420. #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT 0x07000000
  421. #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT 0x08000000
  422. #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT 0x09000000
  423. #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000
  424. #define VIVS_MC_PROFILE_CONFIG2 0x00000478
  425. #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x000000ff
  426. #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0
  427. #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001
  428. #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002
  429. #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003
  430. #define VIVS_MC_PROFILE_CONFIG2_MC_RESET 0x0000000f
  431. #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x0000ff00
  432. #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8
  433. #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000
  434. #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100
  435. #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200
  436. #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00
  437. #define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000
  438. #define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT 24
  439. #define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000
  440. #define VIVS_MC_PROFILE_CONFIG3 0x0000047c
  441. #define VIVS_MC_BUS_CONFIG 0x00000480
  442. #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK 0x0000000f
  443. #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT 0
  444. #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK)
  445. #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK 0x000000f0
  446. #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT 4
  447. #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK)
  448. #define VIVS_MC_START_COMPOSITION 0x00000554
  449. #define VIVS_MC_FLAGS 0x00000558
  450. #define VIVS_MC_FLAGS_128B_MERGE 0x00000001
  451. #define VIVS_MC_FLAGS_TPCV11_COMPRESSION 0x08000000
  452. #define VIVS_MC_L2_CACHE_CONFIG 0x0000055c
  453. #define VIVS_MC_PROFILE_L2_READ 0x00000564
  454. #endif /* STATE_HI_XML */