drm_scdc_helper.c 6.4 KB

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  1. /*
  2. * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sub license,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the
  12. * next paragraph) shall be included in all copies or substantial portions
  13. * of the Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. */
  23. #include <linux/slab.h>
  24. #include <linux/delay.h>
  25. #include <drm/drm_print.h>
  26. #include <drm/drm_scdc_helper.h>
  27. /**
  28. * DOC: scdc helpers
  29. *
  30. * Status and Control Data Channel (SCDC) is a mechanism introduced by the
  31. * HDMI 2.0 specification. It is a point-to-point protocol that allows the
  32. * HDMI source and HDMI sink to exchange data. The same I2C interface that
  33. * is used to access EDID serves as the transport mechanism for SCDC.
  34. */
  35. #define SCDC_I2C_SLAVE_ADDRESS 0x54
  36. /**
  37. * drm_scdc_read - read a block of data from SCDC
  38. * @adapter: I2C controller
  39. * @offset: start offset of block to read
  40. * @buffer: return location for the block to read
  41. * @size: size of the block to read
  42. *
  43. * Reads a block of data from SCDC, starting at a given offset.
  44. *
  45. * Returns:
  46. * 0 on success, negative error code on failure.
  47. */
  48. ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
  49. size_t size)
  50. {
  51. int ret;
  52. struct i2c_msg msgs[2] = {
  53. {
  54. .addr = SCDC_I2C_SLAVE_ADDRESS,
  55. .flags = 0,
  56. .len = 1,
  57. .buf = &offset,
  58. }, {
  59. .addr = SCDC_I2C_SLAVE_ADDRESS,
  60. .flags = I2C_M_RD,
  61. .len = size,
  62. .buf = buffer,
  63. }
  64. };
  65. ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
  66. if (ret < 0)
  67. return ret;
  68. if (ret != ARRAY_SIZE(msgs))
  69. return -EPROTO;
  70. return 0;
  71. }
  72. EXPORT_SYMBOL(drm_scdc_read);
  73. /**
  74. * drm_scdc_write - write a block of data to SCDC
  75. * @adapter: I2C controller
  76. * @offset: start offset of block to write
  77. * @buffer: block of data to write
  78. * @size: size of the block to write
  79. *
  80. * Writes a block of data to SCDC, starting at a given offset.
  81. *
  82. * Returns:
  83. * 0 on success, negative error code on failure.
  84. */
  85. ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
  86. const void *buffer, size_t size)
  87. {
  88. struct i2c_msg msg = {
  89. .addr = SCDC_I2C_SLAVE_ADDRESS,
  90. .flags = 0,
  91. .len = 1 + size,
  92. .buf = NULL,
  93. };
  94. void *data;
  95. int err;
  96. data = kmalloc(1 + size, GFP_KERNEL);
  97. if (!data)
  98. return -ENOMEM;
  99. msg.buf = data;
  100. memcpy(data, &offset, sizeof(offset));
  101. memcpy(data + 1, buffer, size);
  102. err = i2c_transfer(adapter, &msg, 1);
  103. kfree(data);
  104. if (err < 0)
  105. return err;
  106. if (err != 1)
  107. return -EPROTO;
  108. return 0;
  109. }
  110. EXPORT_SYMBOL(drm_scdc_write);
  111. /**
  112. * drm_scdc_check_scrambling_status - what is status of scrambling?
  113. * @adapter: I2C adapter for DDC channel
  114. *
  115. * Reads the scrambler status over SCDC, and checks the
  116. * scrambling status.
  117. *
  118. * Returns:
  119. * True if the scrambling is enabled, false otherwise.
  120. */
  121. bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
  122. {
  123. u8 status;
  124. int ret;
  125. ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
  126. if (ret < 0) {
  127. DRM_DEBUG_KMS("Failed to read scrambling status: %d\n", ret);
  128. return false;
  129. }
  130. return status & SCDC_SCRAMBLING_STATUS;
  131. }
  132. EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
  133. /**
  134. * drm_scdc_set_scrambling - enable scrambling
  135. * @adapter: I2C adapter for DDC channel
  136. * @enable: bool to indicate if scrambling is to be enabled/disabled
  137. *
  138. * Writes the TMDS config register over SCDC channel, and:
  139. * enables scrambling when enable = 1
  140. * disables scrambling when enable = 0
  141. *
  142. * Returns:
  143. * True if scrambling is set/reset successfully, false otherwise.
  144. */
  145. bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
  146. {
  147. u8 config;
  148. int ret;
  149. ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
  150. if (ret < 0) {
  151. DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
  152. return false;
  153. }
  154. if (enable)
  155. config |= SCDC_SCRAMBLING_ENABLE;
  156. else
  157. config &= ~SCDC_SCRAMBLING_ENABLE;
  158. ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
  159. if (ret < 0) {
  160. DRM_DEBUG_KMS("Failed to enable scrambling: %d\n", ret);
  161. return false;
  162. }
  163. return true;
  164. }
  165. EXPORT_SYMBOL(drm_scdc_set_scrambling);
  166. /**
  167. * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
  168. * @adapter: I2C adapter for DDC channel
  169. * @set: ret or reset the high clock ratio
  170. *
  171. *
  172. * TMDS clock ratio calculations go like this:
  173. * TMDS character = 10 bit TMDS encoded value
  174. *
  175. * TMDS character rate = The rate at which TMDS characters are
  176. * transmitted (Mcsc)
  177. *
  178. * TMDS bit rate = 10x TMDS character rate
  179. *
  180. * As per the spec:
  181. * TMDS clock rate for pixel clock < 340 MHz = 1x the character
  182. * rate = 1/10 pixel clock rate
  183. *
  184. * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
  185. * rate = 1/40 pixel clock rate
  186. *
  187. * Writes to the TMDS config register over SCDC channel, and:
  188. * sets TMDS clock ratio to 1/40 when set = 1
  189. *
  190. * sets TMDS clock ratio to 1/10 when set = 0
  191. *
  192. * Returns:
  193. * True if write is successful, false otherwise.
  194. */
  195. bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set)
  196. {
  197. u8 config;
  198. int ret;
  199. ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
  200. if (ret < 0) {
  201. DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
  202. return false;
  203. }
  204. if (set)
  205. config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
  206. else
  207. config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
  208. ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
  209. if (ret < 0) {
  210. DRM_DEBUG_KMS("Failed to set TMDS clock ratio: %d\n", ret);
  211. return false;
  212. }
  213. /*
  214. * The spec says that a source should wait minimum 1ms and maximum
  215. * 100ms after writing the TMDS config for clock ratio. Lets allow a
  216. * wait of upto 2ms here.
  217. */
  218. usleep_range(1000, 2000);
  219. return true;
  220. }
  221. EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);