drm_mipi_dbi.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MIPI Display Bus Interface (DBI) LCD controller support
  4. *
  5. * Copyright 2016 Noralf Trønnes
  6. */
  7. #include <linux/debugfs.h>
  8. #include <linux/delay.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/module.h>
  12. #include <linux/regulator/consumer.h>
  13. #include <linux/spi/spi.h>
  14. #include <drm/drm_connector.h>
  15. #include <drm/drm_damage_helper.h>
  16. #include <drm/drm_drv.h>
  17. #include <drm/drm_gem_cma_helper.h>
  18. #include <drm/drm_format_helper.h>
  19. #include <drm/drm_fourcc.h>
  20. #include <drm/drm_gem_framebuffer_helper.h>
  21. #include <drm/drm_mipi_dbi.h>
  22. #include <drm/drm_modes.h>
  23. #include <drm/drm_probe_helper.h>
  24. #include <drm/drm_rect.h>
  25. #include <video/mipi_display.h>
  26. #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
  27. #define DCS_POWER_MODE_DISPLAY BIT(2)
  28. #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3)
  29. #define DCS_POWER_MODE_SLEEP_MODE BIT(4)
  30. #define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
  31. #define DCS_POWER_MODE_IDLE_MODE BIT(6)
  32. #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7))
  33. /**
  34. * DOC: overview
  35. *
  36. * This library provides helpers for MIPI Display Bus Interface (DBI)
  37. * compatible display controllers.
  38. *
  39. * Many controllers for tiny lcd displays are MIPI compliant and can use this
  40. * library. If a controller uses registers 0x2A and 0x2B to set the area to
  41. * update and uses register 0x2C to write to frame memory, it is most likely
  42. * MIPI compliant.
  43. *
  44. * Only MIPI Type 1 displays are supported since a full frame memory is needed.
  45. *
  46. * There are 3 MIPI DBI implementation types:
  47. *
  48. * A. Motorola 6800 type parallel bus
  49. *
  50. * B. Intel 8080 type parallel bus
  51. *
  52. * C. SPI type with 3 options:
  53. *
  54. * 1. 9-bit with the Data/Command signal as the ninth bit
  55. * 2. Same as above except it's sent as 16 bits
  56. * 3. 8-bit with the Data/Command signal as a separate D/CX pin
  57. *
  58. * Currently mipi_dbi only supports Type C options 1 and 3 with
  59. * mipi_dbi_spi_init().
  60. */
  61. #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
  62. ({ \
  63. if (!len) \
  64. DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
  65. else if (len <= 32) \
  66. DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
  67. else \
  68. DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
  69. })
  70. static const u8 mipi_dbi_dcs_read_commands[] = {
  71. MIPI_DCS_GET_DISPLAY_ID,
  72. MIPI_DCS_GET_RED_CHANNEL,
  73. MIPI_DCS_GET_GREEN_CHANNEL,
  74. MIPI_DCS_GET_BLUE_CHANNEL,
  75. MIPI_DCS_GET_DISPLAY_STATUS,
  76. MIPI_DCS_GET_POWER_MODE,
  77. MIPI_DCS_GET_ADDRESS_MODE,
  78. MIPI_DCS_GET_PIXEL_FORMAT,
  79. MIPI_DCS_GET_DISPLAY_MODE,
  80. MIPI_DCS_GET_SIGNAL_MODE,
  81. MIPI_DCS_GET_DIAGNOSTIC_RESULT,
  82. MIPI_DCS_READ_MEMORY_START,
  83. MIPI_DCS_READ_MEMORY_CONTINUE,
  84. MIPI_DCS_GET_SCANLINE,
  85. MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
  86. MIPI_DCS_GET_CONTROL_DISPLAY,
  87. MIPI_DCS_GET_POWER_SAVE,
  88. MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
  89. MIPI_DCS_READ_DDB_START,
  90. MIPI_DCS_READ_DDB_CONTINUE,
  91. 0, /* sentinel */
  92. };
  93. static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
  94. {
  95. unsigned int i;
  96. if (!dbi->read_commands)
  97. return false;
  98. for (i = 0; i < 0xff; i++) {
  99. if (!dbi->read_commands[i])
  100. return false;
  101. if (cmd == dbi->read_commands[i])
  102. return true;
  103. }
  104. return false;
  105. }
  106. /**
  107. * mipi_dbi_command_read - MIPI DCS read command
  108. * @dbi: MIPI DBI structure
  109. * @cmd: Command
  110. * @val: Value read
  111. *
  112. * Send MIPI DCS read command to the controller.
  113. *
  114. * Returns:
  115. * Zero on success, negative error code on failure.
  116. */
  117. int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
  118. {
  119. if (!dbi->read_commands)
  120. return -EACCES;
  121. if (!mipi_dbi_command_is_read(dbi, cmd))
  122. return -EINVAL;
  123. return mipi_dbi_command_buf(dbi, cmd, val, 1);
  124. }
  125. EXPORT_SYMBOL(mipi_dbi_command_read);
  126. /**
  127. * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
  128. * @dbi: MIPI DBI structure
  129. * @cmd: Command
  130. * @data: Parameter buffer
  131. * @len: Buffer length
  132. *
  133. * Returns:
  134. * Zero on success, negative error code on failure.
  135. */
  136. int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
  137. {
  138. u8 *cmdbuf;
  139. int ret;
  140. /* SPI requires dma-safe buffers */
  141. cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
  142. if (!cmdbuf)
  143. return -ENOMEM;
  144. mutex_lock(&dbi->cmdlock);
  145. ret = dbi->command(dbi, cmdbuf, data, len);
  146. mutex_unlock(&dbi->cmdlock);
  147. kfree(cmdbuf);
  148. return ret;
  149. }
  150. EXPORT_SYMBOL(mipi_dbi_command_buf);
  151. /* This should only be used by mipi_dbi_command() */
  152. int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
  153. size_t len)
  154. {
  155. u8 *buf;
  156. int ret;
  157. buf = kmemdup(data, len, GFP_KERNEL);
  158. if (!buf)
  159. return -ENOMEM;
  160. ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
  161. kfree(buf);
  162. return ret;
  163. }
  164. EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
  165. /**
  166. * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
  167. * @dst: The destination buffer
  168. * @fb: The source framebuffer
  169. * @clip: Clipping rectangle of the area to be copied
  170. * @swap: When true, swap MSB/LSB of 16-bit values
  171. *
  172. * Returns:
  173. * Zero on success, negative error code on failure.
  174. */
  175. int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
  176. struct drm_rect *clip, bool swap)
  177. {
  178. struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
  179. struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
  180. struct dma_buf_attachment *import_attach = gem->import_attach;
  181. struct drm_format_name_buf format_name;
  182. void *src = cma_obj->vaddr;
  183. int ret = 0;
  184. if (import_attach) {
  185. ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
  186. DMA_FROM_DEVICE);
  187. if (ret)
  188. return ret;
  189. }
  190. switch (fb->format->format) {
  191. case DRM_FORMAT_RGB565:
  192. if (swap)
  193. drm_fb_swab(dst, src, fb, clip, !import_attach);
  194. else
  195. drm_fb_memcpy(dst, src, fb, clip);
  196. break;
  197. case DRM_FORMAT_XRGB8888:
  198. drm_fb_xrgb8888_to_rgb565(dst, src, fb, clip, swap);
  199. break;
  200. default:
  201. drm_err_once(fb->dev, "Format is not supported: %s\n",
  202. drm_get_format_name(fb->format->format, &format_name));
  203. return -EINVAL;
  204. }
  205. if (import_attach)
  206. ret = dma_buf_end_cpu_access(import_attach->dmabuf,
  207. DMA_FROM_DEVICE);
  208. return ret;
  209. }
  210. EXPORT_SYMBOL(mipi_dbi_buf_copy);
  211. static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
  212. unsigned int xs, unsigned int xe,
  213. unsigned int ys, unsigned int ye)
  214. {
  215. struct mipi_dbi *dbi = &dbidev->dbi;
  216. xs += dbidev->left_offset;
  217. xe += dbidev->left_offset;
  218. ys += dbidev->top_offset;
  219. ye += dbidev->top_offset;
  220. mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
  221. xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
  222. mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
  223. ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
  224. }
  225. static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
  226. {
  227. struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
  228. struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
  229. struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
  230. unsigned int height = rect->y2 - rect->y1;
  231. unsigned int width = rect->x2 - rect->x1;
  232. struct mipi_dbi *dbi = &dbidev->dbi;
  233. bool swap = dbi->swap_bytes;
  234. int idx, ret = 0;
  235. bool full;
  236. void *tr;
  237. if (WARN_ON(!fb))
  238. return;
  239. if (!drm_dev_enter(fb->dev, &idx))
  240. return;
  241. full = width == fb->width && height == fb->height;
  242. DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
  243. if (!dbi->dc || !full || swap ||
  244. fb->format->format == DRM_FORMAT_XRGB8888) {
  245. tr = dbidev->tx_buf;
  246. ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
  247. if (ret)
  248. goto err_msg;
  249. } else {
  250. tr = cma_obj->vaddr;
  251. }
  252. mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
  253. rect->y2 - 1);
  254. ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
  255. width * height * 2);
  256. err_msg:
  257. if (ret)
  258. drm_err_once(fb->dev, "Failed to update display %d\n", ret);
  259. drm_dev_exit(idx);
  260. }
  261. /**
  262. * mipi_dbi_pipe_update - Display pipe update helper
  263. * @pipe: Simple display pipe
  264. * @old_state: Old plane state
  265. *
  266. * This function handles framebuffer flushing and vblank events. Drivers can use
  267. * this as their &drm_simple_display_pipe_funcs->update callback.
  268. */
  269. void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
  270. struct drm_plane_state *old_state)
  271. {
  272. struct drm_plane_state *state = pipe->plane.state;
  273. struct drm_rect rect;
  274. if (!pipe->crtc.state->active)
  275. return;
  276. if (drm_atomic_helper_damage_merged(old_state, state, &rect))
  277. mipi_dbi_fb_dirty(state->fb, &rect);
  278. }
  279. EXPORT_SYMBOL(mipi_dbi_pipe_update);
  280. /**
  281. * mipi_dbi_enable_flush - MIPI DBI enable helper
  282. * @dbidev: MIPI DBI device structure
  283. * @crtc_state: CRTC state
  284. * @plane_state: Plane state
  285. *
  286. * Flushes the whole framebuffer and enables the backlight. Drivers can use this
  287. * in their &drm_simple_display_pipe_funcs->enable callback.
  288. *
  289. * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
  290. * framebuffer flushing, can't use this function since they both use the same
  291. * flushing code.
  292. */
  293. void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
  294. struct drm_crtc_state *crtc_state,
  295. struct drm_plane_state *plane_state)
  296. {
  297. struct drm_framebuffer *fb = plane_state->fb;
  298. struct drm_rect rect = {
  299. .x1 = 0,
  300. .x2 = fb->width,
  301. .y1 = 0,
  302. .y2 = fb->height,
  303. };
  304. int idx;
  305. if (!drm_dev_enter(&dbidev->drm, &idx))
  306. return;
  307. mipi_dbi_fb_dirty(fb, &rect);
  308. backlight_enable(dbidev->backlight);
  309. drm_dev_exit(idx);
  310. }
  311. EXPORT_SYMBOL(mipi_dbi_enable_flush);
  312. static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
  313. {
  314. struct drm_device *drm = &dbidev->drm;
  315. u16 height = drm->mode_config.min_height;
  316. u16 width = drm->mode_config.min_width;
  317. struct mipi_dbi *dbi = &dbidev->dbi;
  318. size_t len = width * height * 2;
  319. int idx;
  320. if (!drm_dev_enter(drm, &idx))
  321. return;
  322. memset(dbidev->tx_buf, 0, len);
  323. mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
  324. mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
  325. (u8 *)dbidev->tx_buf, len);
  326. drm_dev_exit(idx);
  327. }
  328. /**
  329. * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
  330. * @pipe: Display pipe
  331. *
  332. * This function disables backlight if present, if not the display memory is
  333. * blanked. The regulator is disabled if in use. Drivers can use this as their
  334. * &drm_simple_display_pipe_funcs->disable callback.
  335. */
  336. void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
  337. {
  338. struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
  339. DRM_DEBUG_KMS("\n");
  340. if (dbidev->backlight)
  341. backlight_disable(dbidev->backlight);
  342. else
  343. mipi_dbi_blank(dbidev);
  344. if (dbidev->regulator)
  345. regulator_disable(dbidev->regulator);
  346. }
  347. EXPORT_SYMBOL(mipi_dbi_pipe_disable);
  348. static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
  349. {
  350. struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
  351. struct drm_display_mode *mode;
  352. mode = drm_mode_duplicate(connector->dev, &dbidev->mode);
  353. if (!mode) {
  354. DRM_ERROR("Failed to duplicate mode\n");
  355. return 0;
  356. }
  357. if (mode->name[0] == '\0')
  358. drm_mode_set_name(mode);
  359. mode->type |= DRM_MODE_TYPE_PREFERRED;
  360. drm_mode_probed_add(connector, mode);
  361. if (mode->width_mm) {
  362. connector->display_info.width_mm = mode->width_mm;
  363. connector->display_info.height_mm = mode->height_mm;
  364. }
  365. return 1;
  366. }
  367. static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
  368. .get_modes = mipi_dbi_connector_get_modes,
  369. };
  370. static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
  371. .reset = drm_atomic_helper_connector_reset,
  372. .fill_modes = drm_helper_probe_single_connector_modes,
  373. .destroy = drm_connector_cleanup,
  374. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  375. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  376. };
  377. static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
  378. unsigned int rotation)
  379. {
  380. if (rotation == 0 || rotation == 180) {
  381. return 0;
  382. } else if (rotation == 90 || rotation == 270) {
  383. swap(mode->hdisplay, mode->vdisplay);
  384. swap(mode->hsync_start, mode->vsync_start);
  385. swap(mode->hsync_end, mode->vsync_end);
  386. swap(mode->htotal, mode->vtotal);
  387. swap(mode->width_mm, mode->height_mm);
  388. return 0;
  389. } else {
  390. return -EINVAL;
  391. }
  392. }
  393. static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
  394. .fb_create = drm_gem_fb_create_with_dirty,
  395. .atomic_check = drm_atomic_helper_check,
  396. .atomic_commit = drm_atomic_helper_commit,
  397. };
  398. static const uint32_t mipi_dbi_formats[] = {
  399. DRM_FORMAT_RGB565,
  400. DRM_FORMAT_XRGB8888,
  401. };
  402. /**
  403. * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
  404. * @dbidev: MIPI DBI device structure to initialize
  405. * @funcs: Display pipe functions
  406. * @formats: Array of supported formats (DRM_FORMAT\_\*).
  407. * @format_count: Number of elements in @formats
  408. * @mode: Display mode
  409. * @rotation: Initial rotation in degrees Counter Clock Wise
  410. * @tx_buf_size: Allocate a transmit buffer of this size.
  411. *
  412. * This function sets up a &drm_simple_display_pipe with a &drm_connector that
  413. * has one fixed &drm_display_mode which is rotated according to @rotation.
  414. * This mode is used to set the mode config min/max width/height properties.
  415. *
  416. * Use mipi_dbi_dev_init() if you don't need custom formats.
  417. *
  418. * Note:
  419. * Some of the helper functions expects RGB565 to be the default format and the
  420. * transmit buffer sized to fit that.
  421. *
  422. * Returns:
  423. * Zero on success, negative error code on failure.
  424. */
  425. int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
  426. const struct drm_simple_display_pipe_funcs *funcs,
  427. const uint32_t *formats, unsigned int format_count,
  428. const struct drm_display_mode *mode,
  429. unsigned int rotation, size_t tx_buf_size)
  430. {
  431. static const uint64_t modifiers[] = {
  432. DRM_FORMAT_MOD_LINEAR,
  433. DRM_FORMAT_MOD_INVALID
  434. };
  435. struct drm_device *drm = &dbidev->drm;
  436. int ret;
  437. if (!dbidev->dbi.command)
  438. return -EINVAL;
  439. ret = drmm_mode_config_init(drm);
  440. if (ret)
  441. return ret;
  442. dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
  443. if (!dbidev->tx_buf)
  444. return -ENOMEM;
  445. drm_mode_copy(&dbidev->mode, mode);
  446. ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
  447. if (ret) {
  448. DRM_ERROR("Illegal rotation value %u\n", rotation);
  449. return -EINVAL;
  450. }
  451. drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
  452. ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
  453. DRM_MODE_CONNECTOR_SPI);
  454. if (ret)
  455. return ret;
  456. ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
  457. modifiers, &dbidev->connector);
  458. if (ret)
  459. return ret;
  460. drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
  461. drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
  462. drm->mode_config.min_width = dbidev->mode.hdisplay;
  463. drm->mode_config.max_width = dbidev->mode.hdisplay;
  464. drm->mode_config.min_height = dbidev->mode.vdisplay;
  465. drm->mode_config.max_height = dbidev->mode.vdisplay;
  466. dbidev->rotation = rotation;
  467. DRM_DEBUG_KMS("rotation = %u\n", rotation);
  468. return 0;
  469. }
  470. EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
  471. /**
  472. * mipi_dbi_dev_init - MIPI DBI device initialization
  473. * @dbidev: MIPI DBI device structure to initialize
  474. * @funcs: Display pipe functions
  475. * @mode: Display mode
  476. * @rotation: Initial rotation in degrees Counter Clock Wise
  477. *
  478. * This function sets up a &drm_simple_display_pipe with a &drm_connector that
  479. * has one fixed &drm_display_mode which is rotated according to @rotation.
  480. * This mode is used to set the mode config min/max width/height properties.
  481. * Additionally &mipi_dbi.tx_buf is allocated.
  482. *
  483. * Supported formats: Native RGB565 and emulated XRGB8888.
  484. *
  485. * Returns:
  486. * Zero on success, negative error code on failure.
  487. */
  488. int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
  489. const struct drm_simple_display_pipe_funcs *funcs,
  490. const struct drm_display_mode *mode, unsigned int rotation)
  491. {
  492. size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
  493. dbidev->drm.mode_config.preferred_depth = 16;
  494. return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
  495. ARRAY_SIZE(mipi_dbi_formats), mode,
  496. rotation, bufsize);
  497. }
  498. EXPORT_SYMBOL(mipi_dbi_dev_init);
  499. /**
  500. * mipi_dbi_hw_reset - Hardware reset of controller
  501. * @dbi: MIPI DBI structure
  502. *
  503. * Reset controller if the &mipi_dbi->reset gpio is set.
  504. */
  505. void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
  506. {
  507. if (!dbi->reset)
  508. return;
  509. gpiod_set_value_cansleep(dbi->reset, 0);
  510. usleep_range(20, 1000);
  511. gpiod_set_value_cansleep(dbi->reset, 1);
  512. msleep(120);
  513. }
  514. EXPORT_SYMBOL(mipi_dbi_hw_reset);
  515. /**
  516. * mipi_dbi_display_is_on - Check if display is on
  517. * @dbi: MIPI DBI structure
  518. *
  519. * This function checks the Power Mode register (if readable) to see if
  520. * display output is turned on. This can be used to see if the bootloader
  521. * has already turned on the display avoiding flicker when the pipeline is
  522. * enabled.
  523. *
  524. * Returns:
  525. * true if the display can be verified to be on, false otherwise.
  526. */
  527. bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
  528. {
  529. u8 val;
  530. if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
  531. return false;
  532. val &= ~DCS_POWER_MODE_RESERVED_MASK;
  533. /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
  534. if (val != (DCS_POWER_MODE_DISPLAY |
  535. DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
  536. return false;
  537. DRM_DEBUG_DRIVER("Display is ON\n");
  538. return true;
  539. }
  540. EXPORT_SYMBOL(mipi_dbi_display_is_on);
  541. static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
  542. {
  543. struct device *dev = dbidev->drm.dev;
  544. struct mipi_dbi *dbi = &dbidev->dbi;
  545. int ret;
  546. if (dbidev->regulator) {
  547. ret = regulator_enable(dbidev->regulator);
  548. if (ret) {
  549. DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
  550. return ret;
  551. }
  552. }
  553. if (cond && mipi_dbi_display_is_on(dbi))
  554. return 1;
  555. mipi_dbi_hw_reset(dbi);
  556. ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
  557. if (ret) {
  558. DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
  559. if (dbidev->regulator)
  560. regulator_disable(dbidev->regulator);
  561. return ret;
  562. }
  563. /*
  564. * If we did a hw reset, we know the controller is in Sleep mode and
  565. * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
  566. * we assume worst case and wait 120ms.
  567. */
  568. if (dbi->reset)
  569. usleep_range(5000, 20000);
  570. else
  571. msleep(120);
  572. return 0;
  573. }
  574. /**
  575. * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
  576. * @dbidev: MIPI DBI device structure
  577. *
  578. * This function enables the regulator if used and does a hardware and software
  579. * reset.
  580. *
  581. * Returns:
  582. * Zero on success, or a negative error code.
  583. */
  584. int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
  585. {
  586. return mipi_dbi_poweron_reset_conditional(dbidev, false);
  587. }
  588. EXPORT_SYMBOL(mipi_dbi_poweron_reset);
  589. /**
  590. * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
  591. * @dbidev: MIPI DBI device structure
  592. *
  593. * This function enables the regulator if used and if the display is off, it
  594. * does a hardware and software reset. If mipi_dbi_display_is_on() determines
  595. * that the display is on, no reset is performed.
  596. *
  597. * Returns:
  598. * Zero if the controller was reset, 1 if the display was already on, or a
  599. * negative error code.
  600. */
  601. int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
  602. {
  603. return mipi_dbi_poweron_reset_conditional(dbidev, true);
  604. }
  605. EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
  606. #if IS_ENABLED(CONFIG_SPI)
  607. /**
  608. * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
  609. * @spi: SPI device
  610. * @len: The transfer buffer length.
  611. *
  612. * Many controllers have a max speed of 10MHz, but can be pushed way beyond
  613. * that. Increase reliability by running pixel data at max speed and the rest
  614. * at 10MHz, preventing transfer glitches from messing up the init settings.
  615. */
  616. u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
  617. {
  618. if (len > 64)
  619. return 0; /* use default */
  620. return min_t(u32, 10000000, spi->max_speed_hz);
  621. }
  622. EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
  623. static bool mipi_dbi_machine_little_endian(void)
  624. {
  625. #if defined(__LITTLE_ENDIAN)
  626. return true;
  627. #else
  628. return false;
  629. #endif
  630. }
  631. /*
  632. * MIPI DBI Type C Option 1
  633. *
  634. * If the SPI controller doesn't have 9 bits per word support,
  635. * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
  636. * Pad partial blocks with MIPI_DCS_NOP (zero).
  637. * This is how the D/C bit (x) is added:
  638. * x7654321
  639. * 0x765432
  640. * 10x76543
  641. * 210x7654
  642. * 3210x765
  643. * 43210x76
  644. * 543210x7
  645. * 6543210x
  646. * 76543210
  647. */
  648. static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
  649. const void *buf, size_t len,
  650. unsigned int bpw)
  651. {
  652. bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());
  653. size_t chunk, max_chunk = dbi->tx_buf9_len;
  654. struct spi_device *spi = dbi->spi;
  655. struct spi_transfer tr = {
  656. .tx_buf = dbi->tx_buf9,
  657. .bits_per_word = 8,
  658. };
  659. struct spi_message m;
  660. const u8 *src = buf;
  661. int i, ret;
  662. u8 *dst;
  663. if (drm_debug_enabled(DRM_UT_DRIVER))
  664. pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
  665. __func__, dc, max_chunk);
  666. tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
  667. spi_message_init_with_transfers(&m, &tr, 1);
  668. if (!dc) {
  669. if (WARN_ON_ONCE(len != 1))
  670. return -EINVAL;
  671. /* Command: pad no-op's (zeroes) at beginning of block */
  672. dst = dbi->tx_buf9;
  673. memset(dst, 0, 9);
  674. dst[8] = *src;
  675. tr.len = 9;
  676. return spi_sync(spi, &m);
  677. }
  678. /* max with room for adding one bit per byte */
  679. max_chunk = max_chunk / 9 * 8;
  680. /* but no bigger than len */
  681. max_chunk = min(max_chunk, len);
  682. /* 8 byte blocks */
  683. max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
  684. while (len) {
  685. size_t added = 0;
  686. chunk = min(len, max_chunk);
  687. len -= chunk;
  688. dst = dbi->tx_buf9;
  689. if (chunk < 8) {
  690. u8 val, carry = 0;
  691. /* Data: pad no-op's (zeroes) at end of block */
  692. memset(dst, 0, 9);
  693. if (swap_bytes) {
  694. for (i = 1; i < (chunk + 1); i++) {
  695. val = src[1];
  696. *dst++ = carry | BIT(8 - i) | (val >> i);
  697. carry = val << (8 - i);
  698. i++;
  699. val = src[0];
  700. *dst++ = carry | BIT(8 - i) | (val >> i);
  701. carry = val << (8 - i);
  702. src += 2;
  703. }
  704. *dst++ = carry;
  705. } else {
  706. for (i = 1; i < (chunk + 1); i++) {
  707. val = *src++;
  708. *dst++ = carry | BIT(8 - i) | (val >> i);
  709. carry = val << (8 - i);
  710. }
  711. *dst++ = carry;
  712. }
  713. chunk = 8;
  714. added = 1;
  715. } else {
  716. for (i = 0; i < chunk; i += 8) {
  717. if (swap_bytes) {
  718. *dst++ = BIT(7) | (src[1] >> 1);
  719. *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
  720. *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
  721. *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
  722. *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
  723. *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
  724. *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
  725. *dst++ = (src[7] << 1) | BIT(0);
  726. *dst++ = src[6];
  727. } else {
  728. *dst++ = BIT(7) | (src[0] >> 1);
  729. *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
  730. *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
  731. *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
  732. *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
  733. *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
  734. *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
  735. *dst++ = (src[6] << 1) | BIT(0);
  736. *dst++ = src[7];
  737. }
  738. src += 8;
  739. added++;
  740. }
  741. }
  742. tr.len = chunk + added;
  743. ret = spi_sync(spi, &m);
  744. if (ret)
  745. return ret;
  746. }
  747. return 0;
  748. }
  749. static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
  750. const void *buf, size_t len,
  751. unsigned int bpw)
  752. {
  753. struct spi_device *spi = dbi->spi;
  754. struct spi_transfer tr = {
  755. .bits_per_word = 9,
  756. };
  757. const u16 *src16 = buf;
  758. const u8 *src8 = buf;
  759. struct spi_message m;
  760. size_t max_chunk;
  761. u16 *dst16;
  762. int ret;
  763. if (!spi_is_bpw_supported(spi, 9))
  764. return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
  765. tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
  766. max_chunk = dbi->tx_buf9_len;
  767. dst16 = dbi->tx_buf9;
  768. if (drm_debug_enabled(DRM_UT_DRIVER))
  769. pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
  770. __func__, dc, max_chunk);
  771. max_chunk = min(max_chunk / 2, len);
  772. spi_message_init_with_transfers(&m, &tr, 1);
  773. tr.tx_buf = dst16;
  774. while (len) {
  775. size_t chunk = min(len, max_chunk);
  776. unsigned int i;
  777. if (bpw == 16 && mipi_dbi_machine_little_endian()) {
  778. for (i = 0; i < (chunk * 2); i += 2) {
  779. dst16[i] = *src16 >> 8;
  780. dst16[i + 1] = *src16++ & 0xFF;
  781. if (dc) {
  782. dst16[i] |= 0x0100;
  783. dst16[i + 1] |= 0x0100;
  784. }
  785. }
  786. } else {
  787. for (i = 0; i < chunk; i++) {
  788. dst16[i] = *src8++;
  789. if (dc)
  790. dst16[i] |= 0x0100;
  791. }
  792. }
  793. tr.len = chunk * 2;
  794. len -= chunk;
  795. ret = spi_sync(spi, &m);
  796. if (ret)
  797. return ret;
  798. }
  799. return 0;
  800. }
  801. static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
  802. u8 *parameters, size_t num)
  803. {
  804. unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
  805. int ret;
  806. if (mipi_dbi_command_is_read(dbi, *cmd))
  807. return -EOPNOTSUPP;
  808. MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
  809. ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
  810. if (ret || !num)
  811. return ret;
  812. return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
  813. }
  814. /* MIPI DBI Type C Option 3 */
  815. static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
  816. u8 *data, size_t len)
  817. {
  818. struct spi_device *spi = dbi->spi;
  819. u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
  820. spi->max_speed_hz / 2);
  821. struct spi_transfer tr[2] = {
  822. {
  823. .speed_hz = speed_hz,
  824. .tx_buf = cmd,
  825. .len = 1,
  826. }, {
  827. .speed_hz = speed_hz,
  828. .len = len,
  829. },
  830. };
  831. struct spi_message m;
  832. u8 *buf;
  833. int ret;
  834. if (!len)
  835. return -EINVAL;
  836. /*
  837. * Support non-standard 24-bit and 32-bit Nokia read commands which
  838. * start with a dummy clock, so we need to read an extra byte.
  839. */
  840. if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
  841. *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
  842. if (!(len == 3 || len == 4))
  843. return -EINVAL;
  844. tr[1].len = len + 1;
  845. }
  846. buf = kmalloc(tr[1].len, GFP_KERNEL);
  847. if (!buf)
  848. return -ENOMEM;
  849. tr[1].rx_buf = buf;
  850. gpiod_set_value_cansleep(dbi->dc, 0);
  851. spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
  852. ret = spi_sync(spi, &m);
  853. if (ret)
  854. goto err_free;
  855. if (tr[1].len == len) {
  856. memcpy(data, buf, len);
  857. } else {
  858. unsigned int i;
  859. for (i = 0; i < len; i++)
  860. data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
  861. }
  862. MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
  863. err_free:
  864. kfree(buf);
  865. return ret;
  866. }
  867. static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
  868. u8 *par, size_t num)
  869. {
  870. struct spi_device *spi = dbi->spi;
  871. unsigned int bpw = 8;
  872. u32 speed_hz;
  873. int ret;
  874. if (mipi_dbi_command_is_read(dbi, *cmd))
  875. return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
  876. MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
  877. gpiod_set_value_cansleep(dbi->dc, 0);
  878. speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
  879. ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
  880. if (ret || !num)
  881. return ret;
  882. if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
  883. bpw = 16;
  884. gpiod_set_value_cansleep(dbi->dc, 1);
  885. speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
  886. return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
  887. }
  888. /**
  889. * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
  890. * @spi: SPI device
  891. * @dbi: MIPI DBI structure to initialize
  892. * @dc: D/C gpio (optional)
  893. *
  894. * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
  895. * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
  896. * a driver-specific init.
  897. *
  898. * If @dc is set, a Type C Option 3 interface is assumed, if not
  899. * Type C Option 1.
  900. *
  901. * If the SPI master driver doesn't support the necessary bits per word,
  902. * the following transformation is used:
  903. *
  904. * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
  905. * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
  906. *
  907. * Returns:
  908. * Zero on success, negative error code on failure.
  909. */
  910. int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
  911. struct gpio_desc *dc)
  912. {
  913. struct device *dev = &spi->dev;
  914. int ret;
  915. /*
  916. * Even though it's not the SPI device that does DMA (the master does),
  917. * the dma mask is necessary for the dma_alloc_wc() in
  918. * drm_gem_cma_create(). The dma_addr returned will be a physical
  919. * address which might be different from the bus address, but this is
  920. * not a problem since the address will not be used.
  921. * The virtual address is used in the transfer and the SPI core
  922. * re-maps it on the SPI master device using the DMA streaming API
  923. * (spi_map_buf()).
  924. */
  925. if (!dev->coherent_dma_mask) {
  926. ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
  927. if (ret) {
  928. dev_warn(dev, "Failed to set dma mask %d\n", ret);
  929. return ret;
  930. }
  931. }
  932. dbi->spi = spi;
  933. dbi->read_commands = mipi_dbi_dcs_read_commands;
  934. if (dc) {
  935. dbi->command = mipi_dbi_typec3_command;
  936. dbi->dc = dc;
  937. if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
  938. dbi->swap_bytes = true;
  939. } else {
  940. dbi->command = mipi_dbi_typec1_command;
  941. dbi->tx_buf9_len = SZ_16K;
  942. dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
  943. if (!dbi->tx_buf9)
  944. return -ENOMEM;
  945. }
  946. mutex_init(&dbi->cmdlock);
  947. DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
  948. return 0;
  949. }
  950. EXPORT_SYMBOL(mipi_dbi_spi_init);
  951. /**
  952. * mipi_dbi_spi_transfer - SPI transfer helper
  953. * @spi: SPI device
  954. * @speed_hz: Override speed (optional)
  955. * @bpw: Bits per word
  956. * @buf: Buffer to transfer
  957. * @len: Buffer length
  958. *
  959. * This SPI transfer helper breaks up the transfer of @buf into chunks which
  960. * the SPI controller driver can handle.
  961. *
  962. * Returns:
  963. * Zero on success, negative error code on failure.
  964. */
  965. int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
  966. u8 bpw, const void *buf, size_t len)
  967. {
  968. size_t max_chunk = spi_max_transfer_size(spi);
  969. struct spi_transfer tr = {
  970. .bits_per_word = bpw,
  971. .speed_hz = speed_hz,
  972. };
  973. struct spi_message m;
  974. size_t chunk;
  975. int ret;
  976. spi_message_init_with_transfers(&m, &tr, 1);
  977. while (len) {
  978. chunk = min(len, max_chunk);
  979. tr.tx_buf = buf;
  980. tr.len = chunk;
  981. buf += chunk;
  982. len -= chunk;
  983. ret = spi_sync(spi, &m);
  984. if (ret)
  985. return ret;
  986. }
  987. return 0;
  988. }
  989. EXPORT_SYMBOL(mipi_dbi_spi_transfer);
  990. #endif /* CONFIG_SPI */
  991. #ifdef CONFIG_DEBUG_FS
  992. static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
  993. const char __user *ubuf,
  994. size_t count, loff_t *ppos)
  995. {
  996. struct seq_file *m = file->private_data;
  997. struct mipi_dbi_dev *dbidev = m->private;
  998. u8 val, cmd = 0, parameters[64];
  999. char *buf, *pos, *token;
  1000. int i, ret, idx;
  1001. if (!drm_dev_enter(&dbidev->drm, &idx))
  1002. return -ENODEV;
  1003. buf = memdup_user_nul(ubuf, count);
  1004. if (IS_ERR(buf)) {
  1005. ret = PTR_ERR(buf);
  1006. goto err_exit;
  1007. }
  1008. /* strip trailing whitespace */
  1009. for (i = count - 1; i > 0; i--)
  1010. if (isspace(buf[i]))
  1011. buf[i] = '\0';
  1012. else
  1013. break;
  1014. i = 0;
  1015. pos = buf;
  1016. while (pos) {
  1017. token = strsep(&pos, " ");
  1018. if (!token) {
  1019. ret = -EINVAL;
  1020. goto err_free;
  1021. }
  1022. ret = kstrtou8(token, 16, &val);
  1023. if (ret < 0)
  1024. goto err_free;
  1025. if (token == buf)
  1026. cmd = val;
  1027. else
  1028. parameters[i++] = val;
  1029. if (i == 64) {
  1030. ret = -E2BIG;
  1031. goto err_free;
  1032. }
  1033. }
  1034. ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
  1035. err_free:
  1036. kfree(buf);
  1037. err_exit:
  1038. drm_dev_exit(idx);
  1039. return ret < 0 ? ret : count;
  1040. }
  1041. static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
  1042. {
  1043. struct mipi_dbi_dev *dbidev = m->private;
  1044. struct mipi_dbi *dbi = &dbidev->dbi;
  1045. u8 cmd, val[4];
  1046. int ret, idx;
  1047. size_t len;
  1048. if (!drm_dev_enter(&dbidev->drm, &idx))
  1049. return -ENODEV;
  1050. for (cmd = 0; cmd < 255; cmd++) {
  1051. if (!mipi_dbi_command_is_read(dbi, cmd))
  1052. continue;
  1053. switch (cmd) {
  1054. case MIPI_DCS_READ_MEMORY_START:
  1055. case MIPI_DCS_READ_MEMORY_CONTINUE:
  1056. len = 2;
  1057. break;
  1058. case MIPI_DCS_GET_DISPLAY_ID:
  1059. len = 3;
  1060. break;
  1061. case MIPI_DCS_GET_DISPLAY_STATUS:
  1062. len = 4;
  1063. break;
  1064. default:
  1065. len = 1;
  1066. break;
  1067. }
  1068. seq_printf(m, "%02x: ", cmd);
  1069. ret = mipi_dbi_command_buf(dbi, cmd, val, len);
  1070. if (ret) {
  1071. seq_puts(m, "XX\n");
  1072. continue;
  1073. }
  1074. seq_printf(m, "%*phN\n", (int)len, val);
  1075. }
  1076. drm_dev_exit(idx);
  1077. return 0;
  1078. }
  1079. static int mipi_dbi_debugfs_command_open(struct inode *inode,
  1080. struct file *file)
  1081. {
  1082. return single_open(file, mipi_dbi_debugfs_command_show,
  1083. inode->i_private);
  1084. }
  1085. static const struct file_operations mipi_dbi_debugfs_command_fops = {
  1086. .owner = THIS_MODULE,
  1087. .open = mipi_dbi_debugfs_command_open,
  1088. .read = seq_read,
  1089. .llseek = seq_lseek,
  1090. .release = single_release,
  1091. .write = mipi_dbi_debugfs_command_write,
  1092. };
  1093. /**
  1094. * mipi_dbi_debugfs_init - Create debugfs entries
  1095. * @minor: DRM minor
  1096. *
  1097. * This function creates a 'command' debugfs file for sending commands to the
  1098. * controller or getting the read command values.
  1099. * Drivers can use this as their &drm_driver->debugfs_init callback.
  1100. *
  1101. */
  1102. void mipi_dbi_debugfs_init(struct drm_minor *minor)
  1103. {
  1104. struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
  1105. umode_t mode = S_IFREG | S_IWUSR;
  1106. if (dbidev->dbi.read_commands)
  1107. mode |= S_IRUGO;
  1108. debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
  1109. &mipi_dbi_debugfs_command_fops);
  1110. }
  1111. EXPORT_SYMBOL(mipi_dbi_debugfs_init);
  1112. #endif
  1113. MODULE_LICENSE("GPL");