drm_edid.c 182 KB

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  1. /*
  2. * Copyright (c) 2006 Luc Verhaegen (quirks list)
  3. * Copyright (c) 2007-2008 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. * Copyright 2010 Red Hat, Inc.
  6. *
  7. * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
  8. * FB layer.
  9. * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
  10. *
  11. * Permission is hereby granted, free of charge, to any person obtaining a
  12. * copy of this software and associated documentation files (the "Software"),
  13. * to deal in the Software without restriction, including without limitation
  14. * the rights to use, copy, modify, merge, publish, distribute, sub license,
  15. * and/or sell copies of the Software, and to permit persons to whom the
  16. * Software is furnished to do so, subject to the following conditions:
  17. *
  18. * The above copyright notice and this permission notice (including the
  19. * next paragraph) shall be included in all copies or substantial portions
  20. * of the Software.
  21. *
  22. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  25. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  27. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28. * DEALINGS IN THE SOFTWARE.
  29. */
  30. #include <linux/hdmi.h>
  31. #include <linux/i2c.h>
  32. #include <linux/kernel.h>
  33. #include <linux/module.h>
  34. #include <linux/slab.h>
  35. #include <linux/vga_switcheroo.h>
  36. #include <drm/drm_displayid.h>
  37. #include <drm/drm_drv.h>
  38. #include <drm/drm_edid.h>
  39. #include <drm/drm_encoder.h>
  40. #include <drm/drm_print.h>
  41. #include <drm/drm_scdc_helper.h>
  42. #include "drm_crtc_internal.h"
  43. #define version_greater(edid, maj, min) \
  44. (((edid)->version > (maj)) || \
  45. ((edid)->version == (maj) && (edid)->revision > (min)))
  46. #define EDID_EST_TIMINGS 16
  47. #define EDID_STD_TIMINGS 8
  48. #define EDID_DETAILED_TIMINGS 4
  49. /*
  50. * EDID blocks out in the wild have a variety of bugs, try to collect
  51. * them here (note that userspace may work around broken monitors first,
  52. * but fixes should make their way here so that the kernel "just works"
  53. * on as many displays as possible).
  54. */
  55. /* First detailed mode wrong, use largest 60Hz mode */
  56. #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
  57. /* Reported 135MHz pixel clock is too high, needs adjustment */
  58. #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
  59. /* Prefer the largest mode at 75 Hz */
  60. #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
  61. /* Detail timing is in cm not mm */
  62. #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
  63. /* Detailed timing descriptors have bogus size values, so just take the
  64. * maximum size and use that.
  65. */
  66. #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
  67. /* use +hsync +vsync for detailed mode */
  68. #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
  69. /* Force reduced-blanking timings for detailed modes */
  70. #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
  71. /* Force 8bpc */
  72. #define EDID_QUIRK_FORCE_8BPC (1 << 8)
  73. /* Force 12bpc */
  74. #define EDID_QUIRK_FORCE_12BPC (1 << 9)
  75. /* Force 6bpc */
  76. #define EDID_QUIRK_FORCE_6BPC (1 << 10)
  77. /* Force 10bpc */
  78. #define EDID_QUIRK_FORCE_10BPC (1 << 11)
  79. /* Non desktop display (i.e. HMD) */
  80. #define EDID_QUIRK_NON_DESKTOP (1 << 12)
  81. struct detailed_mode_closure {
  82. struct drm_connector *connector;
  83. struct edid *edid;
  84. bool preferred;
  85. u32 quirks;
  86. int modes;
  87. };
  88. #define LEVEL_DMT 0
  89. #define LEVEL_GTF 1
  90. #define LEVEL_GTF2 2
  91. #define LEVEL_CVT 3
  92. static const struct edid_quirk {
  93. char vendor[4];
  94. int product_id;
  95. u32 quirks;
  96. } edid_quirk_list[] = {
  97. /* Acer AL1706 */
  98. { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
  99. /* Acer F51 */
  100. { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
  101. /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
  102. { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
  103. /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
  104. { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
  105. /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
  106. { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
  107. /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
  108. { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
  109. /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
  110. { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
  111. /* Belinea 10 15 55 */
  112. { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
  113. { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
  114. /* Envision Peripherals, Inc. EN-7100e */
  115. { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
  116. /* Envision EN2028 */
  117. { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
  118. /* Funai Electronics PM36B */
  119. { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
  120. EDID_QUIRK_DETAILED_IN_CM },
  121. /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
  122. { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
  123. /* LG Philips LCD LP154W01-A5 */
  124. { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
  125. { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
  126. /* Samsung SyncMaster 205BW. Note: irony */
  127. { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
  128. /* Samsung SyncMaster 22[5-6]BW */
  129. { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
  130. { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
  131. /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
  132. { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
  133. /* ViewSonic VA2026w */
  134. { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
  135. /* Medion MD 30217 PG */
  136. { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
  137. /* Lenovo G50 */
  138. { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
  139. /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
  140. { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
  141. /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
  142. { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
  143. /* Valve Index Headset */
  144. { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
  145. { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
  146. { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
  147. { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
  148. { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
  149. { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
  150. { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
  151. { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
  152. { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
  153. { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
  154. { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
  155. { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
  156. { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
  157. { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
  158. { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
  159. { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
  160. { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
  161. /* HTC Vive and Vive Pro VR Headsets */
  162. { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
  163. { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
  164. /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
  165. { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
  166. { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
  167. { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
  168. { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
  169. /* Windows Mixed Reality Headsets */
  170. { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
  171. { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
  172. { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
  173. { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
  174. { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
  175. { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
  176. { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
  177. { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
  178. /* Sony PlayStation VR Headset */
  179. { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
  180. /* Sensics VR Headsets */
  181. { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
  182. /* OSVR HDK and HDK2 VR Headsets */
  183. { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
  184. };
  185. /*
  186. * Autogenerated from the DMT spec.
  187. * This table is copied from xfree86/modes/xf86EdidModes.c.
  188. */
  189. static const struct drm_display_mode drm_dmt_modes[] = {
  190. /* 0x01 - 640x350@85Hz */
  191. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
  192. 736, 832, 0, 350, 382, 385, 445, 0,
  193. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  194. /* 0x02 - 640x400@85Hz */
  195. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
  196. 736, 832, 0, 400, 401, 404, 445, 0,
  197. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  198. /* 0x03 - 720x400@85Hz */
  199. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
  200. 828, 936, 0, 400, 401, 404, 446, 0,
  201. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  202. /* 0x04 - 640x480@60Hz */
  203. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  204. 752, 800, 0, 480, 490, 492, 525, 0,
  205. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  206. /* 0x05 - 640x480@72Hz */
  207. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
  208. 704, 832, 0, 480, 489, 492, 520, 0,
  209. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  210. /* 0x06 - 640x480@75Hz */
  211. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
  212. 720, 840, 0, 480, 481, 484, 500, 0,
  213. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  214. /* 0x07 - 640x480@85Hz */
  215. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
  216. 752, 832, 0, 480, 481, 484, 509, 0,
  217. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  218. /* 0x08 - 800x600@56Hz */
  219. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
  220. 896, 1024, 0, 600, 601, 603, 625, 0,
  221. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  222. /* 0x09 - 800x600@60Hz */
  223. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  224. 968, 1056, 0, 600, 601, 605, 628, 0,
  225. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  226. /* 0x0a - 800x600@72Hz */
  227. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
  228. 976, 1040, 0, 600, 637, 643, 666, 0,
  229. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  230. /* 0x0b - 800x600@75Hz */
  231. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
  232. 896, 1056, 0, 600, 601, 604, 625, 0,
  233. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  234. /* 0x0c - 800x600@85Hz */
  235. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
  236. 896, 1048, 0, 600, 601, 604, 631, 0,
  237. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  238. /* 0x0d - 800x600@120Hz RB */
  239. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
  240. 880, 960, 0, 600, 603, 607, 636, 0,
  241. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  242. /* 0x0e - 848x480@60Hz */
  243. { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
  244. 976, 1088, 0, 480, 486, 494, 517, 0,
  245. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  246. /* 0x0f - 1024x768@43Hz, interlace */
  247. { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
  248. 1208, 1264, 0, 768, 768, 776, 817, 0,
  249. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  250. DRM_MODE_FLAG_INTERLACE) },
  251. /* 0x10 - 1024x768@60Hz */
  252. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  253. 1184, 1344, 0, 768, 771, 777, 806, 0,
  254. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  255. /* 0x11 - 1024x768@70Hz */
  256. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
  257. 1184, 1328, 0, 768, 771, 777, 806, 0,
  258. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  259. /* 0x12 - 1024x768@75Hz */
  260. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
  261. 1136, 1312, 0, 768, 769, 772, 800, 0,
  262. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  263. /* 0x13 - 1024x768@85Hz */
  264. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
  265. 1168, 1376, 0, 768, 769, 772, 808, 0,
  266. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  267. /* 0x14 - 1024x768@120Hz RB */
  268. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
  269. 1104, 1184, 0, 768, 771, 775, 813, 0,
  270. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  271. /* 0x15 - 1152x864@75Hz */
  272. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  273. 1344, 1600, 0, 864, 865, 868, 900, 0,
  274. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  275. /* 0x55 - 1280x720@60Hz */
  276. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
  277. 1430, 1650, 0, 720, 725, 730, 750, 0,
  278. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  279. /* 0x16 - 1280x768@60Hz RB */
  280. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
  281. 1360, 1440, 0, 768, 771, 778, 790, 0,
  282. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  283. /* 0x17 - 1280x768@60Hz */
  284. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  285. 1472, 1664, 0, 768, 771, 778, 798, 0,
  286. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  287. /* 0x18 - 1280x768@75Hz */
  288. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
  289. 1488, 1696, 0, 768, 771, 778, 805, 0,
  290. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  291. /* 0x19 - 1280x768@85Hz */
  292. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
  293. 1496, 1712, 0, 768, 771, 778, 809, 0,
  294. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  295. /* 0x1a - 1280x768@120Hz RB */
  296. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
  297. 1360, 1440, 0, 768, 771, 778, 813, 0,
  298. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  299. /* 0x1b - 1280x800@60Hz RB */
  300. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
  301. 1360, 1440, 0, 800, 803, 809, 823, 0,
  302. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  303. /* 0x1c - 1280x800@60Hz */
  304. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  305. 1480, 1680, 0, 800, 803, 809, 831, 0,
  306. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  307. /* 0x1d - 1280x800@75Hz */
  308. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
  309. 1488, 1696, 0, 800, 803, 809, 838, 0,
  310. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  311. /* 0x1e - 1280x800@85Hz */
  312. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
  313. 1496, 1712, 0, 800, 803, 809, 843, 0,
  314. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  315. /* 0x1f - 1280x800@120Hz RB */
  316. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
  317. 1360, 1440, 0, 800, 803, 809, 847, 0,
  318. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  319. /* 0x20 - 1280x960@60Hz */
  320. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  321. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  322. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  323. /* 0x21 - 1280x960@85Hz */
  324. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
  325. 1504, 1728, 0, 960, 961, 964, 1011, 0,
  326. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  327. /* 0x22 - 1280x960@120Hz RB */
  328. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
  329. 1360, 1440, 0, 960, 963, 967, 1017, 0,
  330. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  331. /* 0x23 - 1280x1024@60Hz */
  332. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  333. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  334. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  335. /* 0x24 - 1280x1024@75Hz */
  336. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
  337. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  338. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  339. /* 0x25 - 1280x1024@85Hz */
  340. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
  341. 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
  342. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  343. /* 0x26 - 1280x1024@120Hz RB */
  344. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
  345. 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
  346. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  347. /* 0x27 - 1360x768@60Hz */
  348. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  349. 1536, 1792, 0, 768, 771, 777, 795, 0,
  350. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  351. /* 0x28 - 1360x768@120Hz RB */
  352. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
  353. 1440, 1520, 0, 768, 771, 776, 813, 0,
  354. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  355. /* 0x51 - 1366x768@60Hz */
  356. { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
  357. 1579, 1792, 0, 768, 771, 774, 798, 0,
  358. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  359. /* 0x56 - 1366x768@60Hz */
  360. { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
  361. 1436, 1500, 0, 768, 769, 772, 800, 0,
  362. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  363. /* 0x29 - 1400x1050@60Hz RB */
  364. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
  365. 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
  366. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  367. /* 0x2a - 1400x1050@60Hz */
  368. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  369. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  370. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  371. /* 0x2b - 1400x1050@75Hz */
  372. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
  373. 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
  374. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  375. /* 0x2c - 1400x1050@85Hz */
  376. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
  377. 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
  378. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  379. /* 0x2d - 1400x1050@120Hz RB */
  380. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
  381. 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
  382. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  383. /* 0x2e - 1440x900@60Hz RB */
  384. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
  385. 1520, 1600, 0, 900, 903, 909, 926, 0,
  386. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  387. /* 0x2f - 1440x900@60Hz */
  388. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  389. 1672, 1904, 0, 900, 903, 909, 934, 0,
  390. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  391. /* 0x30 - 1440x900@75Hz */
  392. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
  393. 1688, 1936, 0, 900, 903, 909, 942, 0,
  394. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  395. /* 0x31 - 1440x900@85Hz */
  396. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
  397. 1696, 1952, 0, 900, 903, 909, 948, 0,
  398. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  399. /* 0x32 - 1440x900@120Hz RB */
  400. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
  401. 1520, 1600, 0, 900, 903, 909, 953, 0,
  402. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  403. /* 0x53 - 1600x900@60Hz */
  404. { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
  405. 1704, 1800, 0, 900, 901, 904, 1000, 0,
  406. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  407. /* 0x33 - 1600x1200@60Hz */
  408. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  409. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  410. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  411. /* 0x34 - 1600x1200@65Hz */
  412. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
  413. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  414. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  415. /* 0x35 - 1600x1200@70Hz */
  416. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
  417. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  418. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  419. /* 0x36 - 1600x1200@75Hz */
  420. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
  421. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  422. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  423. /* 0x37 - 1600x1200@85Hz */
  424. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
  425. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  426. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  427. /* 0x38 - 1600x1200@120Hz RB */
  428. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
  429. 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
  430. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  431. /* 0x39 - 1680x1050@60Hz RB */
  432. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
  433. 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
  434. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  435. /* 0x3a - 1680x1050@60Hz */
  436. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  437. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  438. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  439. /* 0x3b - 1680x1050@75Hz */
  440. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
  441. 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
  442. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  443. /* 0x3c - 1680x1050@85Hz */
  444. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
  445. 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
  446. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  447. /* 0x3d - 1680x1050@120Hz RB */
  448. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
  449. 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
  450. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  451. /* 0x3e - 1792x1344@60Hz */
  452. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  453. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  454. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  455. /* 0x3f - 1792x1344@75Hz */
  456. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
  457. 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
  458. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  459. /* 0x40 - 1792x1344@120Hz RB */
  460. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
  461. 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
  462. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  463. /* 0x41 - 1856x1392@60Hz */
  464. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  465. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  466. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  467. /* 0x42 - 1856x1392@75Hz */
  468. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
  469. 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
  470. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  471. /* 0x43 - 1856x1392@120Hz RB */
  472. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
  473. 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
  474. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  475. /* 0x52 - 1920x1080@60Hz */
  476. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
  477. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  478. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  479. /* 0x44 - 1920x1200@60Hz RB */
  480. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
  481. 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
  482. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  483. /* 0x45 - 1920x1200@60Hz */
  484. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  485. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  486. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  487. /* 0x46 - 1920x1200@75Hz */
  488. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
  489. 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
  490. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  491. /* 0x47 - 1920x1200@85Hz */
  492. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
  493. 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
  494. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  495. /* 0x48 - 1920x1200@120Hz RB */
  496. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
  497. 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
  498. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  499. /* 0x49 - 1920x1440@60Hz */
  500. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  501. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  502. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  503. /* 0x4a - 1920x1440@75Hz */
  504. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
  505. 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
  506. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  507. /* 0x4b - 1920x1440@120Hz RB */
  508. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
  509. 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
  510. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  511. /* 0x54 - 2048x1152@60Hz */
  512. { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
  513. 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
  514. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  515. /* 0x4c - 2560x1600@60Hz RB */
  516. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
  517. 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
  518. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  519. /* 0x4d - 2560x1600@60Hz */
  520. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  521. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  522. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  523. /* 0x4e - 2560x1600@75Hz */
  524. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
  525. 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
  526. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  527. /* 0x4f - 2560x1600@85Hz */
  528. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
  529. 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
  530. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  531. /* 0x50 - 2560x1600@120Hz RB */
  532. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
  533. 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
  534. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  535. /* 0x57 - 4096x2160@60Hz RB */
  536. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
  537. 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
  538. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  539. /* 0x58 - 4096x2160@59.94Hz RB */
  540. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
  541. 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
  542. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  543. };
  544. /*
  545. * These more or less come from the DMT spec. The 720x400 modes are
  546. * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
  547. * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
  548. * should be 1152x870, again for the Mac, but instead we use the x864 DMT
  549. * mode.
  550. *
  551. * The DMT modes have been fact-checked; the rest are mild guesses.
  552. */
  553. static const struct drm_display_mode edid_est_modes[] = {
  554. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  555. 968, 1056, 0, 600, 601, 605, 628, 0,
  556. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
  557. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
  558. 896, 1024, 0, 600, 601, 603, 625, 0,
  559. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
  560. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
  561. 720, 840, 0, 480, 481, 484, 500, 0,
  562. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
  563. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
  564. 704, 832, 0, 480, 489, 492, 520, 0,
  565. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
  566. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
  567. 768, 864, 0, 480, 483, 486, 525, 0,
  568. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
  569. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  570. 752, 800, 0, 480, 490, 492, 525, 0,
  571. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
  572. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
  573. 846, 900, 0, 400, 421, 423, 449, 0,
  574. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
  575. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
  576. 846, 900, 0, 400, 412, 414, 449, 0,
  577. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
  578. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
  579. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  580. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
  581. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
  582. 1136, 1312, 0, 768, 769, 772, 800, 0,
  583. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
  584. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
  585. 1184, 1328, 0, 768, 771, 777, 806, 0,
  586. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
  587. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  588. 1184, 1344, 0, 768, 771, 777, 806, 0,
  589. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
  590. { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
  591. 1208, 1264, 0, 768, 768, 776, 817, 0,
  592. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
  593. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
  594. 928, 1152, 0, 624, 625, 628, 667, 0,
  595. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
  596. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
  597. 896, 1056, 0, 600, 601, 604, 625, 0,
  598. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
  599. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
  600. 976, 1040, 0, 600, 637, 643, 666, 0,
  601. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
  602. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  603. 1344, 1600, 0, 864, 865, 868, 900, 0,
  604. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
  605. };
  606. struct minimode {
  607. short w;
  608. short h;
  609. short r;
  610. short rb;
  611. };
  612. static const struct minimode est3_modes[] = {
  613. /* byte 6 */
  614. { 640, 350, 85, 0 },
  615. { 640, 400, 85, 0 },
  616. { 720, 400, 85, 0 },
  617. { 640, 480, 85, 0 },
  618. { 848, 480, 60, 0 },
  619. { 800, 600, 85, 0 },
  620. { 1024, 768, 85, 0 },
  621. { 1152, 864, 75, 0 },
  622. /* byte 7 */
  623. { 1280, 768, 60, 1 },
  624. { 1280, 768, 60, 0 },
  625. { 1280, 768, 75, 0 },
  626. { 1280, 768, 85, 0 },
  627. { 1280, 960, 60, 0 },
  628. { 1280, 960, 85, 0 },
  629. { 1280, 1024, 60, 0 },
  630. { 1280, 1024, 85, 0 },
  631. /* byte 8 */
  632. { 1360, 768, 60, 0 },
  633. { 1440, 900, 60, 1 },
  634. { 1440, 900, 60, 0 },
  635. { 1440, 900, 75, 0 },
  636. { 1440, 900, 85, 0 },
  637. { 1400, 1050, 60, 1 },
  638. { 1400, 1050, 60, 0 },
  639. { 1400, 1050, 75, 0 },
  640. /* byte 9 */
  641. { 1400, 1050, 85, 0 },
  642. { 1680, 1050, 60, 1 },
  643. { 1680, 1050, 60, 0 },
  644. { 1680, 1050, 75, 0 },
  645. { 1680, 1050, 85, 0 },
  646. { 1600, 1200, 60, 0 },
  647. { 1600, 1200, 65, 0 },
  648. { 1600, 1200, 70, 0 },
  649. /* byte 10 */
  650. { 1600, 1200, 75, 0 },
  651. { 1600, 1200, 85, 0 },
  652. { 1792, 1344, 60, 0 },
  653. { 1792, 1344, 75, 0 },
  654. { 1856, 1392, 60, 0 },
  655. { 1856, 1392, 75, 0 },
  656. { 1920, 1200, 60, 1 },
  657. { 1920, 1200, 60, 0 },
  658. /* byte 11 */
  659. { 1920, 1200, 75, 0 },
  660. { 1920, 1200, 85, 0 },
  661. { 1920, 1440, 60, 0 },
  662. { 1920, 1440, 75, 0 },
  663. };
  664. static const struct minimode extra_modes[] = {
  665. { 1024, 576, 60, 0 },
  666. { 1366, 768, 60, 0 },
  667. { 1600, 900, 60, 0 },
  668. { 1680, 945, 60, 0 },
  669. { 1920, 1080, 60, 0 },
  670. { 2048, 1152, 60, 0 },
  671. { 2048, 1536, 60, 0 },
  672. };
  673. /*
  674. * From CEA/CTA-861 spec.
  675. *
  676. * Do not access directly, instead always use cea_mode_for_vic().
  677. */
  678. static const struct drm_display_mode edid_cea_modes_1[] = {
  679. /* 1 - 640x480@60Hz 4:3 */
  680. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  681. 752, 800, 0, 480, 490, 492, 525, 0,
  682. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  683. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  684. /* 2 - 720x480@60Hz 4:3 */
  685. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
  686. 798, 858, 0, 480, 489, 495, 525, 0,
  687. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  688. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  689. /* 3 - 720x480@60Hz 16:9 */
  690. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
  691. 798, 858, 0, 480, 489, 495, 525, 0,
  692. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  693. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  694. /* 4 - 1280x720@60Hz 16:9 */
  695. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
  696. 1430, 1650, 0, 720, 725, 730, 750, 0,
  697. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  698. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  699. /* 5 - 1920x1080i@60Hz 16:9 */
  700. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
  701. 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
  702. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  703. DRM_MODE_FLAG_INTERLACE),
  704. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  705. /* 6 - 720(1440)x480i@60Hz 4:3 */
  706. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
  707. 801, 858, 0, 480, 488, 494, 525, 0,
  708. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  709. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  710. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  711. /* 7 - 720(1440)x480i@60Hz 16:9 */
  712. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
  713. 801, 858, 0, 480, 488, 494, 525, 0,
  714. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  715. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  716. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  717. /* 8 - 720(1440)x240@60Hz 4:3 */
  718. { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
  719. 801, 858, 0, 240, 244, 247, 262, 0,
  720. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  721. DRM_MODE_FLAG_DBLCLK),
  722. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  723. /* 9 - 720(1440)x240@60Hz 16:9 */
  724. { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
  725. 801, 858, 0, 240, 244, 247, 262, 0,
  726. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  727. DRM_MODE_FLAG_DBLCLK),
  728. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  729. /* 10 - 2880x480i@60Hz 4:3 */
  730. { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
  731. 3204, 3432, 0, 480, 488, 494, 525, 0,
  732. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  733. DRM_MODE_FLAG_INTERLACE),
  734. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  735. /* 11 - 2880x480i@60Hz 16:9 */
  736. { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
  737. 3204, 3432, 0, 480, 488, 494, 525, 0,
  738. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  739. DRM_MODE_FLAG_INTERLACE),
  740. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  741. /* 12 - 2880x240@60Hz 4:3 */
  742. { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
  743. 3204, 3432, 0, 240, 244, 247, 262, 0,
  744. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  745. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  746. /* 13 - 2880x240@60Hz 16:9 */
  747. { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
  748. 3204, 3432, 0, 240, 244, 247, 262, 0,
  749. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  750. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  751. /* 14 - 1440x480@60Hz 4:3 */
  752. { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
  753. 1596, 1716, 0, 480, 489, 495, 525, 0,
  754. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  755. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  756. /* 15 - 1440x480@60Hz 16:9 */
  757. { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
  758. 1596, 1716, 0, 480, 489, 495, 525, 0,
  759. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  760. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  761. /* 16 - 1920x1080@60Hz 16:9 */
  762. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
  763. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  764. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  765. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  766. /* 17 - 720x576@50Hz 4:3 */
  767. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
  768. 796, 864, 0, 576, 581, 586, 625, 0,
  769. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  770. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  771. /* 18 - 720x576@50Hz 16:9 */
  772. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
  773. 796, 864, 0, 576, 581, 586, 625, 0,
  774. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  775. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  776. /* 19 - 1280x720@50Hz 16:9 */
  777. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
  778. 1760, 1980, 0, 720, 725, 730, 750, 0,
  779. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  780. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  781. /* 20 - 1920x1080i@50Hz 16:9 */
  782. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
  783. 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
  784. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  785. DRM_MODE_FLAG_INTERLACE),
  786. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  787. /* 21 - 720(1440)x576i@50Hz 4:3 */
  788. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
  789. 795, 864, 0, 576, 580, 586, 625, 0,
  790. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  791. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  792. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  793. /* 22 - 720(1440)x576i@50Hz 16:9 */
  794. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
  795. 795, 864, 0, 576, 580, 586, 625, 0,
  796. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  797. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  798. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  799. /* 23 - 720(1440)x288@50Hz 4:3 */
  800. { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
  801. 795, 864, 0, 288, 290, 293, 312, 0,
  802. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  803. DRM_MODE_FLAG_DBLCLK),
  804. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  805. /* 24 - 720(1440)x288@50Hz 16:9 */
  806. { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
  807. 795, 864, 0, 288, 290, 293, 312, 0,
  808. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  809. DRM_MODE_FLAG_DBLCLK),
  810. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  811. /* 25 - 2880x576i@50Hz 4:3 */
  812. { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
  813. 3180, 3456, 0, 576, 580, 586, 625, 0,
  814. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  815. DRM_MODE_FLAG_INTERLACE),
  816. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  817. /* 26 - 2880x576i@50Hz 16:9 */
  818. { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
  819. 3180, 3456, 0, 576, 580, 586, 625, 0,
  820. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  821. DRM_MODE_FLAG_INTERLACE),
  822. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  823. /* 27 - 2880x288@50Hz 4:3 */
  824. { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
  825. 3180, 3456, 0, 288, 290, 293, 312, 0,
  826. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  827. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  828. /* 28 - 2880x288@50Hz 16:9 */
  829. { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
  830. 3180, 3456, 0, 288, 290, 293, 312, 0,
  831. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  832. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  833. /* 29 - 1440x576@50Hz 4:3 */
  834. { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
  835. 1592, 1728, 0, 576, 581, 586, 625, 0,
  836. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  837. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  838. /* 30 - 1440x576@50Hz 16:9 */
  839. { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
  840. 1592, 1728, 0, 576, 581, 586, 625, 0,
  841. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  842. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  843. /* 31 - 1920x1080@50Hz 16:9 */
  844. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
  845. 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
  846. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  847. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  848. /* 32 - 1920x1080@24Hz 16:9 */
  849. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
  850. 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
  851. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  852. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  853. /* 33 - 1920x1080@25Hz 16:9 */
  854. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
  855. 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
  856. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  857. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  858. /* 34 - 1920x1080@30Hz 16:9 */
  859. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
  860. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  861. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  862. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  863. /* 35 - 2880x480@60Hz 4:3 */
  864. { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
  865. 3192, 3432, 0, 480, 489, 495, 525, 0,
  866. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  867. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  868. /* 36 - 2880x480@60Hz 16:9 */
  869. { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
  870. 3192, 3432, 0, 480, 489, 495, 525, 0,
  871. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  872. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  873. /* 37 - 2880x576@50Hz 4:3 */
  874. { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
  875. 3184, 3456, 0, 576, 581, 586, 625, 0,
  876. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  877. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  878. /* 38 - 2880x576@50Hz 16:9 */
  879. { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
  880. 3184, 3456, 0, 576, 581, 586, 625, 0,
  881. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  882. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  883. /* 39 - 1920x1080i@50Hz 16:9 */
  884. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
  885. 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
  886. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
  887. DRM_MODE_FLAG_INTERLACE),
  888. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  889. /* 40 - 1920x1080i@100Hz 16:9 */
  890. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
  891. 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
  892. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  893. DRM_MODE_FLAG_INTERLACE),
  894. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  895. /* 41 - 1280x720@100Hz 16:9 */
  896. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
  897. 1760, 1980, 0, 720, 725, 730, 750, 0,
  898. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  899. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  900. /* 42 - 720x576@100Hz 4:3 */
  901. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
  902. 796, 864, 0, 576, 581, 586, 625, 0,
  903. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  904. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  905. /* 43 - 720x576@100Hz 16:9 */
  906. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
  907. 796, 864, 0, 576, 581, 586, 625, 0,
  908. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  909. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  910. /* 44 - 720(1440)x576i@100Hz 4:3 */
  911. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
  912. 795, 864, 0, 576, 580, 586, 625, 0,
  913. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  914. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  915. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  916. /* 45 - 720(1440)x576i@100Hz 16:9 */
  917. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
  918. 795, 864, 0, 576, 580, 586, 625, 0,
  919. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  920. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  921. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  922. /* 46 - 1920x1080i@120Hz 16:9 */
  923. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
  924. 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
  925. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  926. DRM_MODE_FLAG_INTERLACE),
  927. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  928. /* 47 - 1280x720@120Hz 16:9 */
  929. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
  930. 1430, 1650, 0, 720, 725, 730, 750, 0,
  931. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  932. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  933. /* 48 - 720x480@120Hz 4:3 */
  934. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
  935. 798, 858, 0, 480, 489, 495, 525, 0,
  936. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  937. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  938. /* 49 - 720x480@120Hz 16:9 */
  939. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
  940. 798, 858, 0, 480, 489, 495, 525, 0,
  941. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  942. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  943. /* 50 - 720(1440)x480i@120Hz 4:3 */
  944. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
  945. 801, 858, 0, 480, 488, 494, 525, 0,
  946. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  947. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  948. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  949. /* 51 - 720(1440)x480i@120Hz 16:9 */
  950. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
  951. 801, 858, 0, 480, 488, 494, 525, 0,
  952. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  953. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  954. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  955. /* 52 - 720x576@200Hz 4:3 */
  956. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
  957. 796, 864, 0, 576, 581, 586, 625, 0,
  958. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  959. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  960. /* 53 - 720x576@200Hz 16:9 */
  961. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
  962. 796, 864, 0, 576, 581, 586, 625, 0,
  963. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  964. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  965. /* 54 - 720(1440)x576i@200Hz 4:3 */
  966. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
  967. 795, 864, 0, 576, 580, 586, 625, 0,
  968. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  969. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  970. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  971. /* 55 - 720(1440)x576i@200Hz 16:9 */
  972. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
  973. 795, 864, 0, 576, 580, 586, 625, 0,
  974. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  975. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  976. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  977. /* 56 - 720x480@240Hz 4:3 */
  978. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
  979. 798, 858, 0, 480, 489, 495, 525, 0,
  980. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  981. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  982. /* 57 - 720x480@240Hz 16:9 */
  983. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
  984. 798, 858, 0, 480, 489, 495, 525, 0,
  985. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  986. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  987. /* 58 - 720(1440)x480i@240Hz 4:3 */
  988. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
  989. 801, 858, 0, 480, 488, 494, 525, 0,
  990. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  991. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  992. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  993. /* 59 - 720(1440)x480i@240Hz 16:9 */
  994. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
  995. 801, 858, 0, 480, 488, 494, 525, 0,
  996. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  997. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  998. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  999. /* 60 - 1280x720@24Hz 16:9 */
  1000. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
  1001. 3080, 3300, 0, 720, 725, 730, 750, 0,
  1002. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1003. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1004. /* 61 - 1280x720@25Hz 16:9 */
  1005. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
  1006. 3740, 3960, 0, 720, 725, 730, 750, 0,
  1007. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1008. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1009. /* 62 - 1280x720@30Hz 16:9 */
  1010. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
  1011. 3080, 3300, 0, 720, 725, 730, 750, 0,
  1012. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1013. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1014. /* 63 - 1920x1080@120Hz 16:9 */
  1015. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
  1016. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  1017. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1018. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1019. /* 64 - 1920x1080@100Hz 16:9 */
  1020. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
  1021. 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
  1022. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1023. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1024. /* 65 - 1280x720@24Hz 64:27 */
  1025. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
  1026. 3080, 3300, 0, 720, 725, 730, 750, 0,
  1027. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1028. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1029. /* 66 - 1280x720@25Hz 64:27 */
  1030. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
  1031. 3740, 3960, 0, 720, 725, 730, 750, 0,
  1032. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1033. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1034. /* 67 - 1280x720@30Hz 64:27 */
  1035. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
  1036. 3080, 3300, 0, 720, 725, 730, 750, 0,
  1037. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1038. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1039. /* 68 - 1280x720@50Hz 64:27 */
  1040. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
  1041. 1760, 1980, 0, 720, 725, 730, 750, 0,
  1042. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1043. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1044. /* 69 - 1280x720@60Hz 64:27 */
  1045. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
  1046. 1430, 1650, 0, 720, 725, 730, 750, 0,
  1047. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1048. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1049. /* 70 - 1280x720@100Hz 64:27 */
  1050. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
  1051. 1760, 1980, 0, 720, 725, 730, 750, 0,
  1052. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1053. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1054. /* 71 - 1280x720@120Hz 64:27 */
  1055. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
  1056. 1430, 1650, 0, 720, 725, 730, 750, 0,
  1057. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1058. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1059. /* 72 - 1920x1080@24Hz 64:27 */
  1060. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
  1061. 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
  1062. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1063. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1064. /* 73 - 1920x1080@25Hz 64:27 */
  1065. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
  1066. 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
  1067. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1068. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1069. /* 74 - 1920x1080@30Hz 64:27 */
  1070. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
  1071. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  1072. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1073. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1074. /* 75 - 1920x1080@50Hz 64:27 */
  1075. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
  1076. 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
  1077. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1078. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1079. /* 76 - 1920x1080@60Hz 64:27 */
  1080. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
  1081. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  1082. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1083. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1084. /* 77 - 1920x1080@100Hz 64:27 */
  1085. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
  1086. 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
  1087. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1088. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1089. /* 78 - 1920x1080@120Hz 64:27 */
  1090. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
  1091. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  1092. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1093. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1094. /* 79 - 1680x720@24Hz 64:27 */
  1095. { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
  1096. 3080, 3300, 0, 720, 725, 730, 750, 0,
  1097. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1098. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1099. /* 80 - 1680x720@25Hz 64:27 */
  1100. { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
  1101. 2948, 3168, 0, 720, 725, 730, 750, 0,
  1102. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1103. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1104. /* 81 - 1680x720@30Hz 64:27 */
  1105. { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
  1106. 2420, 2640, 0, 720, 725, 730, 750, 0,
  1107. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1108. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1109. /* 82 - 1680x720@50Hz 64:27 */
  1110. { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
  1111. 1980, 2200, 0, 720, 725, 730, 750, 0,
  1112. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1113. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1114. /* 83 - 1680x720@60Hz 64:27 */
  1115. { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
  1116. 1980, 2200, 0, 720, 725, 730, 750, 0,
  1117. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1118. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1119. /* 84 - 1680x720@100Hz 64:27 */
  1120. { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
  1121. 1780, 2000, 0, 720, 725, 730, 825, 0,
  1122. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1123. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1124. /* 85 - 1680x720@120Hz 64:27 */
  1125. { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
  1126. 1780, 2000, 0, 720, 725, 730, 825, 0,
  1127. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1128. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1129. /* 86 - 2560x1080@24Hz 64:27 */
  1130. { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
  1131. 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
  1132. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1133. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1134. /* 87 - 2560x1080@25Hz 64:27 */
  1135. { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
  1136. 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
  1137. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1138. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1139. /* 88 - 2560x1080@30Hz 64:27 */
  1140. { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
  1141. 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
  1142. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1143. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1144. /* 89 - 2560x1080@50Hz 64:27 */
  1145. { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
  1146. 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
  1147. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1148. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1149. /* 90 - 2560x1080@60Hz 64:27 */
  1150. { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
  1151. 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
  1152. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1153. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1154. /* 91 - 2560x1080@100Hz 64:27 */
  1155. { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
  1156. 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
  1157. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1158. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1159. /* 92 - 2560x1080@120Hz 64:27 */
  1160. { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
  1161. 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
  1162. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1163. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1164. /* 93 - 3840x2160@24Hz 16:9 */
  1165. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
  1166. 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
  1167. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1168. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1169. /* 94 - 3840x2160@25Hz 16:9 */
  1170. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
  1171. 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
  1172. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1173. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1174. /* 95 - 3840x2160@30Hz 16:9 */
  1175. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
  1176. 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
  1177. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1178. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1179. /* 96 - 3840x2160@50Hz 16:9 */
  1180. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
  1181. 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
  1182. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1183. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1184. /* 97 - 3840x2160@60Hz 16:9 */
  1185. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
  1186. 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
  1187. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1188. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1189. /* 98 - 4096x2160@24Hz 256:135 */
  1190. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
  1191. 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
  1192. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1193. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
  1194. /* 99 - 4096x2160@25Hz 256:135 */
  1195. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
  1196. 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
  1197. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1198. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
  1199. /* 100 - 4096x2160@30Hz 256:135 */
  1200. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
  1201. 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
  1202. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1203. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
  1204. /* 101 - 4096x2160@50Hz 256:135 */
  1205. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
  1206. 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
  1207. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1208. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
  1209. /* 102 - 4096x2160@60Hz 256:135 */
  1210. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
  1211. 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
  1212. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1213. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
  1214. /* 103 - 3840x2160@24Hz 64:27 */
  1215. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
  1216. 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
  1217. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1218. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1219. /* 104 - 3840x2160@25Hz 64:27 */
  1220. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
  1221. 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
  1222. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1223. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1224. /* 105 - 3840x2160@30Hz 64:27 */
  1225. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
  1226. 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
  1227. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1228. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1229. /* 106 - 3840x2160@50Hz 64:27 */
  1230. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
  1231. 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
  1232. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1233. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1234. /* 107 - 3840x2160@60Hz 64:27 */
  1235. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
  1236. 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
  1237. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1238. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1239. /* 108 - 1280x720@48Hz 16:9 */
  1240. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
  1241. 2280, 2500, 0, 720, 725, 730, 750, 0,
  1242. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1243. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1244. /* 109 - 1280x720@48Hz 64:27 */
  1245. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
  1246. 2280, 2500, 0, 720, 725, 730, 750, 0,
  1247. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1248. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1249. /* 110 - 1680x720@48Hz 64:27 */
  1250. { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
  1251. 2530, 2750, 0, 720, 725, 730, 750, 0,
  1252. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1253. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1254. /* 111 - 1920x1080@48Hz 16:9 */
  1255. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
  1256. 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
  1257. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1258. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1259. /* 112 - 1920x1080@48Hz 64:27 */
  1260. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
  1261. 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
  1262. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1263. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1264. /* 113 - 2560x1080@48Hz 64:27 */
  1265. { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
  1266. 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
  1267. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1268. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1269. /* 114 - 3840x2160@48Hz 16:9 */
  1270. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
  1271. 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
  1272. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1273. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1274. /* 115 - 4096x2160@48Hz 256:135 */
  1275. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
  1276. 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
  1277. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1278. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
  1279. /* 116 - 3840x2160@48Hz 64:27 */
  1280. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
  1281. 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
  1282. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1283. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1284. /* 117 - 3840x2160@100Hz 16:9 */
  1285. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
  1286. 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
  1287. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1288. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1289. /* 118 - 3840x2160@120Hz 16:9 */
  1290. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
  1291. 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
  1292. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1293. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1294. /* 119 - 3840x2160@100Hz 64:27 */
  1295. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
  1296. 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
  1297. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1298. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1299. /* 120 - 3840x2160@120Hz 64:27 */
  1300. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
  1301. 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
  1302. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1303. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1304. /* 121 - 5120x2160@24Hz 64:27 */
  1305. { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
  1306. 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
  1307. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1308. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1309. /* 122 - 5120x2160@25Hz 64:27 */
  1310. { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
  1311. 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
  1312. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1313. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1314. /* 123 - 5120x2160@30Hz 64:27 */
  1315. { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
  1316. 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
  1317. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1318. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1319. /* 124 - 5120x2160@48Hz 64:27 */
  1320. { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
  1321. 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
  1322. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1323. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1324. /* 125 - 5120x2160@50Hz 64:27 */
  1325. { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
  1326. 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
  1327. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1328. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1329. /* 126 - 5120x2160@60Hz 64:27 */
  1330. { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
  1331. 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
  1332. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1333. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1334. /* 127 - 5120x2160@100Hz 64:27 */
  1335. { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
  1336. 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
  1337. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1338. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1339. };
  1340. /*
  1341. * From CEA/CTA-861 spec.
  1342. *
  1343. * Do not access directly, instead always use cea_mode_for_vic().
  1344. */
  1345. static const struct drm_display_mode edid_cea_modes_193[] = {
  1346. /* 193 - 5120x2160@120Hz 64:27 */
  1347. { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
  1348. 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
  1349. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1350. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1351. /* 194 - 7680x4320@24Hz 16:9 */
  1352. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
  1353. 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
  1354. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1355. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1356. /* 195 - 7680x4320@25Hz 16:9 */
  1357. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
  1358. 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
  1359. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1360. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1361. /* 196 - 7680x4320@30Hz 16:9 */
  1362. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
  1363. 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
  1364. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1365. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1366. /* 197 - 7680x4320@48Hz 16:9 */
  1367. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
  1368. 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
  1369. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1370. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1371. /* 198 - 7680x4320@50Hz 16:9 */
  1372. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
  1373. 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
  1374. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1375. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1376. /* 199 - 7680x4320@60Hz 16:9 */
  1377. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
  1378. 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
  1379. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1380. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1381. /* 200 - 7680x4320@100Hz 16:9 */
  1382. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
  1383. 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
  1384. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1385. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1386. /* 201 - 7680x4320@120Hz 16:9 */
  1387. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
  1388. 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
  1389. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1390. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1391. /* 202 - 7680x4320@24Hz 64:27 */
  1392. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
  1393. 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
  1394. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1395. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1396. /* 203 - 7680x4320@25Hz 64:27 */
  1397. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
  1398. 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
  1399. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1400. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1401. /* 204 - 7680x4320@30Hz 64:27 */
  1402. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
  1403. 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
  1404. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1405. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1406. /* 205 - 7680x4320@48Hz 64:27 */
  1407. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
  1408. 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
  1409. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1410. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1411. /* 206 - 7680x4320@50Hz 64:27 */
  1412. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
  1413. 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
  1414. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1415. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1416. /* 207 - 7680x4320@60Hz 64:27 */
  1417. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
  1418. 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
  1419. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1420. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1421. /* 208 - 7680x4320@100Hz 64:27 */
  1422. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
  1423. 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
  1424. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1425. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1426. /* 209 - 7680x4320@120Hz 64:27 */
  1427. { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
  1428. 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
  1429. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1430. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1431. /* 210 - 10240x4320@24Hz 64:27 */
  1432. { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
  1433. 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
  1434. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1435. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1436. /* 211 - 10240x4320@25Hz 64:27 */
  1437. { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
  1438. 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
  1439. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1440. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1441. /* 212 - 10240x4320@30Hz 64:27 */
  1442. { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
  1443. 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
  1444. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1445. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1446. /* 213 - 10240x4320@48Hz 64:27 */
  1447. { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
  1448. 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
  1449. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1450. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1451. /* 214 - 10240x4320@50Hz 64:27 */
  1452. { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
  1453. 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
  1454. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1455. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1456. /* 215 - 10240x4320@60Hz 64:27 */
  1457. { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
  1458. 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
  1459. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1460. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1461. /* 216 - 10240x4320@100Hz 64:27 */
  1462. { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
  1463. 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
  1464. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1465. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1466. /* 217 - 10240x4320@120Hz 64:27 */
  1467. { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
  1468. 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
  1469. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1470. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
  1471. /* 218 - 4096x2160@100Hz 256:135 */
  1472. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
  1473. 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
  1474. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1475. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
  1476. /* 219 - 4096x2160@120Hz 256:135 */
  1477. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
  1478. 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
  1479. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1480. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
  1481. };
  1482. /*
  1483. * HDMI 1.4 4k modes. Index using the VIC.
  1484. */
  1485. static const struct drm_display_mode edid_4k_modes[] = {
  1486. /* 0 - dummy, VICs start at 1 */
  1487. { },
  1488. /* 1 - 3840x2160@30Hz */
  1489. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
  1490. 3840, 4016, 4104, 4400, 0,
  1491. 2160, 2168, 2178, 2250, 0,
  1492. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1493. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1494. /* 2 - 3840x2160@25Hz */
  1495. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
  1496. 3840, 4896, 4984, 5280, 0,
  1497. 2160, 2168, 2178, 2250, 0,
  1498. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1499. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1500. /* 3 - 3840x2160@24Hz */
  1501. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
  1502. 3840, 5116, 5204, 5500, 0,
  1503. 2160, 2168, 2178, 2250, 0,
  1504. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1505. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  1506. /* 4 - 4096x2160@24Hz (SMPTE) */
  1507. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
  1508. 4096, 5116, 5204, 5500, 0,
  1509. 2160, 2168, 2178, 2250, 0,
  1510. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1511. .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
  1512. };
  1513. /*** DDC fetch and block validation ***/
  1514. static const u8 edid_header[] = {
  1515. 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
  1516. };
  1517. /**
  1518. * drm_edid_header_is_valid - sanity check the header of the base EDID block
  1519. * @raw_edid: pointer to raw base EDID block
  1520. *
  1521. * Sanity check the header of the base EDID block.
  1522. *
  1523. * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
  1524. */
  1525. int drm_edid_header_is_valid(const u8 *raw_edid)
  1526. {
  1527. int i, score = 0;
  1528. for (i = 0; i < sizeof(edid_header); i++)
  1529. if (raw_edid[i] == edid_header[i])
  1530. score++;
  1531. return score;
  1532. }
  1533. EXPORT_SYMBOL(drm_edid_header_is_valid);
  1534. static int edid_fixup __read_mostly = 6;
  1535. module_param_named(edid_fixup, edid_fixup, int, 0400);
  1536. MODULE_PARM_DESC(edid_fixup,
  1537. "Minimum number of valid EDID header bytes (0-8, default 6)");
  1538. static int validate_displayid(u8 *displayid, int length, int idx);
  1539. static int drm_edid_block_checksum(const u8 *raw_edid)
  1540. {
  1541. int i;
  1542. u8 csum = 0, crc = 0;
  1543. for (i = 0; i < EDID_LENGTH - 1; i++)
  1544. csum += raw_edid[i];
  1545. crc = 0x100 - csum;
  1546. return crc;
  1547. }
  1548. static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
  1549. {
  1550. if (raw_edid[EDID_LENGTH - 1] != real_checksum)
  1551. return true;
  1552. else
  1553. return false;
  1554. }
  1555. static bool drm_edid_is_zero(const u8 *in_edid, int length)
  1556. {
  1557. if (memchr_inv(in_edid, 0, length))
  1558. return false;
  1559. return true;
  1560. }
  1561. /**
  1562. * drm_edid_are_equal - compare two edid blobs.
  1563. * @edid1: pointer to first blob
  1564. * @edid2: pointer to second blob
  1565. * This helper can be used during probing to determine if
  1566. * edid had changed.
  1567. */
  1568. bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
  1569. {
  1570. int edid1_len, edid2_len;
  1571. bool edid1_present = edid1 != NULL;
  1572. bool edid2_present = edid2 != NULL;
  1573. if (edid1_present != edid2_present)
  1574. return false;
  1575. if (edid1) {
  1576. edid1_len = EDID_LENGTH * (1 + edid1->extensions);
  1577. edid2_len = EDID_LENGTH * (1 + edid2->extensions);
  1578. if (edid1_len != edid2_len)
  1579. return false;
  1580. if (memcmp(edid1, edid2, edid1_len))
  1581. return false;
  1582. }
  1583. return true;
  1584. }
  1585. EXPORT_SYMBOL(drm_edid_are_equal);
  1586. /**
  1587. * drm_edid_block_valid - Sanity check the EDID block (base or extension)
  1588. * @raw_edid: pointer to raw EDID block
  1589. * @block: type of block to validate (0 for base, extension otherwise)
  1590. * @print_bad_edid: if true, dump bad EDID blocks to the console
  1591. * @edid_corrupt: if true, the header or checksum is invalid
  1592. *
  1593. * Validate a base or extension EDID block and optionally dump bad blocks to
  1594. * the console.
  1595. *
  1596. * Return: True if the block is valid, false otherwise.
  1597. */
  1598. bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
  1599. bool *edid_corrupt)
  1600. {
  1601. u8 csum;
  1602. struct edid *edid = (struct edid *)raw_edid;
  1603. if (WARN_ON(!raw_edid))
  1604. return false;
  1605. if (edid_fixup > 8 || edid_fixup < 0)
  1606. edid_fixup = 6;
  1607. if (block == 0) {
  1608. int score = drm_edid_header_is_valid(raw_edid);
  1609. if (score == 8) {
  1610. if (edid_corrupt)
  1611. *edid_corrupt = false;
  1612. } else if (score >= edid_fixup) {
  1613. /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
  1614. * The corrupt flag needs to be set here otherwise, the
  1615. * fix-up code here will correct the problem, the
  1616. * checksum is correct and the test fails
  1617. */
  1618. if (edid_corrupt)
  1619. *edid_corrupt = true;
  1620. DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
  1621. memcpy(raw_edid, edid_header, sizeof(edid_header));
  1622. } else {
  1623. if (edid_corrupt)
  1624. *edid_corrupt = true;
  1625. goto bad;
  1626. }
  1627. }
  1628. csum = drm_edid_block_checksum(raw_edid);
  1629. if (drm_edid_block_checksum_diff(raw_edid, csum)) {
  1630. if (edid_corrupt)
  1631. *edid_corrupt = true;
  1632. /* allow CEA to slide through, switches mangle this */
  1633. if (raw_edid[0] == CEA_EXT) {
  1634. DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
  1635. DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
  1636. } else {
  1637. if (print_bad_edid)
  1638. DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
  1639. goto bad;
  1640. }
  1641. }
  1642. /* per-block-type checks */
  1643. switch (raw_edid[0]) {
  1644. case 0: /* base */
  1645. if (edid->version != 1) {
  1646. DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
  1647. goto bad;
  1648. }
  1649. if (edid->revision > 4)
  1650. DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
  1651. break;
  1652. default:
  1653. break;
  1654. }
  1655. return true;
  1656. bad:
  1657. if (print_bad_edid) {
  1658. if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
  1659. pr_notice("EDID block is all zeroes\n");
  1660. } else {
  1661. pr_notice("Raw EDID:\n");
  1662. print_hex_dump(KERN_NOTICE,
  1663. " \t", DUMP_PREFIX_NONE, 16, 1,
  1664. raw_edid, EDID_LENGTH, false);
  1665. }
  1666. }
  1667. return false;
  1668. }
  1669. EXPORT_SYMBOL(drm_edid_block_valid);
  1670. /**
  1671. * drm_edid_is_valid - sanity check EDID data
  1672. * @edid: EDID data
  1673. *
  1674. * Sanity-check an entire EDID record (including extensions)
  1675. *
  1676. * Return: True if the EDID data is valid, false otherwise.
  1677. */
  1678. bool drm_edid_is_valid(struct edid *edid)
  1679. {
  1680. int i;
  1681. u8 *raw = (u8 *)edid;
  1682. if (!edid)
  1683. return false;
  1684. for (i = 0; i <= edid->extensions; i++)
  1685. if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
  1686. return false;
  1687. return true;
  1688. }
  1689. EXPORT_SYMBOL(drm_edid_is_valid);
  1690. #define DDC_SEGMENT_ADDR 0x30
  1691. /**
  1692. * drm_do_probe_ddc_edid() - get EDID information via I2C
  1693. * @data: I2C device adapter
  1694. * @buf: EDID data buffer to be filled
  1695. * @block: 128 byte EDID block to start fetching from
  1696. * @len: EDID data buffer length to fetch
  1697. *
  1698. * Try to fetch EDID information by calling I2C driver functions.
  1699. *
  1700. * Return: 0 on success or -1 on failure.
  1701. */
  1702. static int
  1703. drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
  1704. {
  1705. struct i2c_adapter *adapter = data;
  1706. unsigned char start = block * EDID_LENGTH;
  1707. unsigned char segment = block >> 1;
  1708. unsigned char xfers = segment ? 3 : 2;
  1709. int ret, retries = 5;
  1710. /*
  1711. * The core I2C driver will automatically retry the transfer if the
  1712. * adapter reports EAGAIN. However, we find that bit-banging transfers
  1713. * are susceptible to errors under a heavily loaded machine and
  1714. * generate spurious NAKs and timeouts. Retrying the transfer
  1715. * of the individual block a few times seems to overcome this.
  1716. */
  1717. do {
  1718. struct i2c_msg msgs[] = {
  1719. {
  1720. .addr = DDC_SEGMENT_ADDR,
  1721. .flags = 0,
  1722. .len = 1,
  1723. .buf = &segment,
  1724. }, {
  1725. .addr = DDC_ADDR,
  1726. .flags = 0,
  1727. .len = 1,
  1728. .buf = &start,
  1729. }, {
  1730. .addr = DDC_ADDR,
  1731. .flags = I2C_M_RD,
  1732. .len = len,
  1733. .buf = buf,
  1734. }
  1735. };
  1736. /*
  1737. * Avoid sending the segment addr to not upset non-compliant
  1738. * DDC monitors.
  1739. */
  1740. ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
  1741. if (ret == -ENXIO) {
  1742. DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
  1743. adapter->name);
  1744. break;
  1745. }
  1746. } while (ret != xfers && --retries);
  1747. return ret == xfers ? 0 : -1;
  1748. }
  1749. static void connector_bad_edid(struct drm_connector *connector,
  1750. u8 *edid, int num_blocks)
  1751. {
  1752. int i;
  1753. u8 last_block;
  1754. /*
  1755. * 0x7e in the EDID is the number of extension blocks. The EDID
  1756. * is 1 (base block) + num_ext_blocks big. That means we can think
  1757. * of 0x7e in the EDID of the _index_ of the last block in the
  1758. * combined chunk of memory.
  1759. */
  1760. last_block = edid[0x7e];
  1761. /* Calculate real checksum for the last edid extension block data */
  1762. if (last_block < num_blocks)
  1763. connector->real_edid_checksum =
  1764. drm_edid_block_checksum(edid + last_block * EDID_LENGTH);
  1765. if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
  1766. return;
  1767. drm_warn(connector->dev, "%s: EDID is invalid:\n", connector->name);
  1768. for (i = 0; i < num_blocks; i++) {
  1769. u8 *block = edid + i * EDID_LENGTH;
  1770. char prefix[20];
  1771. if (drm_edid_is_zero(block, EDID_LENGTH))
  1772. sprintf(prefix, "\t[%02x] ZERO ", i);
  1773. else if (!drm_edid_block_valid(block, i, false, NULL))
  1774. sprintf(prefix, "\t[%02x] BAD ", i);
  1775. else
  1776. sprintf(prefix, "\t[%02x] GOOD ", i);
  1777. print_hex_dump(KERN_WARNING,
  1778. prefix, DUMP_PREFIX_NONE, 16, 1,
  1779. block, EDID_LENGTH, false);
  1780. }
  1781. }
  1782. /* Get override or firmware EDID */
  1783. static struct edid *drm_get_override_edid(struct drm_connector *connector)
  1784. {
  1785. struct edid *override = NULL;
  1786. if (connector->override_edid)
  1787. override = drm_edid_duplicate(connector->edid_blob_ptr->data);
  1788. if (!override)
  1789. override = drm_load_edid_firmware(connector);
  1790. return IS_ERR(override) ? NULL : override;
  1791. }
  1792. /**
  1793. * drm_add_override_edid_modes - add modes from override/firmware EDID
  1794. * @connector: connector we're probing
  1795. *
  1796. * Add modes from the override/firmware EDID, if available. Only to be used from
  1797. * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
  1798. * failed during drm_get_edid() and caused the override/firmware EDID to be
  1799. * skipped.
  1800. *
  1801. * Return: The number of modes added or 0 if we couldn't find any.
  1802. */
  1803. int drm_add_override_edid_modes(struct drm_connector *connector)
  1804. {
  1805. struct edid *override;
  1806. int num_modes = 0;
  1807. override = drm_get_override_edid(connector);
  1808. if (override) {
  1809. drm_connector_update_edid_property(connector, override);
  1810. num_modes = drm_add_edid_modes(connector, override);
  1811. kfree(override);
  1812. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
  1813. connector->base.id, connector->name, num_modes);
  1814. }
  1815. return num_modes;
  1816. }
  1817. EXPORT_SYMBOL(drm_add_override_edid_modes);
  1818. /**
  1819. * drm_do_get_edid - get EDID data using a custom EDID block read function
  1820. * @connector: connector we're probing
  1821. * @get_edid_block: EDID block read function
  1822. * @data: private data passed to the block read function
  1823. *
  1824. * When the I2C adapter connected to the DDC bus is hidden behind a device that
  1825. * exposes a different interface to read EDID blocks this function can be used
  1826. * to get EDID data using a custom block read function.
  1827. *
  1828. * As in the general case the DDC bus is accessible by the kernel at the I2C
  1829. * level, drivers must make all reasonable efforts to expose it as an I2C
  1830. * adapter and use drm_get_edid() instead of abusing this function.
  1831. *
  1832. * The EDID may be overridden using debugfs override_edid or firmare EDID
  1833. * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
  1834. * order. Having either of them bypasses actual EDID reads.
  1835. *
  1836. * Return: Pointer to valid EDID or NULL if we couldn't find any.
  1837. */
  1838. struct edid *drm_do_get_edid(struct drm_connector *connector,
  1839. int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
  1840. size_t len),
  1841. void *data)
  1842. {
  1843. int i, j = 0, valid_extensions = 0;
  1844. u8 *edid, *new;
  1845. struct edid *override;
  1846. override = drm_get_override_edid(connector);
  1847. if (override)
  1848. return override;
  1849. if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
  1850. return NULL;
  1851. /* base block fetch */
  1852. for (i = 0; i < 4; i++) {
  1853. if (get_edid_block(data, edid, 0, EDID_LENGTH))
  1854. goto out;
  1855. if (drm_edid_block_valid(edid, 0, false,
  1856. &connector->edid_corrupt))
  1857. break;
  1858. if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
  1859. connector->null_edid_counter++;
  1860. goto carp;
  1861. }
  1862. }
  1863. if (i == 4)
  1864. goto carp;
  1865. /* if there's no extensions, we're done */
  1866. valid_extensions = edid[0x7e];
  1867. if (valid_extensions == 0)
  1868. return (struct edid *)edid;
  1869. new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
  1870. if (!new)
  1871. goto out;
  1872. edid = new;
  1873. for (j = 1; j <= edid[0x7e]; j++) {
  1874. u8 *block = edid + j * EDID_LENGTH;
  1875. for (i = 0; i < 4; i++) {
  1876. if (get_edid_block(data, block, j, EDID_LENGTH))
  1877. goto out;
  1878. if (drm_edid_block_valid(block, j, false, NULL))
  1879. break;
  1880. }
  1881. if (i == 4)
  1882. valid_extensions--;
  1883. }
  1884. if (valid_extensions != edid[0x7e]) {
  1885. u8 *base;
  1886. connector_bad_edid(connector, edid, edid[0x7e] + 1);
  1887. edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
  1888. edid[0x7e] = valid_extensions;
  1889. new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
  1890. GFP_KERNEL);
  1891. if (!new)
  1892. goto out;
  1893. base = new;
  1894. for (i = 0; i <= edid[0x7e]; i++) {
  1895. u8 *block = edid + i * EDID_LENGTH;
  1896. if (!drm_edid_block_valid(block, i, false, NULL))
  1897. continue;
  1898. memcpy(base, block, EDID_LENGTH);
  1899. base += EDID_LENGTH;
  1900. }
  1901. kfree(edid);
  1902. edid = new;
  1903. }
  1904. return (struct edid *)edid;
  1905. carp:
  1906. connector_bad_edid(connector, edid, 1);
  1907. out:
  1908. kfree(edid);
  1909. return NULL;
  1910. }
  1911. EXPORT_SYMBOL_GPL(drm_do_get_edid);
  1912. /**
  1913. * drm_probe_ddc() - probe DDC presence
  1914. * @adapter: I2C adapter to probe
  1915. *
  1916. * Return: True on success, false on failure.
  1917. */
  1918. bool
  1919. drm_probe_ddc(struct i2c_adapter *adapter)
  1920. {
  1921. unsigned char out;
  1922. return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
  1923. }
  1924. EXPORT_SYMBOL(drm_probe_ddc);
  1925. /**
  1926. * drm_get_edid - get EDID data, if available
  1927. * @connector: connector we're probing
  1928. * @adapter: I2C adapter to use for DDC
  1929. *
  1930. * Poke the given I2C channel to grab EDID data if possible. If found,
  1931. * attach it to the connector.
  1932. *
  1933. * Return: Pointer to valid EDID or NULL if we couldn't find any.
  1934. */
  1935. struct edid *drm_get_edid(struct drm_connector *connector,
  1936. struct i2c_adapter *adapter)
  1937. {
  1938. struct edid *edid;
  1939. if (connector->force == DRM_FORCE_OFF)
  1940. return NULL;
  1941. if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
  1942. return NULL;
  1943. edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
  1944. drm_connector_update_edid_property(connector, edid);
  1945. return edid;
  1946. }
  1947. EXPORT_SYMBOL(drm_get_edid);
  1948. /**
  1949. * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
  1950. * @connector: connector we're probing
  1951. * @adapter: I2C adapter to use for DDC
  1952. *
  1953. * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
  1954. * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
  1955. * switch DDC to the GPU which is retrieving EDID.
  1956. *
  1957. * Return: Pointer to valid EDID or %NULL if we couldn't find any.
  1958. */
  1959. struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
  1960. struct i2c_adapter *adapter)
  1961. {
  1962. struct pci_dev *pdev = connector->dev->pdev;
  1963. struct edid *edid;
  1964. vga_switcheroo_lock_ddc(pdev);
  1965. edid = drm_get_edid(connector, adapter);
  1966. vga_switcheroo_unlock_ddc(pdev);
  1967. return edid;
  1968. }
  1969. EXPORT_SYMBOL(drm_get_edid_switcheroo);
  1970. /**
  1971. * drm_edid_duplicate - duplicate an EDID and the extensions
  1972. * @edid: EDID to duplicate
  1973. *
  1974. * Return: Pointer to duplicated EDID or NULL on allocation failure.
  1975. */
  1976. struct edid *drm_edid_duplicate(const struct edid *edid)
  1977. {
  1978. return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
  1979. }
  1980. EXPORT_SYMBOL(drm_edid_duplicate);
  1981. /*** EDID parsing ***/
  1982. /**
  1983. * edid_vendor - match a string against EDID's obfuscated vendor field
  1984. * @edid: EDID to match
  1985. * @vendor: vendor string
  1986. *
  1987. * Returns true if @vendor is in @edid, false otherwise
  1988. */
  1989. static bool edid_vendor(const struct edid *edid, const char *vendor)
  1990. {
  1991. char edid_vendor[3];
  1992. edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
  1993. edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
  1994. ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
  1995. edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
  1996. return !strncmp(edid_vendor, vendor, 3);
  1997. }
  1998. /**
  1999. * edid_get_quirks - return quirk flags for a given EDID
  2000. * @edid: EDID to process
  2001. *
  2002. * This tells subsequent routines what fixes they need to apply.
  2003. */
  2004. static u32 edid_get_quirks(const struct edid *edid)
  2005. {
  2006. const struct edid_quirk *quirk;
  2007. int i;
  2008. for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
  2009. quirk = &edid_quirk_list[i];
  2010. if (edid_vendor(edid, quirk->vendor) &&
  2011. (EDID_PRODUCT_ID(edid) == quirk->product_id))
  2012. return quirk->quirks;
  2013. }
  2014. return 0;
  2015. }
  2016. #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
  2017. #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
  2018. /**
  2019. * edid_fixup_preferred - set preferred modes based on quirk list
  2020. * @connector: has mode list to fix up
  2021. * @quirks: quirks list
  2022. *
  2023. * Walk the mode list for @connector, clearing the preferred status
  2024. * on existing modes and setting it anew for the right mode ala @quirks.
  2025. */
  2026. static void edid_fixup_preferred(struct drm_connector *connector,
  2027. u32 quirks)
  2028. {
  2029. struct drm_display_mode *t, *cur_mode, *preferred_mode;
  2030. int target_refresh = 0;
  2031. int cur_vrefresh, preferred_vrefresh;
  2032. if (list_empty(&connector->probed_modes))
  2033. return;
  2034. if (quirks & EDID_QUIRK_PREFER_LARGE_60)
  2035. target_refresh = 60;
  2036. if (quirks & EDID_QUIRK_PREFER_LARGE_75)
  2037. target_refresh = 75;
  2038. preferred_mode = list_first_entry(&connector->probed_modes,
  2039. struct drm_display_mode, head);
  2040. list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
  2041. cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
  2042. if (cur_mode == preferred_mode)
  2043. continue;
  2044. /* Largest mode is preferred */
  2045. if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
  2046. preferred_mode = cur_mode;
  2047. cur_vrefresh = drm_mode_vrefresh(cur_mode);
  2048. preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
  2049. /* At a given size, try to get closest to target refresh */
  2050. if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
  2051. MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
  2052. MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
  2053. preferred_mode = cur_mode;
  2054. }
  2055. }
  2056. preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
  2057. }
  2058. static bool
  2059. mode_is_rb(const struct drm_display_mode *mode)
  2060. {
  2061. return (mode->htotal - mode->hdisplay == 160) &&
  2062. (mode->hsync_end - mode->hdisplay == 80) &&
  2063. (mode->hsync_end - mode->hsync_start == 32) &&
  2064. (mode->vsync_start - mode->vdisplay == 3);
  2065. }
  2066. /*
  2067. * drm_mode_find_dmt - Create a copy of a mode if present in DMT
  2068. * @dev: Device to duplicate against
  2069. * @hsize: Mode width
  2070. * @vsize: Mode height
  2071. * @fresh: Mode refresh rate
  2072. * @rb: Mode reduced-blanking-ness
  2073. *
  2074. * Walk the DMT mode list looking for a match for the given parameters.
  2075. *
  2076. * Return: A newly allocated copy of the mode, or NULL if not found.
  2077. */
  2078. struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
  2079. int hsize, int vsize, int fresh,
  2080. bool rb)
  2081. {
  2082. int i;
  2083. for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
  2084. const struct drm_display_mode *ptr = &drm_dmt_modes[i];
  2085. if (hsize != ptr->hdisplay)
  2086. continue;
  2087. if (vsize != ptr->vdisplay)
  2088. continue;
  2089. if (fresh != drm_mode_vrefresh(ptr))
  2090. continue;
  2091. if (rb != mode_is_rb(ptr))
  2092. continue;
  2093. return drm_mode_duplicate(dev, ptr);
  2094. }
  2095. return NULL;
  2096. }
  2097. EXPORT_SYMBOL(drm_mode_find_dmt);
  2098. static bool is_display_descriptor(const u8 d[18], u8 tag)
  2099. {
  2100. return d[0] == 0x00 && d[1] == 0x00 &&
  2101. d[2] == 0x00 && d[3] == tag;
  2102. }
  2103. static bool is_detailed_timing_descriptor(const u8 d[18])
  2104. {
  2105. return d[0] != 0x00 || d[1] != 0x00;
  2106. }
  2107. typedef void detailed_cb(struct detailed_timing *timing, void *closure);
  2108. static void
  2109. cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
  2110. {
  2111. int i, n;
  2112. u8 d = ext[0x02];
  2113. u8 *det_base = ext + d;
  2114. if (d < 4 || d > 127)
  2115. return;
  2116. n = (127 - d) / 18;
  2117. for (i = 0; i < n; i++)
  2118. cb((struct detailed_timing *)(det_base + 18 * i), closure);
  2119. }
  2120. static void
  2121. vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
  2122. {
  2123. unsigned int i, n = min((int)ext[0x02], 6);
  2124. u8 *det_base = ext + 5;
  2125. if (ext[0x01] != 1)
  2126. return; /* unknown version */
  2127. for (i = 0; i < n; i++)
  2128. cb((struct detailed_timing *)(det_base + 18 * i), closure);
  2129. }
  2130. static void
  2131. drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
  2132. {
  2133. int i;
  2134. struct edid *edid = (struct edid *)raw_edid;
  2135. if (edid == NULL)
  2136. return;
  2137. for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
  2138. cb(&(edid->detailed_timings[i]), closure);
  2139. for (i = 1; i <= raw_edid[0x7e]; i++) {
  2140. u8 *ext = raw_edid + (i * EDID_LENGTH);
  2141. switch (*ext) {
  2142. case CEA_EXT:
  2143. cea_for_each_detailed_block(ext, cb, closure);
  2144. break;
  2145. case VTB_EXT:
  2146. vtb_for_each_detailed_block(ext, cb, closure);
  2147. break;
  2148. default:
  2149. break;
  2150. }
  2151. }
  2152. }
  2153. static void
  2154. is_rb(struct detailed_timing *t, void *data)
  2155. {
  2156. u8 *r = (u8 *)t;
  2157. if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
  2158. return;
  2159. if (r[15] & 0x10)
  2160. *(bool *)data = true;
  2161. }
  2162. /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
  2163. static bool
  2164. drm_monitor_supports_rb(struct edid *edid)
  2165. {
  2166. if (edid->revision >= 4) {
  2167. bool ret = false;
  2168. drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
  2169. return ret;
  2170. }
  2171. return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
  2172. }
  2173. static void
  2174. find_gtf2(struct detailed_timing *t, void *data)
  2175. {
  2176. u8 *r = (u8 *)t;
  2177. if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
  2178. return;
  2179. if (r[10] == 0x02)
  2180. *(u8 **)data = r;
  2181. }
  2182. /* Secondary GTF curve kicks in above some break frequency */
  2183. static int
  2184. drm_gtf2_hbreak(struct edid *edid)
  2185. {
  2186. u8 *r = NULL;
  2187. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  2188. return r ? (r[12] * 2) : 0;
  2189. }
  2190. static int
  2191. drm_gtf2_2c(struct edid *edid)
  2192. {
  2193. u8 *r = NULL;
  2194. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  2195. return r ? r[13] : 0;
  2196. }
  2197. static int
  2198. drm_gtf2_m(struct edid *edid)
  2199. {
  2200. u8 *r = NULL;
  2201. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  2202. return r ? (r[15] << 8) + r[14] : 0;
  2203. }
  2204. static int
  2205. drm_gtf2_k(struct edid *edid)
  2206. {
  2207. u8 *r = NULL;
  2208. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  2209. return r ? r[16] : 0;
  2210. }
  2211. static int
  2212. drm_gtf2_2j(struct edid *edid)
  2213. {
  2214. u8 *r = NULL;
  2215. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  2216. return r ? r[17] : 0;
  2217. }
  2218. /**
  2219. * standard_timing_level - get std. timing level(CVT/GTF/DMT)
  2220. * @edid: EDID block to scan
  2221. */
  2222. static int standard_timing_level(struct edid *edid)
  2223. {
  2224. if (edid->revision >= 2) {
  2225. if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
  2226. return LEVEL_CVT;
  2227. if (drm_gtf2_hbreak(edid))
  2228. return LEVEL_GTF2;
  2229. if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
  2230. return LEVEL_GTF;
  2231. }
  2232. return LEVEL_DMT;
  2233. }
  2234. /*
  2235. * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
  2236. * monitors fill with ascii space (0x20) instead.
  2237. */
  2238. static int
  2239. bad_std_timing(u8 a, u8 b)
  2240. {
  2241. return (a == 0x00 && b == 0x00) ||
  2242. (a == 0x01 && b == 0x01) ||
  2243. (a == 0x20 && b == 0x20);
  2244. }
  2245. static int drm_mode_hsync(const struct drm_display_mode *mode)
  2246. {
  2247. if (mode->htotal <= 0)
  2248. return 0;
  2249. return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
  2250. }
  2251. /**
  2252. * drm_mode_std - convert standard mode info (width, height, refresh) into mode
  2253. * @connector: connector of for the EDID block
  2254. * @edid: EDID block to scan
  2255. * @t: standard timing params
  2256. *
  2257. * Take the standard timing params (in this case width, aspect, and refresh)
  2258. * and convert them into a real mode using CVT/GTF/DMT.
  2259. */
  2260. static struct drm_display_mode *
  2261. drm_mode_std(struct drm_connector *connector, struct edid *edid,
  2262. struct std_timing *t)
  2263. {
  2264. struct drm_device *dev = connector->dev;
  2265. struct drm_display_mode *m, *mode = NULL;
  2266. int hsize, vsize;
  2267. int vrefresh_rate;
  2268. unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
  2269. >> EDID_TIMING_ASPECT_SHIFT;
  2270. unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
  2271. >> EDID_TIMING_VFREQ_SHIFT;
  2272. int timing_level = standard_timing_level(edid);
  2273. if (bad_std_timing(t->hsize, t->vfreq_aspect))
  2274. return NULL;
  2275. /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
  2276. hsize = t->hsize * 8 + 248;
  2277. /* vrefresh_rate = vfreq + 60 */
  2278. vrefresh_rate = vfreq + 60;
  2279. /* the vdisplay is calculated based on the aspect ratio */
  2280. if (aspect_ratio == 0) {
  2281. if (edid->revision < 3)
  2282. vsize = hsize;
  2283. else
  2284. vsize = (hsize * 10) / 16;
  2285. } else if (aspect_ratio == 1)
  2286. vsize = (hsize * 3) / 4;
  2287. else if (aspect_ratio == 2)
  2288. vsize = (hsize * 4) / 5;
  2289. else
  2290. vsize = (hsize * 9) / 16;
  2291. /* HDTV hack, part 1 */
  2292. if (vrefresh_rate == 60 &&
  2293. ((hsize == 1360 && vsize == 765) ||
  2294. (hsize == 1368 && vsize == 769))) {
  2295. hsize = 1366;
  2296. vsize = 768;
  2297. }
  2298. /*
  2299. * If this connector already has a mode for this size and refresh
  2300. * rate (because it came from detailed or CVT info), use that
  2301. * instead. This way we don't have to guess at interlace or
  2302. * reduced blanking.
  2303. */
  2304. list_for_each_entry(m, &connector->probed_modes, head)
  2305. if (m->hdisplay == hsize && m->vdisplay == vsize &&
  2306. drm_mode_vrefresh(m) == vrefresh_rate)
  2307. return NULL;
  2308. /* HDTV hack, part 2 */
  2309. if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
  2310. mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
  2311. false);
  2312. if (!mode)
  2313. return NULL;
  2314. mode->hdisplay = 1366;
  2315. mode->hsync_start = mode->hsync_start - 1;
  2316. mode->hsync_end = mode->hsync_end - 1;
  2317. return mode;
  2318. }
  2319. /* check whether it can be found in default mode table */
  2320. if (drm_monitor_supports_rb(edid)) {
  2321. mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
  2322. true);
  2323. if (mode)
  2324. return mode;
  2325. }
  2326. mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
  2327. if (mode)
  2328. return mode;
  2329. /* okay, generate it */
  2330. switch (timing_level) {
  2331. case LEVEL_DMT:
  2332. break;
  2333. case LEVEL_GTF:
  2334. mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
  2335. break;
  2336. case LEVEL_GTF2:
  2337. /*
  2338. * This is potentially wrong if there's ever a monitor with
  2339. * more than one ranges section, each claiming a different
  2340. * secondary GTF curve. Please don't do that.
  2341. */
  2342. mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
  2343. if (!mode)
  2344. return NULL;
  2345. if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
  2346. drm_mode_destroy(dev, mode);
  2347. mode = drm_gtf_mode_complex(dev, hsize, vsize,
  2348. vrefresh_rate, 0, 0,
  2349. drm_gtf2_m(edid),
  2350. drm_gtf2_2c(edid),
  2351. drm_gtf2_k(edid),
  2352. drm_gtf2_2j(edid));
  2353. }
  2354. break;
  2355. case LEVEL_CVT:
  2356. mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
  2357. false);
  2358. break;
  2359. }
  2360. return mode;
  2361. }
  2362. /*
  2363. * EDID is delightfully ambiguous about how interlaced modes are to be
  2364. * encoded. Our internal representation is of frame height, but some
  2365. * HDTV detailed timings are encoded as field height.
  2366. *
  2367. * The format list here is from CEA, in frame size. Technically we
  2368. * should be checking refresh rate too. Whatever.
  2369. */
  2370. static void
  2371. drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
  2372. struct detailed_pixel_timing *pt)
  2373. {
  2374. int i;
  2375. static const struct {
  2376. int w, h;
  2377. } cea_interlaced[] = {
  2378. { 1920, 1080 },
  2379. { 720, 480 },
  2380. { 1440, 480 },
  2381. { 2880, 480 },
  2382. { 720, 576 },
  2383. { 1440, 576 },
  2384. { 2880, 576 },
  2385. };
  2386. if (!(pt->misc & DRM_EDID_PT_INTERLACED))
  2387. return;
  2388. for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
  2389. if ((mode->hdisplay == cea_interlaced[i].w) &&
  2390. (mode->vdisplay == cea_interlaced[i].h / 2)) {
  2391. mode->vdisplay *= 2;
  2392. mode->vsync_start *= 2;
  2393. mode->vsync_end *= 2;
  2394. mode->vtotal *= 2;
  2395. mode->vtotal |= 1;
  2396. }
  2397. }
  2398. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  2399. }
  2400. /**
  2401. * drm_mode_detailed - create a new mode from an EDID detailed timing section
  2402. * @dev: DRM device (needed to create new mode)
  2403. * @edid: EDID block
  2404. * @timing: EDID detailed timing info
  2405. * @quirks: quirks to apply
  2406. *
  2407. * An EDID detailed timing block contains enough info for us to create and
  2408. * return a new struct drm_display_mode.
  2409. */
  2410. static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
  2411. struct edid *edid,
  2412. struct detailed_timing *timing,
  2413. u32 quirks)
  2414. {
  2415. struct drm_display_mode *mode;
  2416. struct detailed_pixel_timing *pt = &timing->data.pixel_data;
  2417. unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
  2418. unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
  2419. unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
  2420. unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
  2421. unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
  2422. unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
  2423. unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
  2424. unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
  2425. /* ignore tiny modes */
  2426. if (hactive < 64 || vactive < 64)
  2427. return NULL;
  2428. if (pt->misc & DRM_EDID_PT_STEREO) {
  2429. DRM_DEBUG_KMS("stereo mode not supported\n");
  2430. return NULL;
  2431. }
  2432. if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
  2433. DRM_DEBUG_KMS("composite sync not supported\n");
  2434. }
  2435. /* it is incorrect if hsync/vsync width is zero */
  2436. if (!hsync_pulse_width || !vsync_pulse_width) {
  2437. DRM_DEBUG_KMS("Incorrect Detailed timing. "
  2438. "Wrong Hsync/Vsync pulse width\n");
  2439. return NULL;
  2440. }
  2441. if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
  2442. mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
  2443. if (!mode)
  2444. return NULL;
  2445. goto set_size;
  2446. }
  2447. mode = drm_mode_create(dev);
  2448. if (!mode)
  2449. return NULL;
  2450. if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
  2451. timing->pixel_clock = cpu_to_le16(1088);
  2452. mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
  2453. mode->hdisplay = hactive;
  2454. mode->hsync_start = mode->hdisplay + hsync_offset;
  2455. mode->hsync_end = mode->hsync_start + hsync_pulse_width;
  2456. mode->htotal = mode->hdisplay + hblank;
  2457. mode->vdisplay = vactive;
  2458. mode->vsync_start = mode->vdisplay + vsync_offset;
  2459. mode->vsync_end = mode->vsync_start + vsync_pulse_width;
  2460. mode->vtotal = mode->vdisplay + vblank;
  2461. /* Some EDIDs have bogus h/vtotal values */
  2462. if (mode->hsync_end > mode->htotal)
  2463. mode->htotal = mode->hsync_end + 1;
  2464. if (mode->vsync_end > mode->vtotal)
  2465. mode->vtotal = mode->vsync_end + 1;
  2466. drm_mode_do_interlace_quirk(mode, pt);
  2467. if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
  2468. pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
  2469. }
  2470. mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
  2471. DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
  2472. mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
  2473. DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
  2474. set_size:
  2475. mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
  2476. mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
  2477. if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
  2478. mode->width_mm *= 10;
  2479. mode->height_mm *= 10;
  2480. }
  2481. if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
  2482. mode->width_mm = edid->width_cm * 10;
  2483. mode->height_mm = edid->height_cm * 10;
  2484. }
  2485. mode->type = DRM_MODE_TYPE_DRIVER;
  2486. drm_mode_set_name(mode);
  2487. return mode;
  2488. }
  2489. static bool
  2490. mode_in_hsync_range(const struct drm_display_mode *mode,
  2491. struct edid *edid, u8 *t)
  2492. {
  2493. int hsync, hmin, hmax;
  2494. hmin = t[7];
  2495. if (edid->revision >= 4)
  2496. hmin += ((t[4] & 0x04) ? 255 : 0);
  2497. hmax = t[8];
  2498. if (edid->revision >= 4)
  2499. hmax += ((t[4] & 0x08) ? 255 : 0);
  2500. hsync = drm_mode_hsync(mode);
  2501. return (hsync <= hmax && hsync >= hmin);
  2502. }
  2503. static bool
  2504. mode_in_vsync_range(const struct drm_display_mode *mode,
  2505. struct edid *edid, u8 *t)
  2506. {
  2507. int vsync, vmin, vmax;
  2508. vmin = t[5];
  2509. if (edid->revision >= 4)
  2510. vmin += ((t[4] & 0x01) ? 255 : 0);
  2511. vmax = t[6];
  2512. if (edid->revision >= 4)
  2513. vmax += ((t[4] & 0x02) ? 255 : 0);
  2514. vsync = drm_mode_vrefresh(mode);
  2515. return (vsync <= vmax && vsync >= vmin);
  2516. }
  2517. static u32
  2518. range_pixel_clock(struct edid *edid, u8 *t)
  2519. {
  2520. /* unspecified */
  2521. if (t[9] == 0 || t[9] == 255)
  2522. return 0;
  2523. /* 1.4 with CVT support gives us real precision, yay */
  2524. if (edid->revision >= 4 && t[10] == 0x04)
  2525. return (t[9] * 10000) - ((t[12] >> 2) * 250);
  2526. /* 1.3 is pathetic, so fuzz up a bit */
  2527. return t[9] * 10000 + 5001;
  2528. }
  2529. static bool
  2530. mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
  2531. struct detailed_timing *timing)
  2532. {
  2533. u32 max_clock;
  2534. u8 *t = (u8 *)timing;
  2535. if (!mode_in_hsync_range(mode, edid, t))
  2536. return false;
  2537. if (!mode_in_vsync_range(mode, edid, t))
  2538. return false;
  2539. if ((max_clock = range_pixel_clock(edid, t)))
  2540. if (mode->clock > max_clock)
  2541. return false;
  2542. /* 1.4 max horizontal check */
  2543. if (edid->revision >= 4 && t[10] == 0x04)
  2544. if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
  2545. return false;
  2546. if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
  2547. return false;
  2548. return true;
  2549. }
  2550. static bool valid_inferred_mode(const struct drm_connector *connector,
  2551. const struct drm_display_mode *mode)
  2552. {
  2553. const struct drm_display_mode *m;
  2554. bool ok = false;
  2555. list_for_each_entry(m, &connector->probed_modes, head) {
  2556. if (mode->hdisplay == m->hdisplay &&
  2557. mode->vdisplay == m->vdisplay &&
  2558. drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
  2559. return false; /* duplicated */
  2560. if (mode->hdisplay <= m->hdisplay &&
  2561. mode->vdisplay <= m->vdisplay)
  2562. ok = true;
  2563. }
  2564. return ok;
  2565. }
  2566. static int
  2567. drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
  2568. struct detailed_timing *timing)
  2569. {
  2570. int i, modes = 0;
  2571. struct drm_display_mode *newmode;
  2572. struct drm_device *dev = connector->dev;
  2573. for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
  2574. if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
  2575. valid_inferred_mode(connector, drm_dmt_modes + i)) {
  2576. newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
  2577. if (newmode) {
  2578. drm_mode_probed_add(connector, newmode);
  2579. modes++;
  2580. }
  2581. }
  2582. }
  2583. return modes;
  2584. }
  2585. /* fix up 1366x768 mode from 1368x768;
  2586. * GFT/CVT can't express 1366 width which isn't dividable by 8
  2587. */
  2588. void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
  2589. {
  2590. if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
  2591. mode->hdisplay = 1366;
  2592. mode->hsync_start--;
  2593. mode->hsync_end--;
  2594. drm_mode_set_name(mode);
  2595. }
  2596. }
  2597. static int
  2598. drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
  2599. struct detailed_timing *timing)
  2600. {
  2601. int i, modes = 0;
  2602. struct drm_display_mode *newmode;
  2603. struct drm_device *dev = connector->dev;
  2604. for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
  2605. const struct minimode *m = &extra_modes[i];
  2606. newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
  2607. if (!newmode)
  2608. return modes;
  2609. drm_mode_fixup_1366x768(newmode);
  2610. if (!mode_in_range(newmode, edid, timing) ||
  2611. !valid_inferred_mode(connector, newmode)) {
  2612. drm_mode_destroy(dev, newmode);
  2613. continue;
  2614. }
  2615. drm_mode_probed_add(connector, newmode);
  2616. modes++;
  2617. }
  2618. return modes;
  2619. }
  2620. static int
  2621. drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
  2622. struct detailed_timing *timing)
  2623. {
  2624. int i, modes = 0;
  2625. struct drm_display_mode *newmode;
  2626. struct drm_device *dev = connector->dev;
  2627. bool rb = drm_monitor_supports_rb(edid);
  2628. for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
  2629. const struct minimode *m = &extra_modes[i];
  2630. newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
  2631. if (!newmode)
  2632. return modes;
  2633. drm_mode_fixup_1366x768(newmode);
  2634. if (!mode_in_range(newmode, edid, timing) ||
  2635. !valid_inferred_mode(connector, newmode)) {
  2636. drm_mode_destroy(dev, newmode);
  2637. continue;
  2638. }
  2639. drm_mode_probed_add(connector, newmode);
  2640. modes++;
  2641. }
  2642. return modes;
  2643. }
  2644. static void
  2645. do_inferred_modes(struct detailed_timing *timing, void *c)
  2646. {
  2647. struct detailed_mode_closure *closure = c;
  2648. struct detailed_non_pixel *data = &timing->data.other_data;
  2649. struct detailed_data_monitor_range *range = &data->data.range;
  2650. if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
  2651. return;
  2652. closure->modes += drm_dmt_modes_for_range(closure->connector,
  2653. closure->edid,
  2654. timing);
  2655. if (!version_greater(closure->edid, 1, 1))
  2656. return; /* GTF not defined yet */
  2657. switch (range->flags) {
  2658. case 0x02: /* secondary gtf, XXX could do more */
  2659. case 0x00: /* default gtf */
  2660. closure->modes += drm_gtf_modes_for_range(closure->connector,
  2661. closure->edid,
  2662. timing);
  2663. break;
  2664. case 0x04: /* cvt, only in 1.4+ */
  2665. if (!version_greater(closure->edid, 1, 3))
  2666. break;
  2667. closure->modes += drm_cvt_modes_for_range(closure->connector,
  2668. closure->edid,
  2669. timing);
  2670. break;
  2671. case 0x01: /* just the ranges, no formula */
  2672. default:
  2673. break;
  2674. }
  2675. }
  2676. static int
  2677. add_inferred_modes(struct drm_connector *connector, struct edid *edid)
  2678. {
  2679. struct detailed_mode_closure closure = {
  2680. .connector = connector,
  2681. .edid = edid,
  2682. };
  2683. if (version_greater(edid, 1, 0))
  2684. drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
  2685. &closure);
  2686. return closure.modes;
  2687. }
  2688. static int
  2689. drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
  2690. {
  2691. int i, j, m, modes = 0;
  2692. struct drm_display_mode *mode;
  2693. u8 *est = ((u8 *)timing) + 6;
  2694. for (i = 0; i < 6; i++) {
  2695. for (j = 7; j >= 0; j--) {
  2696. m = (i * 8) + (7 - j);
  2697. if (m >= ARRAY_SIZE(est3_modes))
  2698. break;
  2699. if (est[i] & (1 << j)) {
  2700. mode = drm_mode_find_dmt(connector->dev,
  2701. est3_modes[m].w,
  2702. est3_modes[m].h,
  2703. est3_modes[m].r,
  2704. est3_modes[m].rb);
  2705. if (mode) {
  2706. drm_mode_probed_add(connector, mode);
  2707. modes++;
  2708. }
  2709. }
  2710. }
  2711. }
  2712. return modes;
  2713. }
  2714. static void
  2715. do_established_modes(struct detailed_timing *timing, void *c)
  2716. {
  2717. struct detailed_mode_closure *closure = c;
  2718. if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
  2719. return;
  2720. closure->modes += drm_est3_modes(closure->connector, timing);
  2721. }
  2722. /**
  2723. * add_established_modes - get est. modes from EDID and add them
  2724. * @connector: connector to add mode(s) to
  2725. * @edid: EDID block to scan
  2726. *
  2727. * Each EDID block contains a bitmap of the supported "established modes" list
  2728. * (defined above). Tease them out and add them to the global modes list.
  2729. */
  2730. static int
  2731. add_established_modes(struct drm_connector *connector, struct edid *edid)
  2732. {
  2733. struct drm_device *dev = connector->dev;
  2734. unsigned long est_bits = edid->established_timings.t1 |
  2735. (edid->established_timings.t2 << 8) |
  2736. ((edid->established_timings.mfg_rsvd & 0x80) << 9);
  2737. int i, modes = 0;
  2738. struct detailed_mode_closure closure = {
  2739. .connector = connector,
  2740. .edid = edid,
  2741. };
  2742. for (i = 0; i <= EDID_EST_TIMINGS; i++) {
  2743. if (est_bits & (1<<i)) {
  2744. struct drm_display_mode *newmode;
  2745. newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
  2746. if (newmode) {
  2747. drm_mode_probed_add(connector, newmode);
  2748. modes++;
  2749. }
  2750. }
  2751. }
  2752. if (version_greater(edid, 1, 0))
  2753. drm_for_each_detailed_block((u8 *)edid,
  2754. do_established_modes, &closure);
  2755. return modes + closure.modes;
  2756. }
  2757. static void
  2758. do_standard_modes(struct detailed_timing *timing, void *c)
  2759. {
  2760. struct detailed_mode_closure *closure = c;
  2761. struct detailed_non_pixel *data = &timing->data.other_data;
  2762. struct drm_connector *connector = closure->connector;
  2763. struct edid *edid = closure->edid;
  2764. int i;
  2765. if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
  2766. return;
  2767. for (i = 0; i < 6; i++) {
  2768. struct std_timing *std = &data->data.timings[i];
  2769. struct drm_display_mode *newmode;
  2770. newmode = drm_mode_std(connector, edid, std);
  2771. if (newmode) {
  2772. drm_mode_probed_add(connector, newmode);
  2773. closure->modes++;
  2774. }
  2775. }
  2776. }
  2777. /**
  2778. * add_standard_modes - get std. modes from EDID and add them
  2779. * @connector: connector to add mode(s) to
  2780. * @edid: EDID block to scan
  2781. *
  2782. * Standard modes can be calculated using the appropriate standard (DMT,
  2783. * GTF or CVT. Grab them from @edid and add them to the list.
  2784. */
  2785. static int
  2786. add_standard_modes(struct drm_connector *connector, struct edid *edid)
  2787. {
  2788. int i, modes = 0;
  2789. struct detailed_mode_closure closure = {
  2790. .connector = connector,
  2791. .edid = edid,
  2792. };
  2793. for (i = 0; i < EDID_STD_TIMINGS; i++) {
  2794. struct drm_display_mode *newmode;
  2795. newmode = drm_mode_std(connector, edid,
  2796. &edid->standard_timings[i]);
  2797. if (newmode) {
  2798. drm_mode_probed_add(connector, newmode);
  2799. modes++;
  2800. }
  2801. }
  2802. if (version_greater(edid, 1, 0))
  2803. drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
  2804. &closure);
  2805. /* XXX should also look for standard codes in VTB blocks */
  2806. return modes + closure.modes;
  2807. }
  2808. static int drm_cvt_modes(struct drm_connector *connector,
  2809. struct detailed_timing *timing)
  2810. {
  2811. int i, j, modes = 0;
  2812. struct drm_display_mode *newmode;
  2813. struct drm_device *dev = connector->dev;
  2814. struct cvt_timing *cvt;
  2815. const int rates[] = { 60, 85, 75, 60, 50 };
  2816. const u8 empty[3] = { 0, 0, 0 };
  2817. for (i = 0; i < 4; i++) {
  2818. int width, height;
  2819. cvt = &(timing->data.other_data.data.cvt[i]);
  2820. if (!memcmp(cvt->code, empty, 3))
  2821. continue;
  2822. height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
  2823. switch (cvt->code[1] & 0x0c) {
  2824. /* default - because compiler doesn't see that we've enumerated all cases */
  2825. default:
  2826. case 0x00:
  2827. width = height * 4 / 3;
  2828. break;
  2829. case 0x04:
  2830. width = height * 16 / 9;
  2831. break;
  2832. case 0x08:
  2833. width = height * 16 / 10;
  2834. break;
  2835. case 0x0c:
  2836. width = height * 15 / 9;
  2837. break;
  2838. }
  2839. for (j = 1; j < 5; j++) {
  2840. if (cvt->code[2] & (1 << j)) {
  2841. newmode = drm_cvt_mode(dev, width, height,
  2842. rates[j], j == 0,
  2843. false, false);
  2844. if (newmode) {
  2845. drm_mode_probed_add(connector, newmode);
  2846. modes++;
  2847. }
  2848. }
  2849. }
  2850. }
  2851. return modes;
  2852. }
  2853. static void
  2854. do_cvt_mode(struct detailed_timing *timing, void *c)
  2855. {
  2856. struct detailed_mode_closure *closure = c;
  2857. if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
  2858. return;
  2859. closure->modes += drm_cvt_modes(closure->connector, timing);
  2860. }
  2861. static int
  2862. add_cvt_modes(struct drm_connector *connector, struct edid *edid)
  2863. {
  2864. struct detailed_mode_closure closure = {
  2865. .connector = connector,
  2866. .edid = edid,
  2867. };
  2868. if (version_greater(edid, 1, 2))
  2869. drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
  2870. /* XXX should also look for CVT codes in VTB blocks */
  2871. return closure.modes;
  2872. }
  2873. static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
  2874. static void
  2875. do_detailed_mode(struct detailed_timing *timing, void *c)
  2876. {
  2877. struct detailed_mode_closure *closure = c;
  2878. struct drm_display_mode *newmode;
  2879. if (!is_detailed_timing_descriptor((const u8 *)timing))
  2880. return;
  2881. newmode = drm_mode_detailed(closure->connector->dev,
  2882. closure->edid, timing,
  2883. closure->quirks);
  2884. if (!newmode)
  2885. return;
  2886. if (closure->preferred)
  2887. newmode->type |= DRM_MODE_TYPE_PREFERRED;
  2888. /*
  2889. * Detailed modes are limited to 10kHz pixel clock resolution,
  2890. * so fix up anything that looks like CEA/HDMI mode, but the clock
  2891. * is just slightly off.
  2892. */
  2893. fixup_detailed_cea_mode_clock(newmode);
  2894. drm_mode_probed_add(closure->connector, newmode);
  2895. closure->modes++;
  2896. closure->preferred = false;
  2897. }
  2898. /*
  2899. * add_detailed_modes - Add modes from detailed timings
  2900. * @connector: attached connector
  2901. * @edid: EDID block to scan
  2902. * @quirks: quirks to apply
  2903. */
  2904. static int
  2905. add_detailed_modes(struct drm_connector *connector, struct edid *edid,
  2906. u32 quirks)
  2907. {
  2908. struct detailed_mode_closure closure = {
  2909. .connector = connector,
  2910. .edid = edid,
  2911. .preferred = true,
  2912. .quirks = quirks,
  2913. };
  2914. if (closure.preferred && !version_greater(edid, 1, 3))
  2915. closure.preferred =
  2916. (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
  2917. drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
  2918. return closure.modes;
  2919. }
  2920. #define AUDIO_BLOCK 0x01
  2921. #define VIDEO_BLOCK 0x02
  2922. #define VENDOR_BLOCK 0x03
  2923. #define SPEAKER_BLOCK 0x04
  2924. #define HDR_STATIC_METADATA_BLOCK 0x6
  2925. #define USE_EXTENDED_TAG 0x07
  2926. #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
  2927. #define EXT_VIDEO_DATA_BLOCK_420 0x0E
  2928. #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
  2929. #define EDID_BASIC_AUDIO (1 << 6)
  2930. #define EDID_CEA_YCRCB444 (1 << 5)
  2931. #define EDID_CEA_YCRCB422 (1 << 4)
  2932. #define EDID_CEA_VCDB_QS (1 << 6)
  2933. /*
  2934. * Search EDID for CEA extension block.
  2935. */
  2936. static u8 *drm_find_edid_extension(const struct edid *edid,
  2937. int ext_id, int *ext_index)
  2938. {
  2939. u8 *edid_ext = NULL;
  2940. int i;
  2941. /* No EDID or EDID extensions */
  2942. if (edid == NULL || edid->extensions == 0)
  2943. return NULL;
  2944. /* Find CEA extension */
  2945. for (i = *ext_index; i < edid->extensions; i++) {
  2946. edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
  2947. if (edid_ext[0] == ext_id)
  2948. break;
  2949. }
  2950. if (i >= edid->extensions)
  2951. return NULL;
  2952. *ext_index = i + 1;
  2953. return edid_ext;
  2954. }
  2955. static u8 *drm_find_displayid_extension(const struct edid *edid,
  2956. int *length, int *idx,
  2957. int *ext_index)
  2958. {
  2959. u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index);
  2960. struct displayid_hdr *base;
  2961. int ret;
  2962. if (!displayid)
  2963. return NULL;
  2964. /* EDID extensions block checksum isn't for us */
  2965. *length = EDID_LENGTH - 1;
  2966. *idx = 1;
  2967. ret = validate_displayid(displayid, *length, *idx);
  2968. if (ret)
  2969. return NULL;
  2970. base = (struct displayid_hdr *)&displayid[*idx];
  2971. *length = *idx + sizeof(*base) + base->bytes;
  2972. return displayid;
  2973. }
  2974. static u8 *drm_find_cea_extension(const struct edid *edid)
  2975. {
  2976. int length, idx;
  2977. struct displayid_block *block;
  2978. u8 *cea;
  2979. u8 *displayid;
  2980. int ext_index;
  2981. /* Look for a top level CEA extension block */
  2982. /* FIXME: make callers iterate through multiple CEA ext blocks? */
  2983. ext_index = 0;
  2984. cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
  2985. if (cea)
  2986. return cea;
  2987. /* CEA blocks can also be found embedded in a DisplayID block */
  2988. ext_index = 0;
  2989. for (;;) {
  2990. displayid = drm_find_displayid_extension(edid, &length, &idx,
  2991. &ext_index);
  2992. if (!displayid)
  2993. return NULL;
  2994. idx += sizeof(struct displayid_hdr);
  2995. for_each_displayid_db(displayid, block, idx, length) {
  2996. if (block->tag == DATA_BLOCK_CTA)
  2997. return (u8 *)block;
  2998. }
  2999. }
  3000. return NULL;
  3001. }
  3002. static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
  3003. {
  3004. BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
  3005. BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
  3006. if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
  3007. return &edid_cea_modes_1[vic - 1];
  3008. if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
  3009. return &edid_cea_modes_193[vic - 193];
  3010. return NULL;
  3011. }
  3012. static u8 cea_num_vics(void)
  3013. {
  3014. return 193 + ARRAY_SIZE(edid_cea_modes_193);
  3015. }
  3016. static u8 cea_next_vic(u8 vic)
  3017. {
  3018. if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
  3019. vic = 193;
  3020. return vic;
  3021. }
  3022. /*
  3023. * Calculate the alternate clock for the CEA mode
  3024. * (60Hz vs. 59.94Hz etc.)
  3025. */
  3026. static unsigned int
  3027. cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
  3028. {
  3029. unsigned int clock = cea_mode->clock;
  3030. if (drm_mode_vrefresh(cea_mode) % 6 != 0)
  3031. return clock;
  3032. /*
  3033. * edid_cea_modes contains the 59.94Hz
  3034. * variant for 240 and 480 line modes,
  3035. * and the 60Hz variant otherwise.
  3036. */
  3037. if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
  3038. clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
  3039. else
  3040. clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
  3041. return clock;
  3042. }
  3043. static bool
  3044. cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
  3045. {
  3046. /*
  3047. * For certain VICs the spec allows the vertical
  3048. * front porch to vary by one or two lines.
  3049. *
  3050. * cea_modes[] stores the variant with the shortest
  3051. * vertical front porch. We can adjust the mode to
  3052. * get the other variants by simply increasing the
  3053. * vertical front porch length.
  3054. */
  3055. BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
  3056. cea_mode_for_vic(9)->vtotal != 262 ||
  3057. cea_mode_for_vic(12)->vtotal != 262 ||
  3058. cea_mode_for_vic(13)->vtotal != 262 ||
  3059. cea_mode_for_vic(23)->vtotal != 312 ||
  3060. cea_mode_for_vic(24)->vtotal != 312 ||
  3061. cea_mode_for_vic(27)->vtotal != 312 ||
  3062. cea_mode_for_vic(28)->vtotal != 312);
  3063. if (((vic == 8 || vic == 9 ||
  3064. vic == 12 || vic == 13) && mode->vtotal < 263) ||
  3065. ((vic == 23 || vic == 24 ||
  3066. vic == 27 || vic == 28) && mode->vtotal < 314)) {
  3067. mode->vsync_start++;
  3068. mode->vsync_end++;
  3069. mode->vtotal++;
  3070. return true;
  3071. }
  3072. return false;
  3073. }
  3074. static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
  3075. unsigned int clock_tolerance)
  3076. {
  3077. unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
  3078. u8 vic;
  3079. if (!to_match->clock)
  3080. return 0;
  3081. if (to_match->picture_aspect_ratio)
  3082. match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
  3083. for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
  3084. struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
  3085. unsigned int clock1, clock2;
  3086. /* Check both 60Hz and 59.94Hz */
  3087. clock1 = cea_mode.clock;
  3088. clock2 = cea_mode_alternate_clock(&cea_mode);
  3089. if (abs(to_match->clock - clock1) > clock_tolerance &&
  3090. abs(to_match->clock - clock2) > clock_tolerance)
  3091. continue;
  3092. do {
  3093. if (drm_mode_match(to_match, &cea_mode, match_flags))
  3094. return vic;
  3095. } while (cea_mode_alternate_timings(vic, &cea_mode));
  3096. }
  3097. return 0;
  3098. }
  3099. /**
  3100. * drm_match_cea_mode - look for a CEA mode matching given mode
  3101. * @to_match: display mode
  3102. *
  3103. * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
  3104. * mode.
  3105. */
  3106. u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
  3107. {
  3108. unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
  3109. u8 vic;
  3110. if (!to_match->clock)
  3111. return 0;
  3112. if (to_match->picture_aspect_ratio)
  3113. match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
  3114. for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
  3115. struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
  3116. unsigned int clock1, clock2;
  3117. /* Check both 60Hz and 59.94Hz */
  3118. clock1 = cea_mode.clock;
  3119. clock2 = cea_mode_alternate_clock(&cea_mode);
  3120. if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
  3121. KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
  3122. continue;
  3123. do {
  3124. if (drm_mode_match(to_match, &cea_mode, match_flags))
  3125. return vic;
  3126. } while (cea_mode_alternate_timings(vic, &cea_mode));
  3127. }
  3128. return 0;
  3129. }
  3130. EXPORT_SYMBOL(drm_match_cea_mode);
  3131. static bool drm_valid_cea_vic(u8 vic)
  3132. {
  3133. return cea_mode_for_vic(vic) != NULL;
  3134. }
  3135. static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
  3136. {
  3137. const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
  3138. if (mode)
  3139. return mode->picture_aspect_ratio;
  3140. return HDMI_PICTURE_ASPECT_NONE;
  3141. }
  3142. static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
  3143. {
  3144. return edid_4k_modes[video_code].picture_aspect_ratio;
  3145. }
  3146. /*
  3147. * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
  3148. * specific block).
  3149. */
  3150. static unsigned int
  3151. hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
  3152. {
  3153. return cea_mode_alternate_clock(hdmi_mode);
  3154. }
  3155. static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
  3156. unsigned int clock_tolerance)
  3157. {
  3158. unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
  3159. u8 vic;
  3160. if (!to_match->clock)
  3161. return 0;
  3162. if (to_match->picture_aspect_ratio)
  3163. match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
  3164. for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
  3165. const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
  3166. unsigned int clock1, clock2;
  3167. /* Make sure to also match alternate clocks */
  3168. clock1 = hdmi_mode->clock;
  3169. clock2 = hdmi_mode_alternate_clock(hdmi_mode);
  3170. if (abs(to_match->clock - clock1) > clock_tolerance &&
  3171. abs(to_match->clock - clock2) > clock_tolerance)
  3172. continue;
  3173. if (drm_mode_match(to_match, hdmi_mode, match_flags))
  3174. return vic;
  3175. }
  3176. return 0;
  3177. }
  3178. /*
  3179. * drm_match_hdmi_mode - look for a HDMI mode matching given mode
  3180. * @to_match: display mode
  3181. *
  3182. * An HDMI mode is one defined in the HDMI vendor specific block.
  3183. *
  3184. * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
  3185. */
  3186. static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
  3187. {
  3188. unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
  3189. u8 vic;
  3190. if (!to_match->clock)
  3191. return 0;
  3192. if (to_match->picture_aspect_ratio)
  3193. match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
  3194. for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
  3195. const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
  3196. unsigned int clock1, clock2;
  3197. /* Make sure to also match alternate clocks */
  3198. clock1 = hdmi_mode->clock;
  3199. clock2 = hdmi_mode_alternate_clock(hdmi_mode);
  3200. if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
  3201. KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
  3202. drm_mode_match(to_match, hdmi_mode, match_flags))
  3203. return vic;
  3204. }
  3205. return 0;
  3206. }
  3207. static bool drm_valid_hdmi_vic(u8 vic)
  3208. {
  3209. return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
  3210. }
  3211. static int
  3212. add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
  3213. {
  3214. struct drm_device *dev = connector->dev;
  3215. struct drm_display_mode *mode, *tmp;
  3216. LIST_HEAD(list);
  3217. int modes = 0;
  3218. /* Don't add CEA modes if the CEA extension block is missing */
  3219. if (!drm_find_cea_extension(edid))
  3220. return 0;
  3221. /*
  3222. * Go through all probed modes and create a new mode
  3223. * with the alternate clock for certain CEA modes.
  3224. */
  3225. list_for_each_entry(mode, &connector->probed_modes, head) {
  3226. const struct drm_display_mode *cea_mode = NULL;
  3227. struct drm_display_mode *newmode;
  3228. u8 vic = drm_match_cea_mode(mode);
  3229. unsigned int clock1, clock2;
  3230. if (drm_valid_cea_vic(vic)) {
  3231. cea_mode = cea_mode_for_vic(vic);
  3232. clock2 = cea_mode_alternate_clock(cea_mode);
  3233. } else {
  3234. vic = drm_match_hdmi_mode(mode);
  3235. if (drm_valid_hdmi_vic(vic)) {
  3236. cea_mode = &edid_4k_modes[vic];
  3237. clock2 = hdmi_mode_alternate_clock(cea_mode);
  3238. }
  3239. }
  3240. if (!cea_mode)
  3241. continue;
  3242. clock1 = cea_mode->clock;
  3243. if (clock1 == clock2)
  3244. continue;
  3245. if (mode->clock != clock1 && mode->clock != clock2)
  3246. continue;
  3247. newmode = drm_mode_duplicate(dev, cea_mode);
  3248. if (!newmode)
  3249. continue;
  3250. /* Carry over the stereo flags */
  3251. newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
  3252. /*
  3253. * The current mode could be either variant. Make
  3254. * sure to pick the "other" clock for the new mode.
  3255. */
  3256. if (mode->clock != clock1)
  3257. newmode->clock = clock1;
  3258. else
  3259. newmode->clock = clock2;
  3260. list_add_tail(&newmode->head, &list);
  3261. }
  3262. list_for_each_entry_safe(mode, tmp, &list, head) {
  3263. list_del(&mode->head);
  3264. drm_mode_probed_add(connector, mode);
  3265. modes++;
  3266. }
  3267. return modes;
  3268. }
  3269. static u8 svd_to_vic(u8 svd)
  3270. {
  3271. /* 0-6 bit vic, 7th bit native mode indicator */
  3272. if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
  3273. return svd & 127;
  3274. return svd;
  3275. }
  3276. static struct drm_display_mode *
  3277. drm_display_mode_from_vic_index(struct drm_connector *connector,
  3278. const u8 *video_db, u8 video_len,
  3279. u8 video_index)
  3280. {
  3281. struct drm_device *dev = connector->dev;
  3282. struct drm_display_mode *newmode;
  3283. u8 vic;
  3284. if (video_db == NULL || video_index >= video_len)
  3285. return NULL;
  3286. /* CEA modes are numbered 1..127 */
  3287. vic = svd_to_vic(video_db[video_index]);
  3288. if (!drm_valid_cea_vic(vic))
  3289. return NULL;
  3290. newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
  3291. if (!newmode)
  3292. return NULL;
  3293. return newmode;
  3294. }
  3295. /*
  3296. * do_y420vdb_modes - Parse YCBCR 420 only modes
  3297. * @connector: connector corresponding to the HDMI sink
  3298. * @svds: start of the data block of CEA YCBCR 420 VDB
  3299. * @len: length of the CEA YCBCR 420 VDB
  3300. *
  3301. * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
  3302. * which contains modes which can be supported in YCBCR 420
  3303. * output format only.
  3304. */
  3305. static int do_y420vdb_modes(struct drm_connector *connector,
  3306. const u8 *svds, u8 svds_len)
  3307. {
  3308. int modes = 0, i;
  3309. struct drm_device *dev = connector->dev;
  3310. struct drm_display_info *info = &connector->display_info;
  3311. struct drm_hdmi_info *hdmi = &info->hdmi;
  3312. for (i = 0; i < svds_len; i++) {
  3313. u8 vic = svd_to_vic(svds[i]);
  3314. struct drm_display_mode *newmode;
  3315. if (!drm_valid_cea_vic(vic))
  3316. continue;
  3317. newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
  3318. if (!newmode)
  3319. break;
  3320. bitmap_set(hdmi->y420_vdb_modes, vic, 1);
  3321. drm_mode_probed_add(connector, newmode);
  3322. modes++;
  3323. }
  3324. if (modes > 0)
  3325. info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
  3326. return modes;
  3327. }
  3328. /*
  3329. * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
  3330. * @connector: connector corresponding to the HDMI sink
  3331. * @vic: CEA vic for the video mode to be added in the map
  3332. *
  3333. * Makes an entry for a videomode in the YCBCR 420 bitmap
  3334. */
  3335. static void
  3336. drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
  3337. {
  3338. u8 vic = svd_to_vic(svd);
  3339. struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
  3340. if (!drm_valid_cea_vic(vic))
  3341. return;
  3342. bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
  3343. }
  3344. /**
  3345. * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
  3346. * @dev: DRM device
  3347. * @video_code: CEA VIC of the mode
  3348. *
  3349. * Creates a new mode matching the specified CEA VIC.
  3350. *
  3351. * Returns: A new drm_display_mode on success or NULL on failure
  3352. */
  3353. struct drm_display_mode *
  3354. drm_display_mode_from_cea_vic(struct drm_device *dev,
  3355. u8 video_code)
  3356. {
  3357. const struct drm_display_mode *cea_mode;
  3358. struct drm_display_mode *newmode;
  3359. cea_mode = cea_mode_for_vic(video_code);
  3360. if (!cea_mode)
  3361. return NULL;
  3362. newmode = drm_mode_duplicate(dev, cea_mode);
  3363. if (!newmode)
  3364. return NULL;
  3365. return newmode;
  3366. }
  3367. EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
  3368. static int
  3369. do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
  3370. {
  3371. int i, modes = 0;
  3372. struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
  3373. for (i = 0; i < len; i++) {
  3374. struct drm_display_mode *mode;
  3375. mode = drm_display_mode_from_vic_index(connector, db, len, i);
  3376. if (mode) {
  3377. /*
  3378. * YCBCR420 capability block contains a bitmap which
  3379. * gives the index of CEA modes from CEA VDB, which
  3380. * can support YCBCR 420 sampling output also (apart
  3381. * from RGB/YCBCR444 etc).
  3382. * For example, if the bit 0 in bitmap is set,
  3383. * first mode in VDB can support YCBCR420 output too.
  3384. * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
  3385. */
  3386. if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
  3387. drm_add_cmdb_modes(connector, db[i]);
  3388. drm_mode_probed_add(connector, mode);
  3389. modes++;
  3390. }
  3391. }
  3392. return modes;
  3393. }
  3394. struct stereo_mandatory_mode {
  3395. int width, height, vrefresh;
  3396. unsigned int flags;
  3397. };
  3398. static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
  3399. { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
  3400. { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
  3401. { 1920, 1080, 50,
  3402. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
  3403. { 1920, 1080, 60,
  3404. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
  3405. { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
  3406. { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
  3407. { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
  3408. { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
  3409. };
  3410. static bool
  3411. stereo_match_mandatory(const struct drm_display_mode *mode,
  3412. const struct stereo_mandatory_mode *stereo_mode)
  3413. {
  3414. unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
  3415. return mode->hdisplay == stereo_mode->width &&
  3416. mode->vdisplay == stereo_mode->height &&
  3417. interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
  3418. drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
  3419. }
  3420. static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
  3421. {
  3422. struct drm_device *dev = connector->dev;
  3423. const struct drm_display_mode *mode;
  3424. struct list_head stereo_modes;
  3425. int modes = 0, i;
  3426. INIT_LIST_HEAD(&stereo_modes);
  3427. list_for_each_entry(mode, &connector->probed_modes, head) {
  3428. for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
  3429. const struct stereo_mandatory_mode *mandatory;
  3430. struct drm_display_mode *new_mode;
  3431. if (!stereo_match_mandatory(mode,
  3432. &stereo_mandatory_modes[i]))
  3433. continue;
  3434. mandatory = &stereo_mandatory_modes[i];
  3435. new_mode = drm_mode_duplicate(dev, mode);
  3436. if (!new_mode)
  3437. continue;
  3438. new_mode->flags |= mandatory->flags;
  3439. list_add_tail(&new_mode->head, &stereo_modes);
  3440. modes++;
  3441. }
  3442. }
  3443. list_splice_tail(&stereo_modes, &connector->probed_modes);
  3444. return modes;
  3445. }
  3446. static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
  3447. {
  3448. struct drm_device *dev = connector->dev;
  3449. struct drm_display_mode *newmode;
  3450. if (!drm_valid_hdmi_vic(vic)) {
  3451. DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
  3452. return 0;
  3453. }
  3454. newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
  3455. if (!newmode)
  3456. return 0;
  3457. drm_mode_probed_add(connector, newmode);
  3458. return 1;
  3459. }
  3460. static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
  3461. const u8 *video_db, u8 video_len, u8 video_index)
  3462. {
  3463. struct drm_display_mode *newmode;
  3464. int modes = 0;
  3465. if (structure & (1 << 0)) {
  3466. newmode = drm_display_mode_from_vic_index(connector, video_db,
  3467. video_len,
  3468. video_index);
  3469. if (newmode) {
  3470. newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
  3471. drm_mode_probed_add(connector, newmode);
  3472. modes++;
  3473. }
  3474. }
  3475. if (structure & (1 << 6)) {
  3476. newmode = drm_display_mode_from_vic_index(connector, video_db,
  3477. video_len,
  3478. video_index);
  3479. if (newmode) {
  3480. newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
  3481. drm_mode_probed_add(connector, newmode);
  3482. modes++;
  3483. }
  3484. }
  3485. if (structure & (1 << 8)) {
  3486. newmode = drm_display_mode_from_vic_index(connector, video_db,
  3487. video_len,
  3488. video_index);
  3489. if (newmode) {
  3490. newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
  3491. drm_mode_probed_add(connector, newmode);
  3492. modes++;
  3493. }
  3494. }
  3495. return modes;
  3496. }
  3497. /*
  3498. * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
  3499. * @connector: connector corresponding to the HDMI sink
  3500. * @db: start of the CEA vendor specific block
  3501. * @len: length of the CEA block payload, ie. one can access up to db[len]
  3502. *
  3503. * Parses the HDMI VSDB looking for modes to add to @connector. This function
  3504. * also adds the stereo 3d modes when applicable.
  3505. */
  3506. static int
  3507. do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
  3508. const u8 *video_db, u8 video_len)
  3509. {
  3510. struct drm_display_info *info = &connector->display_info;
  3511. int modes = 0, offset = 0, i, multi_present = 0, multi_len;
  3512. u8 vic_len, hdmi_3d_len = 0;
  3513. u16 mask;
  3514. u16 structure_all;
  3515. if (len < 8)
  3516. goto out;
  3517. /* no HDMI_Video_Present */
  3518. if (!(db[8] & (1 << 5)))
  3519. goto out;
  3520. /* Latency_Fields_Present */
  3521. if (db[8] & (1 << 7))
  3522. offset += 2;
  3523. /* I_Latency_Fields_Present */
  3524. if (db[8] & (1 << 6))
  3525. offset += 2;
  3526. /* the declared length is not long enough for the 2 first bytes
  3527. * of additional video format capabilities */
  3528. if (len < (8 + offset + 2))
  3529. goto out;
  3530. /* 3D_Present */
  3531. offset++;
  3532. if (db[8 + offset] & (1 << 7)) {
  3533. modes += add_hdmi_mandatory_stereo_modes(connector);
  3534. /* 3D_Multi_present */
  3535. multi_present = (db[8 + offset] & 0x60) >> 5;
  3536. }
  3537. offset++;
  3538. vic_len = db[8 + offset] >> 5;
  3539. hdmi_3d_len = db[8 + offset] & 0x1f;
  3540. for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
  3541. u8 vic;
  3542. vic = db[9 + offset + i];
  3543. modes += add_hdmi_mode(connector, vic);
  3544. }
  3545. offset += 1 + vic_len;
  3546. if (multi_present == 1)
  3547. multi_len = 2;
  3548. else if (multi_present == 2)
  3549. multi_len = 4;
  3550. else
  3551. multi_len = 0;
  3552. if (len < (8 + offset + hdmi_3d_len - 1))
  3553. goto out;
  3554. if (hdmi_3d_len < multi_len)
  3555. goto out;
  3556. if (multi_present == 1 || multi_present == 2) {
  3557. /* 3D_Structure_ALL */
  3558. structure_all = (db[8 + offset] << 8) | db[9 + offset];
  3559. /* check if 3D_MASK is present */
  3560. if (multi_present == 2)
  3561. mask = (db[10 + offset] << 8) | db[11 + offset];
  3562. else
  3563. mask = 0xffff;
  3564. for (i = 0; i < 16; i++) {
  3565. if (mask & (1 << i))
  3566. modes += add_3d_struct_modes(connector,
  3567. structure_all,
  3568. video_db,
  3569. video_len, i);
  3570. }
  3571. }
  3572. offset += multi_len;
  3573. for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
  3574. int vic_index;
  3575. struct drm_display_mode *newmode = NULL;
  3576. unsigned int newflag = 0;
  3577. bool detail_present;
  3578. detail_present = ((db[8 + offset + i] & 0x0f) > 7);
  3579. if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
  3580. break;
  3581. /* 2D_VIC_order_X */
  3582. vic_index = db[8 + offset + i] >> 4;
  3583. /* 3D_Structure_X */
  3584. switch (db[8 + offset + i] & 0x0f) {
  3585. case 0:
  3586. newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
  3587. break;
  3588. case 6:
  3589. newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
  3590. break;
  3591. case 8:
  3592. /* 3D_Detail_X */
  3593. if ((db[9 + offset + i] >> 4) == 1)
  3594. newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
  3595. break;
  3596. }
  3597. if (newflag != 0) {
  3598. newmode = drm_display_mode_from_vic_index(connector,
  3599. video_db,
  3600. video_len,
  3601. vic_index);
  3602. if (newmode) {
  3603. newmode->flags |= newflag;
  3604. drm_mode_probed_add(connector, newmode);
  3605. modes++;
  3606. }
  3607. }
  3608. if (detail_present)
  3609. i++;
  3610. }
  3611. out:
  3612. if (modes > 0)
  3613. info->has_hdmi_infoframe = true;
  3614. return modes;
  3615. }
  3616. static int
  3617. cea_db_payload_len(const u8 *db)
  3618. {
  3619. return db[0] & 0x1f;
  3620. }
  3621. static int
  3622. cea_db_extended_tag(const u8 *db)
  3623. {
  3624. return db[1];
  3625. }
  3626. static int
  3627. cea_db_tag(const u8 *db)
  3628. {
  3629. return db[0] >> 5;
  3630. }
  3631. static int
  3632. cea_revision(const u8 *cea)
  3633. {
  3634. /*
  3635. * FIXME is this correct for the DispID variant?
  3636. * The DispID spec doesn't really specify whether
  3637. * this is the revision of the CEA extension or
  3638. * the DispID CEA data block. And the only value
  3639. * given as an example is 0.
  3640. */
  3641. return cea[1];
  3642. }
  3643. static int
  3644. cea_db_offsets(const u8 *cea, int *start, int *end)
  3645. {
  3646. /* DisplayID CTA extension blocks and top-level CEA EDID
  3647. * block header definitions differ in the following bytes:
  3648. * 1) Byte 2 of the header specifies length differently,
  3649. * 2) Byte 3 is only present in the CEA top level block.
  3650. *
  3651. * The different definitions for byte 2 follow.
  3652. *
  3653. * DisplayID CTA extension block defines byte 2 as:
  3654. * Number of payload bytes
  3655. *
  3656. * CEA EDID block defines byte 2 as:
  3657. * Byte number (decimal) within this block where the 18-byte
  3658. * DTDs begin. If no non-DTD data is present in this extension
  3659. * block, the value should be set to 04h (the byte after next).
  3660. * If set to 00h, there are no DTDs present in this block and
  3661. * no non-DTD data.
  3662. */
  3663. if (cea[0] == DATA_BLOCK_CTA) {
  3664. /*
  3665. * for_each_displayid_db() has already verified
  3666. * that these stay within expected bounds.
  3667. */
  3668. *start = 3;
  3669. *end = *start + cea[2];
  3670. } else if (cea[0] == CEA_EXT) {
  3671. /* Data block offset in CEA extension block */
  3672. *start = 4;
  3673. *end = cea[2];
  3674. if (*end == 0)
  3675. *end = 127;
  3676. if (*end < 4 || *end > 127)
  3677. return -ERANGE;
  3678. } else {
  3679. return -EOPNOTSUPP;
  3680. }
  3681. return 0;
  3682. }
  3683. static bool cea_db_is_hdmi_vsdb(const u8 *db)
  3684. {
  3685. int hdmi_id;
  3686. if (cea_db_tag(db) != VENDOR_BLOCK)
  3687. return false;
  3688. if (cea_db_payload_len(db) < 5)
  3689. return false;
  3690. hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
  3691. return hdmi_id == HDMI_IEEE_OUI;
  3692. }
  3693. static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
  3694. {
  3695. unsigned int oui;
  3696. if (cea_db_tag(db) != VENDOR_BLOCK)
  3697. return false;
  3698. if (cea_db_payload_len(db) < 7)
  3699. return false;
  3700. oui = db[3] << 16 | db[2] << 8 | db[1];
  3701. return oui == HDMI_FORUM_IEEE_OUI;
  3702. }
  3703. static bool cea_db_is_vcdb(const u8 *db)
  3704. {
  3705. if (cea_db_tag(db) != USE_EXTENDED_TAG)
  3706. return false;
  3707. if (cea_db_payload_len(db) != 2)
  3708. return false;
  3709. if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
  3710. return false;
  3711. return true;
  3712. }
  3713. static bool cea_db_is_y420cmdb(const u8 *db)
  3714. {
  3715. if (cea_db_tag(db) != USE_EXTENDED_TAG)
  3716. return false;
  3717. if (!cea_db_payload_len(db))
  3718. return false;
  3719. if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
  3720. return false;
  3721. return true;
  3722. }
  3723. static bool cea_db_is_y420vdb(const u8 *db)
  3724. {
  3725. if (cea_db_tag(db) != USE_EXTENDED_TAG)
  3726. return false;
  3727. if (!cea_db_payload_len(db))
  3728. return false;
  3729. if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
  3730. return false;
  3731. return true;
  3732. }
  3733. #define for_each_cea_db(cea, i, start, end) \
  3734. for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
  3735. static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
  3736. const u8 *db)
  3737. {
  3738. struct drm_display_info *info = &connector->display_info;
  3739. struct drm_hdmi_info *hdmi = &info->hdmi;
  3740. u8 map_len = cea_db_payload_len(db) - 1;
  3741. u8 count;
  3742. u64 map = 0;
  3743. if (map_len == 0) {
  3744. /* All CEA modes support ycbcr420 sampling also.*/
  3745. hdmi->y420_cmdb_map = U64_MAX;
  3746. info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
  3747. return;
  3748. }
  3749. /*
  3750. * This map indicates which of the existing CEA block modes
  3751. * from VDB can support YCBCR420 output too. So if bit=0 is
  3752. * set, first mode from VDB can support YCBCR420 output too.
  3753. * We will parse and keep this map, before parsing VDB itself
  3754. * to avoid going through the same block again and again.
  3755. *
  3756. * Spec is not clear about max possible size of this block.
  3757. * Clamping max bitmap block size at 8 bytes. Every byte can
  3758. * address 8 CEA modes, in this way this map can address
  3759. * 8*8 = first 64 SVDs.
  3760. */
  3761. if (WARN_ON_ONCE(map_len > 8))
  3762. map_len = 8;
  3763. for (count = 0; count < map_len; count++)
  3764. map |= (u64)db[2 + count] << (8 * count);
  3765. if (map)
  3766. info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
  3767. hdmi->y420_cmdb_map = map;
  3768. }
  3769. static int
  3770. add_cea_modes(struct drm_connector *connector, struct edid *edid)
  3771. {
  3772. const u8 *cea = drm_find_cea_extension(edid);
  3773. const u8 *db, *hdmi = NULL, *video = NULL;
  3774. u8 dbl, hdmi_len, video_len = 0;
  3775. int modes = 0;
  3776. if (cea && cea_revision(cea) >= 3) {
  3777. int i, start, end;
  3778. if (cea_db_offsets(cea, &start, &end))
  3779. return 0;
  3780. for_each_cea_db(cea, i, start, end) {
  3781. db = &cea[i];
  3782. dbl = cea_db_payload_len(db);
  3783. if (cea_db_tag(db) == VIDEO_BLOCK) {
  3784. video = db + 1;
  3785. video_len = dbl;
  3786. modes += do_cea_modes(connector, video, dbl);
  3787. } else if (cea_db_is_hdmi_vsdb(db)) {
  3788. hdmi = db;
  3789. hdmi_len = dbl;
  3790. } else if (cea_db_is_y420vdb(db)) {
  3791. const u8 *vdb420 = &db[2];
  3792. /* Add 4:2:0(only) modes present in EDID */
  3793. modes += do_y420vdb_modes(connector,
  3794. vdb420,
  3795. dbl - 1);
  3796. }
  3797. }
  3798. }
  3799. /*
  3800. * We parse the HDMI VSDB after having added the cea modes as we will
  3801. * be patching their flags when the sink supports stereo 3D.
  3802. */
  3803. if (hdmi)
  3804. modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
  3805. video_len);
  3806. return modes;
  3807. }
  3808. static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
  3809. {
  3810. const struct drm_display_mode *cea_mode;
  3811. int clock1, clock2, clock;
  3812. u8 vic;
  3813. const char *type;
  3814. /*
  3815. * allow 5kHz clock difference either way to account for
  3816. * the 10kHz clock resolution limit of detailed timings.
  3817. */
  3818. vic = drm_match_cea_mode_clock_tolerance(mode, 5);
  3819. if (drm_valid_cea_vic(vic)) {
  3820. type = "CEA";
  3821. cea_mode = cea_mode_for_vic(vic);
  3822. clock1 = cea_mode->clock;
  3823. clock2 = cea_mode_alternate_clock(cea_mode);
  3824. } else {
  3825. vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
  3826. if (drm_valid_hdmi_vic(vic)) {
  3827. type = "HDMI";
  3828. cea_mode = &edid_4k_modes[vic];
  3829. clock1 = cea_mode->clock;
  3830. clock2 = hdmi_mode_alternate_clock(cea_mode);
  3831. } else {
  3832. return;
  3833. }
  3834. }
  3835. /* pick whichever is closest */
  3836. if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
  3837. clock = clock1;
  3838. else
  3839. clock = clock2;
  3840. if (mode->clock == clock)
  3841. return;
  3842. DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
  3843. type, vic, mode->clock, clock);
  3844. mode->clock = clock;
  3845. }
  3846. static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
  3847. {
  3848. if (cea_db_tag(db) != USE_EXTENDED_TAG)
  3849. return false;
  3850. if (db[1] != HDR_STATIC_METADATA_BLOCK)
  3851. return false;
  3852. if (cea_db_payload_len(db) < 3)
  3853. return false;
  3854. return true;
  3855. }
  3856. static uint8_t eotf_supported(const u8 *edid_ext)
  3857. {
  3858. return edid_ext[2] &
  3859. (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
  3860. BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
  3861. BIT(HDMI_EOTF_SMPTE_ST2084) |
  3862. BIT(HDMI_EOTF_BT_2100_HLG));
  3863. }
  3864. static uint8_t hdr_metadata_type(const u8 *edid_ext)
  3865. {
  3866. return edid_ext[3] &
  3867. BIT(HDMI_STATIC_METADATA_TYPE1);
  3868. }
  3869. static void
  3870. drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
  3871. {
  3872. u16 len;
  3873. len = cea_db_payload_len(db);
  3874. connector->hdr_sink_metadata.hdmi_type1.eotf =
  3875. eotf_supported(db);
  3876. connector->hdr_sink_metadata.hdmi_type1.metadata_type =
  3877. hdr_metadata_type(db);
  3878. if (len >= 4)
  3879. connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
  3880. if (len >= 5)
  3881. connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
  3882. if (len >= 6)
  3883. connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
  3884. }
  3885. static void
  3886. drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
  3887. {
  3888. u8 len = cea_db_payload_len(db);
  3889. if (len >= 6 && (db[6] & (1 << 7)))
  3890. connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
  3891. if (len >= 8) {
  3892. connector->latency_present[0] = db[8] >> 7;
  3893. connector->latency_present[1] = (db[8] >> 6) & 1;
  3894. }
  3895. if (len >= 9)
  3896. connector->video_latency[0] = db[9];
  3897. if (len >= 10)
  3898. connector->audio_latency[0] = db[10];
  3899. if (len >= 11)
  3900. connector->video_latency[1] = db[11];
  3901. if (len >= 12)
  3902. connector->audio_latency[1] = db[12];
  3903. DRM_DEBUG_KMS("HDMI: latency present %d %d, "
  3904. "video latency %d %d, "
  3905. "audio latency %d %d\n",
  3906. connector->latency_present[0],
  3907. connector->latency_present[1],
  3908. connector->video_latency[0],
  3909. connector->video_latency[1],
  3910. connector->audio_latency[0],
  3911. connector->audio_latency[1]);
  3912. }
  3913. static void
  3914. monitor_name(struct detailed_timing *t, void *data)
  3915. {
  3916. if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
  3917. return;
  3918. *(u8 **)data = t->data.other_data.data.str.str;
  3919. }
  3920. static int get_monitor_name(struct edid *edid, char name[13])
  3921. {
  3922. char *edid_name = NULL;
  3923. int mnl;
  3924. if (!edid || !name)
  3925. return 0;
  3926. drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
  3927. for (mnl = 0; edid_name && mnl < 13; mnl++) {
  3928. if (edid_name[mnl] == 0x0a)
  3929. break;
  3930. name[mnl] = edid_name[mnl];
  3931. }
  3932. return mnl;
  3933. }
  3934. /**
  3935. * drm_edid_get_monitor_name - fetch the monitor name from the edid
  3936. * @edid: monitor EDID information
  3937. * @name: pointer to a character array to hold the name of the monitor
  3938. * @bufsize: The size of the name buffer (should be at least 14 chars.)
  3939. *
  3940. */
  3941. void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
  3942. {
  3943. int name_length;
  3944. char buf[13];
  3945. if (bufsize <= 0)
  3946. return;
  3947. name_length = min(get_monitor_name(edid, buf), bufsize - 1);
  3948. memcpy(name, buf, name_length);
  3949. name[name_length] = '\0';
  3950. }
  3951. EXPORT_SYMBOL(drm_edid_get_monitor_name);
  3952. static void clear_eld(struct drm_connector *connector)
  3953. {
  3954. memset(connector->eld, 0, sizeof(connector->eld));
  3955. connector->latency_present[0] = false;
  3956. connector->latency_present[1] = false;
  3957. connector->video_latency[0] = 0;
  3958. connector->audio_latency[0] = 0;
  3959. connector->video_latency[1] = 0;
  3960. connector->audio_latency[1] = 0;
  3961. }
  3962. /*
  3963. * drm_edid_to_eld - build ELD from EDID
  3964. * @connector: connector corresponding to the HDMI/DP sink
  3965. * @edid: EDID to parse
  3966. *
  3967. * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
  3968. * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
  3969. */
  3970. static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
  3971. {
  3972. uint8_t *eld = connector->eld;
  3973. u8 *cea;
  3974. u8 *db;
  3975. int total_sad_count = 0;
  3976. int mnl;
  3977. int dbl;
  3978. clear_eld(connector);
  3979. if (!edid)
  3980. return;
  3981. cea = drm_find_cea_extension(edid);
  3982. if (!cea) {
  3983. DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
  3984. return;
  3985. }
  3986. mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
  3987. DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
  3988. eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
  3989. eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
  3990. eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
  3991. eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
  3992. eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
  3993. eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
  3994. eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
  3995. if (cea_revision(cea) >= 3) {
  3996. int i, start, end;
  3997. int sad_count;
  3998. if (cea_db_offsets(cea, &start, &end)) {
  3999. start = 0;
  4000. end = 0;
  4001. }
  4002. for_each_cea_db(cea, i, start, end) {
  4003. db = &cea[i];
  4004. dbl = cea_db_payload_len(db);
  4005. switch (cea_db_tag(db)) {
  4006. case AUDIO_BLOCK:
  4007. /* Audio Data Block, contains SADs */
  4008. sad_count = min(dbl / 3, 15 - total_sad_count);
  4009. if (sad_count >= 1)
  4010. memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
  4011. &db[1], sad_count * 3);
  4012. total_sad_count += sad_count;
  4013. break;
  4014. case SPEAKER_BLOCK:
  4015. /* Speaker Allocation Data Block */
  4016. if (dbl >= 1)
  4017. eld[DRM_ELD_SPEAKER] = db[1];
  4018. break;
  4019. case VENDOR_BLOCK:
  4020. /* HDMI Vendor-Specific Data Block */
  4021. if (cea_db_is_hdmi_vsdb(db))
  4022. drm_parse_hdmi_vsdb_audio(connector, db);
  4023. break;
  4024. default:
  4025. break;
  4026. }
  4027. }
  4028. }
  4029. eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
  4030. if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
  4031. connector->connector_type == DRM_MODE_CONNECTOR_eDP)
  4032. eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
  4033. else
  4034. eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
  4035. eld[DRM_ELD_BASELINE_ELD_LEN] =
  4036. DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
  4037. DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
  4038. drm_eld_size(eld), total_sad_count);
  4039. }
  4040. /**
  4041. * drm_edid_to_sad - extracts SADs from EDID
  4042. * @edid: EDID to parse
  4043. * @sads: pointer that will be set to the extracted SADs
  4044. *
  4045. * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
  4046. *
  4047. * Note: The returned pointer needs to be freed using kfree().
  4048. *
  4049. * Return: The number of found SADs or negative number on error.
  4050. */
  4051. int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
  4052. {
  4053. int count = 0;
  4054. int i, start, end, dbl;
  4055. u8 *cea;
  4056. cea = drm_find_cea_extension(edid);
  4057. if (!cea) {
  4058. DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
  4059. return 0;
  4060. }
  4061. if (cea_revision(cea) < 3) {
  4062. DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
  4063. return 0;
  4064. }
  4065. if (cea_db_offsets(cea, &start, &end)) {
  4066. DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
  4067. return -EPROTO;
  4068. }
  4069. for_each_cea_db(cea, i, start, end) {
  4070. u8 *db = &cea[i];
  4071. if (cea_db_tag(db) == AUDIO_BLOCK) {
  4072. int j;
  4073. dbl = cea_db_payload_len(db);
  4074. count = dbl / 3; /* SAD is 3B */
  4075. *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
  4076. if (!*sads)
  4077. return -ENOMEM;
  4078. for (j = 0; j < count; j++) {
  4079. u8 *sad = &db[1 + j * 3];
  4080. (*sads)[j].format = (sad[0] & 0x78) >> 3;
  4081. (*sads)[j].channels = sad[0] & 0x7;
  4082. (*sads)[j].freq = sad[1] & 0x7F;
  4083. (*sads)[j].byte2 = sad[2];
  4084. }
  4085. break;
  4086. }
  4087. }
  4088. return count;
  4089. }
  4090. EXPORT_SYMBOL(drm_edid_to_sad);
  4091. /**
  4092. * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
  4093. * @edid: EDID to parse
  4094. * @sadb: pointer to the speaker block
  4095. *
  4096. * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
  4097. *
  4098. * Note: The returned pointer needs to be freed using kfree().
  4099. *
  4100. * Return: The number of found Speaker Allocation Blocks or negative number on
  4101. * error.
  4102. */
  4103. int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
  4104. {
  4105. int count = 0;
  4106. int i, start, end, dbl;
  4107. const u8 *cea;
  4108. cea = drm_find_cea_extension(edid);
  4109. if (!cea) {
  4110. DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
  4111. return 0;
  4112. }
  4113. if (cea_revision(cea) < 3) {
  4114. DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
  4115. return 0;
  4116. }
  4117. if (cea_db_offsets(cea, &start, &end)) {
  4118. DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
  4119. return -EPROTO;
  4120. }
  4121. for_each_cea_db(cea, i, start, end) {
  4122. const u8 *db = &cea[i];
  4123. if (cea_db_tag(db) == SPEAKER_BLOCK) {
  4124. dbl = cea_db_payload_len(db);
  4125. /* Speaker Allocation Data Block */
  4126. if (dbl == 3) {
  4127. *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
  4128. if (!*sadb)
  4129. return -ENOMEM;
  4130. count = dbl;
  4131. break;
  4132. }
  4133. }
  4134. }
  4135. return count;
  4136. }
  4137. EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
  4138. /**
  4139. * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
  4140. * @connector: connector associated with the HDMI/DP sink
  4141. * @mode: the display mode
  4142. *
  4143. * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
  4144. * the sink doesn't support audio or video.
  4145. */
  4146. int drm_av_sync_delay(struct drm_connector *connector,
  4147. const struct drm_display_mode *mode)
  4148. {
  4149. int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
  4150. int a, v;
  4151. if (!connector->latency_present[0])
  4152. return 0;
  4153. if (!connector->latency_present[1])
  4154. i = 0;
  4155. a = connector->audio_latency[i];
  4156. v = connector->video_latency[i];
  4157. /*
  4158. * HDMI/DP sink doesn't support audio or video?
  4159. */
  4160. if (a == 255 || v == 255)
  4161. return 0;
  4162. /*
  4163. * Convert raw EDID values to millisecond.
  4164. * Treat unknown latency as 0ms.
  4165. */
  4166. if (a)
  4167. a = min(2 * (a - 1), 500);
  4168. if (v)
  4169. v = min(2 * (v - 1), 500);
  4170. return max(v - a, 0);
  4171. }
  4172. EXPORT_SYMBOL(drm_av_sync_delay);
  4173. /**
  4174. * drm_detect_hdmi_monitor - detect whether monitor is HDMI
  4175. * @edid: monitor EDID information
  4176. *
  4177. * Parse the CEA extension according to CEA-861-B.
  4178. *
  4179. * Drivers that have added the modes parsed from EDID to drm_display_info
  4180. * should use &drm_display_info.is_hdmi instead of calling this function.
  4181. *
  4182. * Return: True if the monitor is HDMI, false if not or unknown.
  4183. */
  4184. bool drm_detect_hdmi_monitor(struct edid *edid)
  4185. {
  4186. u8 *edid_ext;
  4187. int i;
  4188. int start_offset, end_offset;
  4189. edid_ext = drm_find_cea_extension(edid);
  4190. if (!edid_ext)
  4191. return false;
  4192. if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
  4193. return false;
  4194. /*
  4195. * Because HDMI identifier is in Vendor Specific Block,
  4196. * search it from all data blocks of CEA extension.
  4197. */
  4198. for_each_cea_db(edid_ext, i, start_offset, end_offset) {
  4199. if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
  4200. return true;
  4201. }
  4202. return false;
  4203. }
  4204. EXPORT_SYMBOL(drm_detect_hdmi_monitor);
  4205. /**
  4206. * drm_detect_monitor_audio - check monitor audio capability
  4207. * @edid: EDID block to scan
  4208. *
  4209. * Monitor should have CEA extension block.
  4210. * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
  4211. * audio' only. If there is any audio extension block and supported
  4212. * audio format, assume at least 'basic audio' support, even if 'basic
  4213. * audio' is not defined in EDID.
  4214. *
  4215. * Return: True if the monitor supports audio, false otherwise.
  4216. */
  4217. bool drm_detect_monitor_audio(struct edid *edid)
  4218. {
  4219. u8 *edid_ext;
  4220. int i, j;
  4221. bool has_audio = false;
  4222. int start_offset, end_offset;
  4223. edid_ext = drm_find_cea_extension(edid);
  4224. if (!edid_ext)
  4225. goto end;
  4226. has_audio = (edid_ext[0] == CEA_EXT &&
  4227. (edid_ext[3] & EDID_BASIC_AUDIO) != 0);
  4228. if (has_audio) {
  4229. DRM_DEBUG_KMS("Monitor has basic audio support\n");
  4230. goto end;
  4231. }
  4232. if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
  4233. goto end;
  4234. for_each_cea_db(edid_ext, i, start_offset, end_offset) {
  4235. if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
  4236. has_audio = true;
  4237. for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
  4238. DRM_DEBUG_KMS("CEA audio format %d\n",
  4239. (edid_ext[i + j] >> 3) & 0xf);
  4240. goto end;
  4241. }
  4242. }
  4243. end:
  4244. return has_audio;
  4245. }
  4246. EXPORT_SYMBOL(drm_detect_monitor_audio);
  4247. /**
  4248. * drm_default_rgb_quant_range - default RGB quantization range
  4249. * @mode: display mode
  4250. *
  4251. * Determine the default RGB quantization range for the mode,
  4252. * as specified in CEA-861.
  4253. *
  4254. * Return: The default RGB quantization range for the mode
  4255. */
  4256. enum hdmi_quantization_range
  4257. drm_default_rgb_quant_range(const struct drm_display_mode *mode)
  4258. {
  4259. /* All CEA modes other than VIC 1 use limited quantization range. */
  4260. return drm_match_cea_mode(mode) > 1 ?
  4261. HDMI_QUANTIZATION_RANGE_LIMITED :
  4262. HDMI_QUANTIZATION_RANGE_FULL;
  4263. }
  4264. EXPORT_SYMBOL(drm_default_rgb_quant_range);
  4265. static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
  4266. {
  4267. struct drm_display_info *info = &connector->display_info;
  4268. DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
  4269. if (db[2] & EDID_CEA_VCDB_QS)
  4270. info->rgb_quant_range_selectable = true;
  4271. }
  4272. static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
  4273. const u8 *db)
  4274. {
  4275. u8 dc_mask;
  4276. struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
  4277. dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
  4278. hdmi->y420_dc_modes = dc_mask;
  4279. }
  4280. static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
  4281. const u8 *hf_vsdb)
  4282. {
  4283. struct drm_display_info *display = &connector->display_info;
  4284. struct drm_hdmi_info *hdmi = &display->hdmi;
  4285. display->has_hdmi_infoframe = true;
  4286. if (hf_vsdb[6] & 0x80) {
  4287. hdmi->scdc.supported = true;
  4288. if (hf_vsdb[6] & 0x40)
  4289. hdmi->scdc.read_request = true;
  4290. }
  4291. /*
  4292. * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
  4293. * And as per the spec, three factors confirm this:
  4294. * * Availability of a HF-VSDB block in EDID (check)
  4295. * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
  4296. * * SCDC support available (let's check)
  4297. * Lets check it out.
  4298. */
  4299. if (hf_vsdb[5]) {
  4300. /* max clock is 5000 KHz times block value */
  4301. u32 max_tmds_clock = hf_vsdb[5] * 5000;
  4302. struct drm_scdc *scdc = &hdmi->scdc;
  4303. if (max_tmds_clock > 340000) {
  4304. display->max_tmds_clock = max_tmds_clock;
  4305. DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
  4306. display->max_tmds_clock);
  4307. }
  4308. if (scdc->supported) {
  4309. scdc->scrambling.supported = true;
  4310. /* Few sinks support scrambling for clocks < 340M */
  4311. if ((hf_vsdb[6] & 0x8))
  4312. scdc->scrambling.low_rates = true;
  4313. }
  4314. }
  4315. drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
  4316. }
  4317. static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
  4318. const u8 *hdmi)
  4319. {
  4320. struct drm_display_info *info = &connector->display_info;
  4321. unsigned int dc_bpc = 0;
  4322. /* HDMI supports at least 8 bpc */
  4323. info->bpc = 8;
  4324. if (cea_db_payload_len(hdmi) < 6)
  4325. return;
  4326. if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
  4327. dc_bpc = 10;
  4328. info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
  4329. DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
  4330. connector->name);
  4331. }
  4332. if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
  4333. dc_bpc = 12;
  4334. info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
  4335. DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
  4336. connector->name);
  4337. }
  4338. if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
  4339. dc_bpc = 16;
  4340. info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
  4341. DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
  4342. connector->name);
  4343. }
  4344. if (dc_bpc == 0) {
  4345. DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
  4346. connector->name);
  4347. return;
  4348. }
  4349. DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
  4350. connector->name, dc_bpc);
  4351. info->bpc = dc_bpc;
  4352. /* YCRCB444 is optional according to spec. */
  4353. if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
  4354. DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
  4355. connector->name);
  4356. }
  4357. /*
  4358. * Spec says that if any deep color mode is supported at all,
  4359. * then deep color 36 bit must be supported.
  4360. */
  4361. if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
  4362. DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
  4363. connector->name);
  4364. }
  4365. }
  4366. static void
  4367. drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
  4368. {
  4369. struct drm_display_info *info = &connector->display_info;
  4370. u8 len = cea_db_payload_len(db);
  4371. info->is_hdmi = true;
  4372. if (len >= 6)
  4373. info->dvi_dual = db[6] & 1;
  4374. if (len >= 7)
  4375. info->max_tmds_clock = db[7] * 5000;
  4376. DRM_DEBUG_KMS("HDMI: DVI dual %d, "
  4377. "max TMDS clock %d kHz\n",
  4378. info->dvi_dual,
  4379. info->max_tmds_clock);
  4380. drm_parse_hdmi_deep_color_info(connector, db);
  4381. }
  4382. static void drm_parse_cea_ext(struct drm_connector *connector,
  4383. const struct edid *edid)
  4384. {
  4385. struct drm_display_info *info = &connector->display_info;
  4386. const u8 *edid_ext;
  4387. int i, start, end;
  4388. edid_ext = drm_find_cea_extension(edid);
  4389. if (!edid_ext)
  4390. return;
  4391. info->cea_rev = edid_ext[1];
  4392. /* The existence of a CEA block should imply RGB support */
  4393. info->color_formats = DRM_COLOR_FORMAT_RGB444;
  4394. if (edid_ext[3] & EDID_CEA_YCRCB444)
  4395. info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
  4396. if (edid_ext[3] & EDID_CEA_YCRCB422)
  4397. info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
  4398. if (cea_db_offsets(edid_ext, &start, &end))
  4399. return;
  4400. for_each_cea_db(edid_ext, i, start, end) {
  4401. const u8 *db = &edid_ext[i];
  4402. if (cea_db_is_hdmi_vsdb(db))
  4403. drm_parse_hdmi_vsdb_video(connector, db);
  4404. if (cea_db_is_hdmi_forum_vsdb(db))
  4405. drm_parse_hdmi_forum_vsdb(connector, db);
  4406. if (cea_db_is_y420cmdb(db))
  4407. drm_parse_y420cmdb_bitmap(connector, db);
  4408. if (cea_db_is_vcdb(db))
  4409. drm_parse_vcdb(connector, db);
  4410. if (cea_db_is_hdmi_hdr_metadata_block(db))
  4411. drm_parse_hdr_metadata_block(connector, db);
  4412. }
  4413. }
  4414. static
  4415. void get_monitor_range(struct detailed_timing *timing,
  4416. void *info_monitor_range)
  4417. {
  4418. struct drm_monitor_range_info *monitor_range = info_monitor_range;
  4419. const struct detailed_non_pixel *data = &timing->data.other_data;
  4420. const struct detailed_data_monitor_range *range = &data->data.range;
  4421. if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
  4422. return;
  4423. /*
  4424. * Check for flag range limits only. If flag == 1 then
  4425. * no additional timing information provided.
  4426. * Default GTF, GTF Secondary curve and CVT are not
  4427. * supported
  4428. */
  4429. if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
  4430. return;
  4431. monitor_range->min_vfreq = range->min_vfreq;
  4432. monitor_range->max_vfreq = range->max_vfreq;
  4433. }
  4434. static
  4435. void drm_get_monitor_range(struct drm_connector *connector,
  4436. const struct edid *edid)
  4437. {
  4438. struct drm_display_info *info = &connector->display_info;
  4439. if (!version_greater(edid, 1, 1))
  4440. return;
  4441. drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
  4442. &info->monitor_range);
  4443. DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
  4444. info->monitor_range.min_vfreq,
  4445. info->monitor_range.max_vfreq);
  4446. }
  4447. /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
  4448. * all of the values which would have been set from EDID
  4449. */
  4450. void
  4451. drm_reset_display_info(struct drm_connector *connector)
  4452. {
  4453. struct drm_display_info *info = &connector->display_info;
  4454. info->width_mm = 0;
  4455. info->height_mm = 0;
  4456. info->bpc = 0;
  4457. info->color_formats = 0;
  4458. info->cea_rev = 0;
  4459. info->max_tmds_clock = 0;
  4460. info->dvi_dual = false;
  4461. info->is_hdmi = false;
  4462. info->has_hdmi_infoframe = false;
  4463. info->rgb_quant_range_selectable = false;
  4464. memset(&info->hdmi, 0, sizeof(info->hdmi));
  4465. info->non_desktop = 0;
  4466. memset(&info->monitor_range, 0, sizeof(info->monitor_range));
  4467. }
  4468. u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
  4469. {
  4470. struct drm_display_info *info = &connector->display_info;
  4471. u32 quirks = edid_get_quirks(edid);
  4472. drm_reset_display_info(connector);
  4473. info->width_mm = edid->width_cm * 10;
  4474. info->height_mm = edid->height_cm * 10;
  4475. info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
  4476. drm_get_monitor_range(connector, edid);
  4477. DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
  4478. if (edid->revision < 3)
  4479. return quirks;
  4480. if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
  4481. return quirks;
  4482. info->color_formats |= DRM_COLOR_FORMAT_RGB444;
  4483. drm_parse_cea_ext(connector, edid);
  4484. /*
  4485. * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
  4486. *
  4487. * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
  4488. * tells us to assume 8 bpc color depth if the EDID doesn't have
  4489. * extensions which tell otherwise.
  4490. */
  4491. if (info->bpc == 0 && edid->revision == 3 &&
  4492. edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
  4493. info->bpc = 8;
  4494. DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
  4495. connector->name, info->bpc);
  4496. }
  4497. /* Only defined for 1.4 with digital displays */
  4498. if (edid->revision < 4)
  4499. return quirks;
  4500. switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
  4501. case DRM_EDID_DIGITAL_DEPTH_6:
  4502. info->bpc = 6;
  4503. break;
  4504. case DRM_EDID_DIGITAL_DEPTH_8:
  4505. info->bpc = 8;
  4506. break;
  4507. case DRM_EDID_DIGITAL_DEPTH_10:
  4508. info->bpc = 10;
  4509. break;
  4510. case DRM_EDID_DIGITAL_DEPTH_12:
  4511. info->bpc = 12;
  4512. break;
  4513. case DRM_EDID_DIGITAL_DEPTH_14:
  4514. info->bpc = 14;
  4515. break;
  4516. case DRM_EDID_DIGITAL_DEPTH_16:
  4517. info->bpc = 16;
  4518. break;
  4519. case DRM_EDID_DIGITAL_DEPTH_UNDEF:
  4520. default:
  4521. info->bpc = 0;
  4522. break;
  4523. }
  4524. DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
  4525. connector->name, info->bpc);
  4526. if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
  4527. info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
  4528. if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
  4529. info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
  4530. return quirks;
  4531. }
  4532. static int validate_displayid(u8 *displayid, int length, int idx)
  4533. {
  4534. int i, dispid_length;
  4535. u8 csum = 0;
  4536. struct displayid_hdr *base;
  4537. base = (struct displayid_hdr *)&displayid[idx];
  4538. DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
  4539. base->rev, base->bytes, base->prod_id, base->ext_count);
  4540. /* +1 for DispID checksum */
  4541. dispid_length = sizeof(*base) + base->bytes + 1;
  4542. if (dispid_length > length - idx)
  4543. return -EINVAL;
  4544. for (i = 0; i < dispid_length; i++)
  4545. csum += displayid[idx + i];
  4546. if (csum) {
  4547. DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
  4548. return -EINVAL;
  4549. }
  4550. return 0;
  4551. }
  4552. static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
  4553. struct displayid_detailed_timings_1 *timings)
  4554. {
  4555. struct drm_display_mode *mode;
  4556. unsigned pixel_clock = (timings->pixel_clock[0] |
  4557. (timings->pixel_clock[1] << 8) |
  4558. (timings->pixel_clock[2] << 16)) + 1;
  4559. unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
  4560. unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
  4561. unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
  4562. unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
  4563. unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
  4564. unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
  4565. unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
  4566. unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
  4567. bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
  4568. bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
  4569. mode = drm_mode_create(dev);
  4570. if (!mode)
  4571. return NULL;
  4572. mode->clock = pixel_clock * 10;
  4573. mode->hdisplay = hactive;
  4574. mode->hsync_start = mode->hdisplay + hsync;
  4575. mode->hsync_end = mode->hsync_start + hsync_width;
  4576. mode->htotal = mode->hdisplay + hblank;
  4577. mode->vdisplay = vactive;
  4578. mode->vsync_start = mode->vdisplay + vsync;
  4579. mode->vsync_end = mode->vsync_start + vsync_width;
  4580. mode->vtotal = mode->vdisplay + vblank;
  4581. mode->flags = 0;
  4582. mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
  4583. mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
  4584. mode->type = DRM_MODE_TYPE_DRIVER;
  4585. if (timings->flags & 0x80)
  4586. mode->type |= DRM_MODE_TYPE_PREFERRED;
  4587. drm_mode_set_name(mode);
  4588. return mode;
  4589. }
  4590. static int add_displayid_detailed_1_modes(struct drm_connector *connector,
  4591. struct displayid_block *block)
  4592. {
  4593. struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
  4594. int i;
  4595. int num_timings;
  4596. struct drm_display_mode *newmode;
  4597. int num_modes = 0;
  4598. /* blocks must be multiple of 20 bytes length */
  4599. if (block->num_bytes % 20)
  4600. return 0;
  4601. num_timings = block->num_bytes / 20;
  4602. for (i = 0; i < num_timings; i++) {
  4603. struct displayid_detailed_timings_1 *timings = &det->timings[i];
  4604. newmode = drm_mode_displayid_detailed(connector->dev, timings);
  4605. if (!newmode)
  4606. continue;
  4607. drm_mode_probed_add(connector, newmode);
  4608. num_modes++;
  4609. }
  4610. return num_modes;
  4611. }
  4612. static int add_displayid_detailed_modes(struct drm_connector *connector,
  4613. struct edid *edid)
  4614. {
  4615. u8 *displayid;
  4616. int length, idx;
  4617. struct displayid_block *block;
  4618. int num_modes = 0;
  4619. int ext_index = 0;
  4620. for (;;) {
  4621. displayid = drm_find_displayid_extension(edid, &length, &idx,
  4622. &ext_index);
  4623. if (!displayid)
  4624. break;
  4625. idx += sizeof(struct displayid_hdr);
  4626. for_each_displayid_db(displayid, block, idx, length) {
  4627. switch (block->tag) {
  4628. case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
  4629. num_modes += add_displayid_detailed_1_modes(connector, block);
  4630. break;
  4631. }
  4632. }
  4633. }
  4634. return num_modes;
  4635. }
  4636. /**
  4637. * drm_add_edid_modes - add modes from EDID data, if available
  4638. * @connector: connector we're probing
  4639. * @edid: EDID data
  4640. *
  4641. * Add the specified modes to the connector's mode list. Also fills out the
  4642. * &drm_display_info structure and ELD in @connector with any information which
  4643. * can be derived from the edid.
  4644. *
  4645. * Return: The number of modes added or 0 if we couldn't find any.
  4646. */
  4647. int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
  4648. {
  4649. int num_modes = 0;
  4650. u32 quirks;
  4651. if (edid == NULL) {
  4652. clear_eld(connector);
  4653. return 0;
  4654. }
  4655. if (!drm_edid_is_valid(edid)) {
  4656. clear_eld(connector);
  4657. drm_warn(connector->dev, "%s: EDID invalid.\n",
  4658. connector->name);
  4659. return 0;
  4660. }
  4661. drm_edid_to_eld(connector, edid);
  4662. /*
  4663. * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
  4664. * To avoid multiple parsing of same block, lets parse that map
  4665. * from sink info, before parsing CEA modes.
  4666. */
  4667. quirks = drm_add_display_info(connector, edid);
  4668. /*
  4669. * EDID spec says modes should be preferred in this order:
  4670. * - preferred detailed mode
  4671. * - other detailed modes from base block
  4672. * - detailed modes from extension blocks
  4673. * - CVT 3-byte code modes
  4674. * - standard timing codes
  4675. * - established timing codes
  4676. * - modes inferred from GTF or CVT range information
  4677. *
  4678. * We get this pretty much right.
  4679. *
  4680. * XXX order for additional mode types in extension blocks?
  4681. */
  4682. num_modes += add_detailed_modes(connector, edid, quirks);
  4683. num_modes += add_cvt_modes(connector, edid);
  4684. num_modes += add_standard_modes(connector, edid);
  4685. num_modes += add_established_modes(connector, edid);
  4686. num_modes += add_cea_modes(connector, edid);
  4687. num_modes += add_alternate_cea_modes(connector, edid);
  4688. num_modes += add_displayid_detailed_modes(connector, edid);
  4689. if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
  4690. num_modes += add_inferred_modes(connector, edid);
  4691. if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
  4692. edid_fixup_preferred(connector, quirks);
  4693. if (quirks & EDID_QUIRK_FORCE_6BPC)
  4694. connector->display_info.bpc = 6;
  4695. if (quirks & EDID_QUIRK_FORCE_8BPC)
  4696. connector->display_info.bpc = 8;
  4697. if (quirks & EDID_QUIRK_FORCE_10BPC)
  4698. connector->display_info.bpc = 10;
  4699. if (quirks & EDID_QUIRK_FORCE_12BPC)
  4700. connector->display_info.bpc = 12;
  4701. return num_modes;
  4702. }
  4703. EXPORT_SYMBOL(drm_add_edid_modes);
  4704. /**
  4705. * drm_add_modes_noedid - add modes for the connectors without EDID
  4706. * @connector: connector we're probing
  4707. * @hdisplay: the horizontal display limit
  4708. * @vdisplay: the vertical display limit
  4709. *
  4710. * Add the specified modes to the connector's mode list. Only when the
  4711. * hdisplay/vdisplay is not beyond the given limit, it will be added.
  4712. *
  4713. * Return: The number of modes added or 0 if we couldn't find any.
  4714. */
  4715. int drm_add_modes_noedid(struct drm_connector *connector,
  4716. int hdisplay, int vdisplay)
  4717. {
  4718. int i, count, num_modes = 0;
  4719. struct drm_display_mode *mode;
  4720. struct drm_device *dev = connector->dev;
  4721. count = ARRAY_SIZE(drm_dmt_modes);
  4722. if (hdisplay < 0)
  4723. hdisplay = 0;
  4724. if (vdisplay < 0)
  4725. vdisplay = 0;
  4726. for (i = 0; i < count; i++) {
  4727. const struct drm_display_mode *ptr = &drm_dmt_modes[i];
  4728. if (hdisplay && vdisplay) {
  4729. /*
  4730. * Only when two are valid, they will be used to check
  4731. * whether the mode should be added to the mode list of
  4732. * the connector.
  4733. */
  4734. if (ptr->hdisplay > hdisplay ||
  4735. ptr->vdisplay > vdisplay)
  4736. continue;
  4737. }
  4738. if (drm_mode_vrefresh(ptr) > 61)
  4739. continue;
  4740. mode = drm_mode_duplicate(dev, ptr);
  4741. if (mode) {
  4742. drm_mode_probed_add(connector, mode);
  4743. num_modes++;
  4744. }
  4745. }
  4746. return num_modes;
  4747. }
  4748. EXPORT_SYMBOL(drm_add_modes_noedid);
  4749. /**
  4750. * drm_set_preferred_mode - Sets the preferred mode of a connector
  4751. * @connector: connector whose mode list should be processed
  4752. * @hpref: horizontal resolution of preferred mode
  4753. * @vpref: vertical resolution of preferred mode
  4754. *
  4755. * Marks a mode as preferred if it matches the resolution specified by @hpref
  4756. * and @vpref.
  4757. */
  4758. void drm_set_preferred_mode(struct drm_connector *connector,
  4759. int hpref, int vpref)
  4760. {
  4761. struct drm_display_mode *mode;
  4762. list_for_each_entry(mode, &connector->probed_modes, head) {
  4763. if (mode->hdisplay == hpref &&
  4764. mode->vdisplay == vpref)
  4765. mode->type |= DRM_MODE_TYPE_PREFERRED;
  4766. }
  4767. }
  4768. EXPORT_SYMBOL(drm_set_preferred_mode);
  4769. static bool is_hdmi2_sink(const struct drm_connector *connector)
  4770. {
  4771. /*
  4772. * FIXME: sil-sii8620 doesn't have a connector around when
  4773. * we need one, so we have to be prepared for a NULL connector.
  4774. */
  4775. if (!connector)
  4776. return true;
  4777. return connector->display_info.hdmi.scdc.supported ||
  4778. connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
  4779. }
  4780. static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
  4781. {
  4782. return sink_eotf & BIT(output_eotf);
  4783. }
  4784. /**
  4785. * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
  4786. * HDR metadata from userspace
  4787. * @frame: HDMI DRM infoframe
  4788. * @conn_state: Connector state containing HDR metadata
  4789. *
  4790. * Return: 0 on success or a negative error code on failure.
  4791. */
  4792. int
  4793. drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
  4794. const struct drm_connector_state *conn_state)
  4795. {
  4796. struct drm_connector *connector;
  4797. struct hdr_output_metadata *hdr_metadata;
  4798. int err;
  4799. if (!frame || !conn_state)
  4800. return -EINVAL;
  4801. connector = conn_state->connector;
  4802. if (!conn_state->hdr_output_metadata)
  4803. return -EINVAL;
  4804. hdr_metadata = conn_state->hdr_output_metadata->data;
  4805. if (!hdr_metadata || !connector)
  4806. return -EINVAL;
  4807. /* Sink EOTF is Bit map while infoframe is absolute values */
  4808. if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
  4809. connector->hdr_sink_metadata.hdmi_type1.eotf)) {
  4810. DRM_DEBUG_KMS("EOTF Not Supported\n");
  4811. return -EINVAL;
  4812. }
  4813. err = hdmi_drm_infoframe_init(frame);
  4814. if (err < 0)
  4815. return err;
  4816. frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
  4817. frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
  4818. BUILD_BUG_ON(sizeof(frame->display_primaries) !=
  4819. sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
  4820. BUILD_BUG_ON(sizeof(frame->white_point) !=
  4821. sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
  4822. memcpy(&frame->display_primaries,
  4823. &hdr_metadata->hdmi_metadata_type1.display_primaries,
  4824. sizeof(frame->display_primaries));
  4825. memcpy(&frame->white_point,
  4826. &hdr_metadata->hdmi_metadata_type1.white_point,
  4827. sizeof(frame->white_point));
  4828. frame->max_display_mastering_luminance =
  4829. hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
  4830. frame->min_display_mastering_luminance =
  4831. hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
  4832. frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
  4833. frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
  4834. return 0;
  4835. }
  4836. EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
  4837. static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
  4838. const struct drm_display_mode *mode)
  4839. {
  4840. bool has_hdmi_infoframe = connector ?
  4841. connector->display_info.has_hdmi_infoframe : false;
  4842. if (!has_hdmi_infoframe)
  4843. return 0;
  4844. /* No HDMI VIC when signalling 3D video format */
  4845. if (mode->flags & DRM_MODE_FLAG_3D_MASK)
  4846. return 0;
  4847. return drm_match_hdmi_mode(mode);
  4848. }
  4849. static u8 drm_mode_cea_vic(const struct drm_connector *connector,
  4850. const struct drm_display_mode *mode)
  4851. {
  4852. u8 vic;
  4853. /*
  4854. * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
  4855. * we should send its VIC in vendor infoframes, else send the
  4856. * VIC in AVI infoframes. Lets check if this mode is present in
  4857. * HDMI 1.4b 4K modes
  4858. */
  4859. if (drm_mode_hdmi_vic(connector, mode))
  4860. return 0;
  4861. vic = drm_match_cea_mode(mode);
  4862. /*
  4863. * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
  4864. * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
  4865. * have to make sure we dont break HDMI 1.4 sinks.
  4866. */
  4867. if (!is_hdmi2_sink(connector) && vic > 64)
  4868. return 0;
  4869. return vic;
  4870. }
  4871. /**
  4872. * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
  4873. * data from a DRM display mode
  4874. * @frame: HDMI AVI infoframe
  4875. * @connector: the connector
  4876. * @mode: DRM display mode
  4877. *
  4878. * Return: 0 on success or a negative error code on failure.
  4879. */
  4880. int
  4881. drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
  4882. const struct drm_connector *connector,
  4883. const struct drm_display_mode *mode)
  4884. {
  4885. enum hdmi_picture_aspect picture_aspect;
  4886. u8 vic, hdmi_vic;
  4887. if (!frame || !mode)
  4888. return -EINVAL;
  4889. hdmi_avi_infoframe_init(frame);
  4890. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  4891. frame->pixel_repeat = 1;
  4892. vic = drm_mode_cea_vic(connector, mode);
  4893. hdmi_vic = drm_mode_hdmi_vic(connector, mode);
  4894. frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
  4895. /*
  4896. * As some drivers don't support atomic, we can't use connector state.
  4897. * So just initialize the frame with default values, just the same way
  4898. * as it's done with other properties here.
  4899. */
  4900. frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
  4901. frame->itc = 0;
  4902. /*
  4903. * Populate picture aspect ratio from either
  4904. * user input (if specified) or from the CEA/HDMI mode lists.
  4905. */
  4906. picture_aspect = mode->picture_aspect_ratio;
  4907. if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
  4908. if (vic)
  4909. picture_aspect = drm_get_cea_aspect_ratio(vic);
  4910. else if (hdmi_vic)
  4911. picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
  4912. }
  4913. /*
  4914. * The infoframe can't convey anything but none, 4:3
  4915. * and 16:9, so if the user has asked for anything else
  4916. * we can only satisfy it by specifying the right VIC.
  4917. */
  4918. if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
  4919. if (vic) {
  4920. if (picture_aspect != drm_get_cea_aspect_ratio(vic))
  4921. return -EINVAL;
  4922. } else if (hdmi_vic) {
  4923. if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
  4924. return -EINVAL;
  4925. } else {
  4926. return -EINVAL;
  4927. }
  4928. picture_aspect = HDMI_PICTURE_ASPECT_NONE;
  4929. }
  4930. frame->video_code = vic;
  4931. frame->picture_aspect = picture_aspect;
  4932. frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
  4933. frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
  4934. return 0;
  4935. }
  4936. EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
  4937. /* HDMI Colorspace Spec Definitions */
  4938. #define FULL_COLORIMETRY_MASK 0x1FF
  4939. #define NORMAL_COLORIMETRY_MASK 0x3
  4940. #define EXTENDED_COLORIMETRY_MASK 0x7
  4941. #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
  4942. #define C(x) ((x) << 0)
  4943. #define EC(x) ((x) << 2)
  4944. #define ACE(x) ((x) << 5)
  4945. #define HDMI_COLORIMETRY_NO_DATA 0x0
  4946. #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
  4947. #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
  4948. #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
  4949. #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
  4950. #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
  4951. #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
  4952. #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
  4953. #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
  4954. #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
  4955. #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
  4956. #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
  4957. #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
  4958. static const u32 hdmi_colorimetry_val[] = {
  4959. [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
  4960. [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
  4961. [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
  4962. [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
  4963. [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
  4964. [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
  4965. [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
  4966. [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
  4967. [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
  4968. [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
  4969. [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
  4970. };
  4971. #undef C
  4972. #undef EC
  4973. #undef ACE
  4974. /**
  4975. * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
  4976. * colorspace information
  4977. * @frame: HDMI AVI infoframe
  4978. * @conn_state: connector state
  4979. */
  4980. void
  4981. drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
  4982. const struct drm_connector_state *conn_state)
  4983. {
  4984. u32 colorimetry_val;
  4985. u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
  4986. if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
  4987. colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
  4988. else
  4989. colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
  4990. frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
  4991. /*
  4992. * ToDo: Extend it for ACE formats as well. Modify the infoframe
  4993. * structure and extend it in drivers/video/hdmi
  4994. */
  4995. frame->extended_colorimetry = (colorimetry_val >> 2) &
  4996. EXTENDED_COLORIMETRY_MASK;
  4997. }
  4998. EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
  4999. /**
  5000. * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
  5001. * quantization range information
  5002. * @frame: HDMI AVI infoframe
  5003. * @connector: the connector
  5004. * @mode: DRM display mode
  5005. * @rgb_quant_range: RGB quantization range (Q)
  5006. */
  5007. void
  5008. drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
  5009. const struct drm_connector *connector,
  5010. const struct drm_display_mode *mode,
  5011. enum hdmi_quantization_range rgb_quant_range)
  5012. {
  5013. const struct drm_display_info *info = &connector->display_info;
  5014. /*
  5015. * CEA-861:
  5016. * "A Source shall not send a non-zero Q value that does not correspond
  5017. * to the default RGB Quantization Range for the transmitted Picture
  5018. * unless the Sink indicates support for the Q bit in a Video
  5019. * Capabilities Data Block."
  5020. *
  5021. * HDMI 2.0 recommends sending non-zero Q when it does match the
  5022. * default RGB quantization range for the mode, even when QS=0.
  5023. */
  5024. if (info->rgb_quant_range_selectable ||
  5025. rgb_quant_range == drm_default_rgb_quant_range(mode))
  5026. frame->quantization_range = rgb_quant_range;
  5027. else
  5028. frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
  5029. /*
  5030. * CEA-861-F:
  5031. * "When transmitting any RGB colorimetry, the Source should set the
  5032. * YQ-field to match the RGB Quantization Range being transmitted
  5033. * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
  5034. * set YQ=1) and the Sink shall ignore the YQ-field."
  5035. *
  5036. * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
  5037. * by non-zero YQ when receiving RGB. There doesn't seem to be any
  5038. * good way to tell which version of CEA-861 the sink supports, so
  5039. * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
  5040. * on on CEA-861-F.
  5041. */
  5042. if (!is_hdmi2_sink(connector) ||
  5043. rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
  5044. frame->ycc_quantization_range =
  5045. HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
  5046. else
  5047. frame->ycc_quantization_range =
  5048. HDMI_YCC_QUANTIZATION_RANGE_FULL;
  5049. }
  5050. EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
  5051. /**
  5052. * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
  5053. * bar information
  5054. * @frame: HDMI AVI infoframe
  5055. * @conn_state: connector state
  5056. */
  5057. void
  5058. drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
  5059. const struct drm_connector_state *conn_state)
  5060. {
  5061. frame->right_bar = conn_state->tv.margins.right;
  5062. frame->left_bar = conn_state->tv.margins.left;
  5063. frame->top_bar = conn_state->tv.margins.top;
  5064. frame->bottom_bar = conn_state->tv.margins.bottom;
  5065. }
  5066. EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
  5067. static enum hdmi_3d_structure
  5068. s3d_structure_from_display_mode(const struct drm_display_mode *mode)
  5069. {
  5070. u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
  5071. switch (layout) {
  5072. case DRM_MODE_FLAG_3D_FRAME_PACKING:
  5073. return HDMI_3D_STRUCTURE_FRAME_PACKING;
  5074. case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
  5075. return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
  5076. case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
  5077. return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
  5078. case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
  5079. return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
  5080. case DRM_MODE_FLAG_3D_L_DEPTH:
  5081. return HDMI_3D_STRUCTURE_L_DEPTH;
  5082. case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
  5083. return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
  5084. case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
  5085. return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
  5086. case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
  5087. return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
  5088. default:
  5089. return HDMI_3D_STRUCTURE_INVALID;
  5090. }
  5091. }
  5092. /**
  5093. * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
  5094. * data from a DRM display mode
  5095. * @frame: HDMI vendor infoframe
  5096. * @connector: the connector
  5097. * @mode: DRM display mode
  5098. *
  5099. * Note that there's is a need to send HDMI vendor infoframes only when using a
  5100. * 4k or stereoscopic 3D mode. So when giving any other mode as input this
  5101. * function will return -EINVAL, error that can be safely ignored.
  5102. *
  5103. * Return: 0 on success or a negative error code on failure.
  5104. */
  5105. int
  5106. drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
  5107. const struct drm_connector *connector,
  5108. const struct drm_display_mode *mode)
  5109. {
  5110. /*
  5111. * FIXME: sil-sii8620 doesn't have a connector around when
  5112. * we need one, so we have to be prepared for a NULL connector.
  5113. */
  5114. bool has_hdmi_infoframe = connector ?
  5115. connector->display_info.has_hdmi_infoframe : false;
  5116. int err;
  5117. if (!frame || !mode)
  5118. return -EINVAL;
  5119. if (!has_hdmi_infoframe)
  5120. return -EINVAL;
  5121. err = hdmi_vendor_infoframe_init(frame);
  5122. if (err < 0)
  5123. return err;
  5124. /*
  5125. * Even if it's not absolutely necessary to send the infoframe
  5126. * (ie.vic==0 and s3d_struct==0) we will still send it if we
  5127. * know that the sink can handle it. This is based on a
  5128. * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
  5129. * have trouble realizing that they shuld switch from 3D to 2D
  5130. * mode if the source simply stops sending the infoframe when
  5131. * it wants to switch from 3D to 2D.
  5132. */
  5133. frame->vic = drm_mode_hdmi_vic(connector, mode);
  5134. frame->s3d_struct = s3d_structure_from_display_mode(mode);
  5135. return 0;
  5136. }
  5137. EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
  5138. static void drm_parse_tiled_block(struct drm_connector *connector,
  5139. const struct displayid_block *block)
  5140. {
  5141. const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
  5142. u16 w, h;
  5143. u8 tile_v_loc, tile_h_loc;
  5144. u8 num_v_tile, num_h_tile;
  5145. struct drm_tile_group *tg;
  5146. w = tile->tile_size[0] | tile->tile_size[1] << 8;
  5147. h = tile->tile_size[2] | tile->tile_size[3] << 8;
  5148. num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
  5149. num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
  5150. tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
  5151. tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
  5152. connector->has_tile = true;
  5153. if (tile->tile_cap & 0x80)
  5154. connector->tile_is_single_monitor = true;
  5155. connector->num_h_tile = num_h_tile + 1;
  5156. connector->num_v_tile = num_v_tile + 1;
  5157. connector->tile_h_loc = tile_h_loc;
  5158. connector->tile_v_loc = tile_v_loc;
  5159. connector->tile_h_size = w + 1;
  5160. connector->tile_v_size = h + 1;
  5161. DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
  5162. DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
  5163. DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
  5164. num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
  5165. DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
  5166. tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
  5167. if (!tg)
  5168. tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
  5169. if (!tg)
  5170. return;
  5171. if (connector->tile_group != tg) {
  5172. /* if we haven't got a pointer,
  5173. take the reference, drop ref to old tile group */
  5174. if (connector->tile_group)
  5175. drm_mode_put_tile_group(connector->dev, connector->tile_group);
  5176. connector->tile_group = tg;
  5177. } else {
  5178. /* if same tile group, then release the ref we just took. */
  5179. drm_mode_put_tile_group(connector->dev, tg);
  5180. }
  5181. }
  5182. static void drm_displayid_parse_tiled(struct drm_connector *connector,
  5183. const u8 *displayid, int length, int idx)
  5184. {
  5185. const struct displayid_block *block;
  5186. idx += sizeof(struct displayid_hdr);
  5187. for_each_displayid_db(displayid, block, idx, length) {
  5188. DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
  5189. block->tag, block->rev, block->num_bytes);
  5190. switch (block->tag) {
  5191. case DATA_BLOCK_TILED_DISPLAY:
  5192. drm_parse_tiled_block(connector, block);
  5193. break;
  5194. default:
  5195. DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
  5196. break;
  5197. }
  5198. }
  5199. }
  5200. void drm_update_tile_info(struct drm_connector *connector,
  5201. const struct edid *edid)
  5202. {
  5203. const void *displayid = NULL;
  5204. int ext_index = 0;
  5205. int length, idx;
  5206. connector->has_tile = false;
  5207. for (;;) {
  5208. displayid = drm_find_displayid_extension(edid, &length, &idx,
  5209. &ext_index);
  5210. if (!displayid)
  5211. break;
  5212. drm_displayid_parse_tiled(connector, displayid, length, idx);
  5213. }
  5214. if (!connector->has_tile && connector->tile_group) {
  5215. drm_mode_put_tile_group(connector->dev, connector->tile_group);
  5216. connector->tile_group = NULL;
  5217. }
  5218. }