drm_dsc.c 12 KB

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  1. // SPDX-License-Identifier: MIT
  2. /*
  3. * Copyright © 2018 Intel Corp
  4. *
  5. * Author:
  6. * Manasi Navare <manasi.d.navare@intel.com>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/init.h>
  11. #include <linux/errno.h>
  12. #include <linux/byteorder/generic.h>
  13. #include <drm/drm_print.h>
  14. #include <drm/drm_dp_helper.h>
  15. #include <drm/drm_dsc.h>
  16. /**
  17. * DOC: dsc helpers
  18. *
  19. * VESA specification for DP 1.4 adds a new feature called Display Stream
  20. * Compression (DSC) used to compress the pixel bits before sending it on
  21. * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
  22. * display interfaces can support high resolutions at higher frames rates uisng
  23. * the maximum available link capacity of these interfaces.
  24. *
  25. * These functions contain some common logic and helpers to deal with VESA
  26. * Display Stream Compression standard required for DSC on Display Port/eDP or
  27. * MIPI display interfaces.
  28. */
  29. /**
  30. * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
  31. * for DisplayPort as per the DP 1.4 spec.
  32. * @pps_header: Secondary data packet header for DSC Picture
  33. * Parameter Set as defined in &struct dp_sdp_header
  34. *
  35. * DP 1.4 spec defines the secondary data packet for sending the
  36. * picture parameter infoframes from the source to the sink.
  37. * This function populates the SDP header defined in
  38. * &struct dp_sdp_header.
  39. */
  40. void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header)
  41. {
  42. memset(pps_header, 0, sizeof(*pps_header));
  43. pps_header->HB1 = DP_SDP_PPS;
  44. pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
  45. }
  46. EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
  47. /**
  48. * drm_dsc_pps_payload_pack() - Populates the DSC PPS
  49. *
  50. * @pps_payload:
  51. * Bitwise struct for DSC Picture Parameter Set. This is defined
  52. * by &struct drm_dsc_picture_parameter_set
  53. * @dsc_cfg:
  54. * DSC Configuration data filled by driver as defined by
  55. * &struct drm_dsc_config
  56. *
  57. * DSC source device sends a picture parameter set (PPS) containing the
  58. * information required by the sink to decode the compressed frame. Driver
  59. * populates the DSC PPS struct using the DSC configuration parameters in
  60. * the order expected by the DSC Display Sink device. For the DSC, the sink
  61. * device expects the PPS payload in big endian format for fields
  62. * that span more than 1 byte.
  63. */
  64. void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
  65. const struct drm_dsc_config *dsc_cfg)
  66. {
  67. int i;
  68. /* Protect against someone accidently changing struct size */
  69. BUILD_BUG_ON(sizeof(*pps_payload) !=
  70. DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
  71. memset(pps_payload, 0, sizeof(*pps_payload));
  72. /* PPS 0 */
  73. pps_payload->dsc_version =
  74. dsc_cfg->dsc_version_minor |
  75. dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
  76. /* PPS 1, 2 is 0 */
  77. /* PPS 3 */
  78. pps_payload->pps_3 =
  79. dsc_cfg->line_buf_depth |
  80. dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
  81. /* PPS 4 */
  82. pps_payload->pps_4 =
  83. ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
  84. DSC_PPS_MSB_SHIFT) |
  85. dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
  86. dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
  87. dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
  88. dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
  89. /* PPS 5 */
  90. pps_payload->bits_per_pixel_low =
  91. (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
  92. /*
  93. * The DSC panel expects the PPS packet to have big endian format
  94. * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
  95. * to big endian format. If format is little endian, it will swap
  96. * bytes to convert to Big endian else keep it unchanged.
  97. */
  98. /* PPS 6, 7 */
  99. pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
  100. /* PPS 8, 9 */
  101. pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
  102. /* PPS 10, 11 */
  103. pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
  104. /* PPS 12, 13 */
  105. pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
  106. /* PPS 14, 15 */
  107. pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
  108. /* PPS 16 */
  109. pps_payload->initial_xmit_delay_high =
  110. ((dsc_cfg->initial_xmit_delay &
  111. DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
  112. DSC_PPS_MSB_SHIFT);
  113. /* PPS 17 */
  114. pps_payload->initial_xmit_delay_low =
  115. (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
  116. /* PPS 18, 19 */
  117. pps_payload->initial_dec_delay =
  118. cpu_to_be16(dsc_cfg->initial_dec_delay);
  119. /* PPS 20 is 0 */
  120. /* PPS 21 */
  121. pps_payload->initial_scale_value =
  122. dsc_cfg->initial_scale_value;
  123. /* PPS 22, 23 */
  124. pps_payload->scale_increment_interval =
  125. cpu_to_be16(dsc_cfg->scale_increment_interval);
  126. /* PPS 24 */
  127. pps_payload->scale_decrement_interval_high =
  128. ((dsc_cfg->scale_decrement_interval &
  129. DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
  130. DSC_PPS_MSB_SHIFT);
  131. /* PPS 25 */
  132. pps_payload->scale_decrement_interval_low =
  133. (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
  134. /* PPS 26[7:0], PPS 27[7:5] RESERVED */
  135. /* PPS 27 */
  136. pps_payload->first_line_bpg_offset =
  137. dsc_cfg->first_line_bpg_offset;
  138. /* PPS 28, 29 */
  139. pps_payload->nfl_bpg_offset =
  140. cpu_to_be16(dsc_cfg->nfl_bpg_offset);
  141. /* PPS 30, 31 */
  142. pps_payload->slice_bpg_offset =
  143. cpu_to_be16(dsc_cfg->slice_bpg_offset);
  144. /* PPS 32, 33 */
  145. pps_payload->initial_offset =
  146. cpu_to_be16(dsc_cfg->initial_offset);
  147. /* PPS 34, 35 */
  148. pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
  149. /* PPS 36 */
  150. pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
  151. /* PPS 37 */
  152. pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
  153. /* PPS 38, 39 */
  154. pps_payload->rc_model_size =
  155. cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
  156. /* PPS 40 */
  157. pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
  158. /* PPS 41 */
  159. pps_payload->rc_quant_incr_limit0 =
  160. dsc_cfg->rc_quant_incr_limit0;
  161. /* PPS 42 */
  162. pps_payload->rc_quant_incr_limit1 =
  163. dsc_cfg->rc_quant_incr_limit1;
  164. /* PPS 43 */
  165. pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
  166. DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
  167. /* PPS 44 - 57 */
  168. for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
  169. pps_payload->rc_buf_thresh[i] =
  170. dsc_cfg->rc_buf_thresh[i];
  171. /* PPS 58 - 87 */
  172. /*
  173. * For DSC sink programming the RC Range parameter fields
  174. * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
  175. */
  176. for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
  177. pps_payload->rc_range_parameters[i] =
  178. cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp <<
  179. DSC_PPS_RC_RANGE_MINQP_SHIFT) |
  180. (dsc_cfg->rc_range_params[i].range_max_qp <<
  181. DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
  182. (dsc_cfg->rc_range_params[i].range_bpg_offset));
  183. }
  184. /* PPS 88 */
  185. pps_payload->native_422_420 = dsc_cfg->native_422 |
  186. dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
  187. /* PPS 89 */
  188. pps_payload->second_line_bpg_offset =
  189. dsc_cfg->second_line_bpg_offset;
  190. /* PPS 90, 91 */
  191. pps_payload->nsl_bpg_offset =
  192. cpu_to_be16(dsc_cfg->nsl_bpg_offset);
  193. /* PPS 92, 93 */
  194. pps_payload->second_line_offset_adj =
  195. cpu_to_be16(dsc_cfg->second_line_offset_adj);
  196. /* PPS 94 - 127 are O */
  197. }
  198. EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
  199. /**
  200. * drm_dsc_compute_rc_parameters() - Write rate control
  201. * parameters to the dsc configuration defined in
  202. * &struct drm_dsc_config in accordance with the DSC 1.2
  203. * specification. Some configuration fields must be present
  204. * beforehand.
  205. *
  206. * @vdsc_cfg:
  207. * DSC Configuration data partially filled by driver
  208. */
  209. int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
  210. {
  211. unsigned long groups_per_line = 0;
  212. unsigned long groups_total = 0;
  213. unsigned long num_extra_mux_bits = 0;
  214. unsigned long slice_bits = 0;
  215. unsigned long hrd_delay = 0;
  216. unsigned long final_scale = 0;
  217. unsigned long rbs_min = 0;
  218. if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
  219. /* Number of groups used to code each line of a slice */
  220. groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
  221. DSC_RC_PIXELS_PER_GROUP);
  222. /* chunksize in Bytes */
  223. vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
  224. vdsc_cfg->bits_per_pixel,
  225. (8 * 16));
  226. } else {
  227. /* Number of groups used to code each line of a slice */
  228. groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
  229. DSC_RC_PIXELS_PER_GROUP);
  230. /* chunksize in Bytes */
  231. vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
  232. vdsc_cfg->bits_per_pixel,
  233. (8 * 16));
  234. }
  235. if (vdsc_cfg->convert_rgb)
  236. num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
  237. (4 * vdsc_cfg->bits_per_component + 4)
  238. - 2);
  239. else if (vdsc_cfg->native_422)
  240. num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
  241. (4 * vdsc_cfg->bits_per_component + 4) +
  242. 3 * (4 * vdsc_cfg->bits_per_component) - 2;
  243. else
  244. num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
  245. (4 * vdsc_cfg->bits_per_component + 4) +
  246. 2 * (4 * vdsc_cfg->bits_per_component) - 2;
  247. /* Number of bits in one Slice */
  248. slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
  249. while ((num_extra_mux_bits > 0) &&
  250. ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
  251. num_extra_mux_bits--;
  252. if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
  253. vdsc_cfg->initial_scale_value = groups_per_line + 8;
  254. /* scale_decrement_interval calculation according to DSC spec 1.11 */
  255. if (vdsc_cfg->initial_scale_value > 8)
  256. vdsc_cfg->scale_decrement_interval = groups_per_line /
  257. (vdsc_cfg->initial_scale_value - 8);
  258. else
  259. vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
  260. vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
  261. (vdsc_cfg->initial_xmit_delay *
  262. vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
  263. if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
  264. DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
  265. return -ERANGE;
  266. }
  267. final_scale = (vdsc_cfg->rc_model_size * 8) /
  268. (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
  269. if (vdsc_cfg->slice_height > 1)
  270. /*
  271. * NflBpgOffset is 16 bit value with 11 fractional bits
  272. * hence we multiply by 2^11 for preserving the
  273. * fractional part
  274. */
  275. vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
  276. (vdsc_cfg->slice_height - 1));
  277. else
  278. vdsc_cfg->nfl_bpg_offset = 0;
  279. /* Number of groups used to code the entire slice */
  280. groups_total = groups_per_line * vdsc_cfg->slice_height;
  281. /* slice_bpg_offset is 16 bit value with 11 fractional bits */
  282. vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
  283. vdsc_cfg->initial_offset +
  284. num_extra_mux_bits) << 11),
  285. groups_total);
  286. if (final_scale > 9) {
  287. /*
  288. * ScaleIncrementInterval =
  289. * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
  290. * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
  291. * we need divide by 2^11 from pstDscCfg values
  292. */
  293. vdsc_cfg->scale_increment_interval =
  294. (vdsc_cfg->final_offset * (1 << 11)) /
  295. ((vdsc_cfg->nfl_bpg_offset +
  296. vdsc_cfg->slice_bpg_offset) *
  297. (final_scale - 9));
  298. } else {
  299. /*
  300. * If finalScaleValue is less than or equal to 9, a value of 0 should
  301. * be used to disable the scale increment at the end of the slice
  302. */
  303. vdsc_cfg->scale_increment_interval = 0;
  304. }
  305. /*
  306. * DSC spec mentions that bits_per_pixel specifies the target
  307. * bits/pixel (bpp) rate that is used by the encoder,
  308. * in steps of 1/16 of a bit per pixel
  309. */
  310. rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
  311. DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
  312. vdsc_cfg->bits_per_pixel, 16) +
  313. groups_per_line * vdsc_cfg->first_line_bpg_offset;
  314. hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
  315. vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
  316. vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
  317. return 0;
  318. }
  319. EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);