tc358775.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * TC358775 DSI to LVDS bridge driver
  4. *
  5. * Copyright (C) 2020 SMART Wireless Computing
  6. * Author: Vinay Simha BN <simhavcs@gmail.com>
  7. *
  8. */
  9. /* #define DEBUG */
  10. #include <linux/bitfield.h>
  11. #include <linux/clk.h>
  12. #include <linux/device.h>
  13. #include <linux/gpio/consumer.h>
  14. #include <linux/i2c.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/slab.h>
  19. #include <asm/unaligned.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_bridge.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_dp_helper.h>
  24. #include <drm/drm_mipi_dsi.h>
  25. #include <drm/drm_of.h>
  26. #include <drm/drm_panel.h>
  27. #include <drm/drm_probe_helper.h>
  28. #define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val)
  29. /* Registers */
  30. /* DSI D-PHY Layer Registers */
  31. #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
  32. #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
  33. #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
  34. #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
  35. #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
  36. #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
  37. #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
  38. #define CLW_CNTRL 0x0040 /* Clock Lane Control */
  39. #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */
  40. #define D1W_CNTRL 0x0048 /* Data Lane 1 Control */
  41. #define D2W_CNTRL 0x004C /* Data Lane 2 Control */
  42. #define D3W_CNTRL 0x0050 /* Data Lane 3 Control */
  43. #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
  44. /* DSI PPI Layer Registers */
  45. #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
  46. #define PPI_START_FUNCTION 1
  47. #define PPI_BUSYPPI 0x0108
  48. #define PPI_LINEINITCNT 0x0110 /* Line Initialization Wait Counter */
  49. #define PPI_LPTXTIMECNT 0x0114
  50. #define PPI_LANEENABLE 0x0134 /* Enables each lane at the PPI layer. */
  51. #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
  52. /* Analog timer function enable */
  53. #define PPI_CLS_ATMR 0x0140 /* Delay for Clock Lane in LPRX */
  54. #define PPI_D0S_ATMR 0x0144 /* Delay for Data Lane 0 in LPRX */
  55. #define PPI_D1S_ATMR 0x0148 /* Delay for Data Lane 1 in LPRX */
  56. #define PPI_D2S_ATMR 0x014C /* Delay for Data Lane 2 in LPRX */
  57. #define PPI_D3S_ATMR 0x0150 /* Delay for Data Lane 3 in LPRX */
  58. #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* For lane 0 */
  59. #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* For lane 1 */
  60. #define PPI_D2S_CLRSIPOCOUNT 0x016C /* For lane 2 */
  61. #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* For lane 3 */
  62. #define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */
  63. #define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */
  64. #define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */
  65. #define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */
  66. #define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */
  67. #define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */
  68. #define D0S_PREP 0x01A4 /* Digital Counter inside of PHY IO */
  69. #define D1S_PREP 0x01A8 /* Digital Counter inside of PHY IO */
  70. #define D2S_PREP 0x01AC /* Digital Counter inside of PHY IO */
  71. #define D3S_PREP 0x01B0 /* Digital Counter inside of PHY IO */
  72. #define CLS_ZERO 0x01C0 /* Digital Counter inside of PHY IO */
  73. #define D0S_ZERO 0x01C4 /* Digital Counter inside of PHY IO */
  74. #define D1S_ZERO 0x01C8 /* Digital Counter inside of PHY IO */
  75. #define D2S_ZERO 0x01CC /* Digital Counter inside of PHY IO */
  76. #define D3S_ZERO 0x01D0 /* Digital Counter inside of PHY IO */
  77. #define PPI_CLRFLG 0x01E0 /* PRE Counters has reached set values */
  78. #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
  79. #define HSTIMEOUT 0x01F0 /* HS Rx Time Out Counter */
  80. #define HSTIMEOUTENABLE 0x01F4 /* Enable HS Rx Time Out Counter */
  81. #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
  82. #define DSI_RX_START 1
  83. #define DSI_BUSYDSI 0x0208
  84. #define DSI_LANEENABLE 0x0210 /* Enables each lane at the Protocol layer. */
  85. #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
  86. #define DSI_LANESTATUS1 0x0218 /* Displays lane is in ULPS or STOP state */
  87. #define DSI_INTSTATUS 0x0220 /* Interrupt Status */
  88. #define DSI_INTMASK 0x0224 /* Interrupt Mask */
  89. #define DSI_INTCLR 0x0228 /* Interrupt Clear */
  90. #define DSI_LPTXTO 0x0230 /* Low Power Tx Time Out Counter */
  91. #define DSIERRCNT 0x0300 /* DSI Error Count */
  92. #define APLCTRL 0x0400 /* Application Layer Control */
  93. #define RDPKTLN 0x0404 /* Command Read Packet Length */
  94. #define VPCTRL 0x0450 /* Video Path Control */
  95. #define HTIM1 0x0454 /* Horizontal Timing Control 1 */
  96. #define HTIM2 0x0458 /* Horizontal Timing Control 2 */
  97. #define VTIM1 0x045C /* Vertical Timing Control 1 */
  98. #define VTIM2 0x0460 /* Vertical Timing Control 2 */
  99. #define VFUEN 0x0464 /* Video Frame Timing Update Enable */
  100. #define VFUEN_EN BIT(0) /* Upload Enable */
  101. /* Mux Input Select for LVDS LINK Input */
  102. #define LV_MX0003 0x0480 /* Bit 0 to 3 */
  103. #define LV_MX0407 0x0484 /* Bit 4 to 7 */
  104. #define LV_MX0811 0x0488 /* Bit 8 to 11 */
  105. #define LV_MX1215 0x048C /* Bit 12 to 15 */
  106. #define LV_MX1619 0x0490 /* Bit 16 to 19 */
  107. #define LV_MX2023 0x0494 /* Bit 20 to 23 */
  108. #define LV_MX2427 0x0498 /* Bit 24 to 27 */
  109. #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
  110. FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
  111. /* Input bit numbers used in mux registers */
  112. enum {
  113. LVI_R0,
  114. LVI_R1,
  115. LVI_R2,
  116. LVI_R3,
  117. LVI_R4,
  118. LVI_R5,
  119. LVI_R6,
  120. LVI_R7,
  121. LVI_G0,
  122. LVI_G1,
  123. LVI_G2,
  124. LVI_G3,
  125. LVI_G4,
  126. LVI_G5,
  127. LVI_G6,
  128. LVI_G7,
  129. LVI_B0,
  130. LVI_B1,
  131. LVI_B2,
  132. LVI_B3,
  133. LVI_B4,
  134. LVI_B5,
  135. LVI_B6,
  136. LVI_B7,
  137. LVI_HS,
  138. LVI_VS,
  139. LVI_DE,
  140. LVI_L0
  141. };
  142. #define LVCFG 0x049C /* LVDS Configuration */
  143. #define LVPHY0 0x04A0 /* LVDS PHY 0 */
  144. #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
  145. #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
  146. #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
  147. #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
  148. #define LVPHY1 0x04A4 /* LVDS PHY 1 */
  149. #define SYSSTAT 0x0500 /* System Status */
  150. #define SYSRST 0x0504 /* System Reset */
  151. #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
  152. #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
  153. #define SYS_RST_LCD BIT(2) /* Reset LCD controller */
  154. #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
  155. #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
  156. #define SYS_RST_REG BIT(5) /* Reset Register module */
  157. /* GPIO Registers */
  158. #define GPIOC 0x0520 /* GPIO Control */
  159. #define GPIOO 0x0524 /* GPIO Output */
  160. #define GPIOI 0x0528 /* GPIO Input */
  161. /* I2C Registers */
  162. #define I2CTIMCTRL 0x0540 /* I2C IF Timing and Enable Control */
  163. #define I2CMADDR 0x0544 /* I2C Master Addressing */
  164. #define WDATAQ 0x0548 /* Write Data Queue */
  165. #define RDATAQ 0x054C /* Read Data Queue */
  166. /* Chip ID and Revision ID Register */
  167. #define IDREG 0x0580
  168. #define LPX_PERIOD 4
  169. #define TTA_GET 0x40000
  170. #define TTA_SURE 6
  171. #define SINGLE_LINK 1
  172. #define DUAL_LINK 2
  173. #define TC358775XBG_ID 0x00007500
  174. /* Debug Registers */
  175. #define DEBUG00 0x05A0 /* Debug */
  176. #define DEBUG01 0x05A4 /* LVDS Data */
  177. #define DSI_CLEN_BIT BIT(0)
  178. #define DIVIDE_BY_3 3 /* PCLK=DCLK/3 */
  179. #define DIVIDE_BY_6 6 /* PCLK=DCLK/6 */
  180. #define LVCFG_LVEN_BIT BIT(0)
  181. #define L0EN BIT(1)
  182. #define TC358775_VPCTRL_VSDELAY__MASK 0x3FF00000
  183. #define TC358775_VPCTRL_VSDELAY__SHIFT 20
  184. static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
  185. {
  186. return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) &
  187. TC358775_VPCTRL_VSDELAY__MASK;
  188. }
  189. #define TC358775_VPCTRL_OPXLFMT__MASK 0x00000100
  190. #define TC358775_VPCTRL_OPXLFMT__SHIFT 8
  191. static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
  192. {
  193. return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) &
  194. TC358775_VPCTRL_OPXLFMT__MASK;
  195. }
  196. #define TC358775_VPCTRL_MSF__MASK 0x00000001
  197. #define TC358775_VPCTRL_MSF__SHIFT 0
  198. static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
  199. {
  200. return ((val) << TC358775_VPCTRL_MSF__SHIFT) &
  201. TC358775_VPCTRL_MSF__MASK;
  202. }
  203. #define TC358775_LVCFG_PCLKDIV__MASK 0x000000f0
  204. #define TC358775_LVCFG_PCLKDIV__SHIFT 4
  205. static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
  206. {
  207. return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
  208. TC358775_LVCFG_PCLKDIV__MASK;
  209. }
  210. #define TC358775_LVCFG_LVDLINK__MASK 0x00000002
  211. #define TC358775_LVCFG_LVDLINK__SHIFT 0
  212. static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
  213. {
  214. return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
  215. TC358775_LVCFG_LVDLINK__MASK;
  216. }
  217. enum tc358775_ports {
  218. TC358775_DSI_IN,
  219. TC358775_LVDS_OUT0,
  220. TC358775_LVDS_OUT1,
  221. };
  222. struct tc_data {
  223. struct i2c_client *i2c;
  224. struct device *dev;
  225. struct drm_bridge bridge;
  226. struct drm_bridge *panel_bridge;
  227. struct device_node *host_node;
  228. struct mipi_dsi_device *dsi;
  229. u8 num_dsi_lanes;
  230. struct regulator *vdd;
  231. struct regulator *vddio;
  232. struct gpio_desc *reset_gpio;
  233. struct gpio_desc *stby_gpio;
  234. u8 lvds_link; /* single-link or dual-link */
  235. u8 bpc;
  236. };
  237. static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
  238. {
  239. return container_of(b, struct tc_data, bridge);
  240. }
  241. static void tc_bridge_pre_enable(struct drm_bridge *bridge)
  242. {
  243. struct tc_data *tc = bridge_to_tc(bridge);
  244. struct device *dev = &tc->dsi->dev;
  245. int ret;
  246. ret = regulator_enable(tc->vddio);
  247. if (ret < 0)
  248. dev_err(dev, "regulator vddio enable failed, %d\n", ret);
  249. usleep_range(10000, 11000);
  250. ret = regulator_enable(tc->vdd);
  251. if (ret < 0)
  252. dev_err(dev, "regulator vdd enable failed, %d\n", ret);
  253. usleep_range(10000, 11000);
  254. gpiod_set_value(tc->stby_gpio, 0);
  255. usleep_range(10000, 11000);
  256. gpiod_set_value(tc->reset_gpio, 0);
  257. usleep_range(10, 20);
  258. }
  259. static void tc_bridge_post_disable(struct drm_bridge *bridge)
  260. {
  261. struct tc_data *tc = bridge_to_tc(bridge);
  262. struct device *dev = &tc->dsi->dev;
  263. int ret;
  264. gpiod_set_value(tc->reset_gpio, 1);
  265. usleep_range(10, 20);
  266. gpiod_set_value(tc->stby_gpio, 1);
  267. usleep_range(10000, 11000);
  268. ret = regulator_disable(tc->vdd);
  269. if (ret < 0)
  270. dev_err(dev, "regulator vdd disable failed, %d\n", ret);
  271. usleep_range(10000, 11000);
  272. ret = regulator_disable(tc->vddio);
  273. if (ret < 0)
  274. dev_err(dev, "regulator vddio disable failed, %d\n", ret);
  275. usleep_range(10000, 11000);
  276. }
  277. static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val)
  278. {
  279. int ret;
  280. u8 buf_addr[2];
  281. put_unaligned_be16(addr, buf_addr);
  282. ret = i2c_master_send(i2c, buf_addr, sizeof(buf_addr));
  283. if (ret < 0)
  284. goto fail;
  285. ret = i2c_master_recv(i2c, (u8 *)val, sizeof(*val));
  286. if (ret < 0)
  287. goto fail;
  288. pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val);
  289. fail:
  290. dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",
  291. ret, addr);
  292. }
  293. static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val)
  294. {
  295. u8 data[6];
  296. int ret;
  297. put_unaligned_be16(addr, data);
  298. put_unaligned_le32(val, data + 2);
  299. ret = i2c_master_send(i2c, data, ARRAY_SIZE(data));
  300. if (ret < 0)
  301. dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n",
  302. ret, addr);
  303. }
  304. /* helper function to access bus_formats */
  305. static struct drm_connector *get_connector(struct drm_encoder *encoder)
  306. {
  307. struct drm_device *dev = encoder->dev;
  308. struct drm_connector *connector;
  309. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  310. if (connector->encoder == encoder)
  311. return connector;
  312. return NULL;
  313. }
  314. static void tc_bridge_enable(struct drm_bridge *bridge)
  315. {
  316. struct tc_data *tc = bridge_to_tc(bridge);
  317. u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
  318. u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
  319. u32 val = 0;
  320. u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
  321. struct drm_display_mode *mode;
  322. struct drm_connector *connector = get_connector(bridge->encoder);
  323. mode = &bridge->encoder->crtc->state->adjusted_mode;
  324. hback_porch = mode->htotal - mode->hsync_end;
  325. hsync_len = mode->hsync_end - mode->hsync_start;
  326. vback_porch = mode->vtotal - mode->vsync_end;
  327. vsync_len = mode->vsync_end - mode->vsync_start;
  328. htime1 = (hback_porch << 16) + hsync_len;
  329. vtime1 = (vback_porch << 16) + vsync_len;
  330. hfront_porch = mode->hsync_start - mode->hdisplay;
  331. hactive = mode->hdisplay;
  332. vfront_porch = mode->vsync_start - mode->vdisplay;
  333. vactive = mode->vdisplay;
  334. htime2 = (hfront_porch << 16) + hactive;
  335. vtime2 = (vfront_porch << 16) + vactive;
  336. d2l_read(tc->i2c, IDREG, &val);
  337. dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",
  338. (val >> 8) & 0xFF, val & 0xFF);
  339. d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
  340. SYS_RST_LCD | SYS_RST_I2CM | SYS_RST_I2CS);
  341. usleep_range(30000, 40000);
  342. d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
  343. d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
  344. d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
  345. d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
  346. d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
  347. d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
  348. val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
  349. d2l_write(tc->i2c, PPI_LANEENABLE, val);
  350. d2l_write(tc->i2c, DSI_LANEENABLE, val);
  351. d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
  352. d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
  353. if (tc->bpc == 8)
  354. val = TC358775_VPCTRL_OPXLFMT(1);
  355. else /* bpc = 6; */
  356. val = TC358775_VPCTRL_MSF(1);
  357. dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;
  358. clkdiv = dsiclk / DIVIDE_BY_3 * tc->lvds_link;
  359. byteclk = dsiclk / 4;
  360. t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;
  361. t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;
  362. t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /
  363. tc->num_dsi_lanes);
  364. vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;
  365. val |= TC358775_VPCTRL_VSDELAY(vsdelay);
  366. d2l_write(tc->i2c, VPCTRL, val);
  367. d2l_write(tc->i2c, HTIM1, htime1);
  368. d2l_write(tc->i2c, VTIM1, vtime1);
  369. d2l_write(tc->i2c, HTIM2, htime2);
  370. d2l_write(tc->i2c, VTIM2, vtime2);
  371. d2l_write(tc->i2c, VFUEN, VFUEN_EN);
  372. d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
  373. d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
  374. dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
  375. connector->display_info.bus_formats[0],
  376. tc->bpc);
  377. /*
  378. * Default hardware register settings of tc358775 configured
  379. * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format
  380. */
  381. if (connector->display_info.bus_formats[0] ==
  382. MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
  383. /* VESA-24 */
  384. d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
  385. d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
  386. d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
  387. d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
  388. d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
  389. d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
  390. d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
  391. } else { /* MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */
  392. d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
  393. d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5, LVI_G0));
  394. d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0, LVI_L0));
  395. d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
  396. d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1, LVI_B2));
  397. d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
  398. d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_L0));
  399. }
  400. d2l_write(tc->i2c, VFUEN, VFUEN_EN);
  401. val = LVCFG_LVEN_BIT;
  402. if (tc->lvds_link == DUAL_LINK) {
  403. val |= TC358775_LVCFG_LVDLINK(1);
  404. val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
  405. } else {
  406. val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
  407. }
  408. d2l_write(tc->i2c, LVCFG, val);
  409. }
  410. static enum drm_mode_status
  411. tc_mode_valid(struct drm_bridge *bridge,
  412. const struct drm_display_info *info,
  413. const struct drm_display_mode *mode)
  414. {
  415. struct tc_data *tc = bridge_to_tc(bridge);
  416. /*
  417. * Maximum pixel clock speed 135MHz for single-link
  418. * 270MHz for dual-link
  419. */
  420. if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||
  421. (mode->clock > 270000 && tc->lvds_link == DUAL_LINK))
  422. return MODE_CLOCK_HIGH;
  423. switch (info->bus_formats[0]) {
  424. case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
  425. case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
  426. /* RGB888 */
  427. tc->bpc = 8;
  428. break;
  429. case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
  430. /* RGB666 */
  431. tc->bpc = 6;
  432. break;
  433. default:
  434. dev_warn(tc->dev,
  435. "unsupported LVDS bus format 0x%04x\n",
  436. info->bus_formats[0]);
  437. return MODE_NOMODE;
  438. }
  439. return MODE_OK;
  440. }
  441. static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc)
  442. {
  443. struct device_node *endpoint;
  444. struct device_node *parent;
  445. struct device_node *remote;
  446. struct property *prop;
  447. int len = 0;
  448. /*
  449. * To get the data-lanes of dsi, we need to access the dsi0_out of port1
  450. * of dsi0 endpoint from bridge port0 of d2l_in
  451. */
  452. endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
  453. TC358775_DSI_IN, -1);
  454. if (endpoint) {
  455. /* dsi0_out node */
  456. parent = of_graph_get_remote_port_parent(endpoint);
  457. of_node_put(endpoint);
  458. if (parent) {
  459. /* dsi0 port 1 */
  460. endpoint = of_graph_get_endpoint_by_regs(parent, 1, -1);
  461. of_node_put(parent);
  462. if (endpoint) {
  463. prop = of_find_property(endpoint, "data-lanes",
  464. &len);
  465. of_node_put(endpoint);
  466. if (!prop) {
  467. dev_err(tc->dev,
  468. "failed to find data lane\n");
  469. return -EPROBE_DEFER;
  470. }
  471. }
  472. }
  473. }
  474. tc->num_dsi_lanes = len / sizeof(u32);
  475. if (tc->num_dsi_lanes < 1 || tc->num_dsi_lanes > 4)
  476. return -EINVAL;
  477. tc->host_node = of_graph_get_remote_node(np, 0, 0);
  478. if (!tc->host_node)
  479. return -ENODEV;
  480. of_node_put(tc->host_node);
  481. tc->lvds_link = SINGLE_LINK;
  482. endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
  483. TC358775_LVDS_OUT1, -1);
  484. if (endpoint) {
  485. remote = of_graph_get_remote_port_parent(endpoint);
  486. of_node_put(endpoint);
  487. if (remote) {
  488. if (of_device_is_available(remote))
  489. tc->lvds_link = DUAL_LINK;
  490. of_node_put(remote);
  491. }
  492. }
  493. dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);
  494. dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link);
  495. return 0;
  496. }
  497. static int tc_bridge_attach(struct drm_bridge *bridge,
  498. enum drm_bridge_attach_flags flags)
  499. {
  500. struct tc_data *tc = bridge_to_tc(bridge);
  501. struct device *dev = &tc->i2c->dev;
  502. struct mipi_dsi_host *host;
  503. struct mipi_dsi_device *dsi;
  504. int ret;
  505. const struct mipi_dsi_device_info info = { .type = "tc358775",
  506. .channel = 0,
  507. .node = NULL,
  508. };
  509. host = of_find_mipi_dsi_host_by_node(tc->host_node);
  510. if (!host) {
  511. dev_err(dev, "failed to find dsi host\n");
  512. return -EPROBE_DEFER;
  513. }
  514. dsi = mipi_dsi_device_register_full(host, &info);
  515. if (IS_ERR(dsi)) {
  516. dev_err(dev, "failed to create dsi device\n");
  517. ret = PTR_ERR(dsi);
  518. goto err_dsi_device;
  519. }
  520. tc->dsi = dsi;
  521. dsi->lanes = tc->num_dsi_lanes;
  522. dsi->format = MIPI_DSI_FMT_RGB888;
  523. dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
  524. ret = mipi_dsi_attach(dsi);
  525. if (ret < 0) {
  526. dev_err(dev, "failed to attach dsi to host\n");
  527. goto err_dsi_attach;
  528. }
  529. /* Attach the panel-bridge to the dsi bridge */
  530. return drm_bridge_attach(bridge->encoder, tc->panel_bridge,
  531. &tc->bridge, flags);
  532. err_dsi_attach:
  533. mipi_dsi_device_unregister(dsi);
  534. err_dsi_device:
  535. return ret;
  536. }
  537. static const struct drm_bridge_funcs tc_bridge_funcs = {
  538. .attach = tc_bridge_attach,
  539. .pre_enable = tc_bridge_pre_enable,
  540. .enable = tc_bridge_enable,
  541. .mode_valid = tc_mode_valid,
  542. .post_disable = tc_bridge_post_disable,
  543. };
  544. static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
  545. {
  546. struct device *dev = &client->dev;
  547. struct drm_panel *panel;
  548. struct tc_data *tc;
  549. int ret;
  550. tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
  551. if (!tc)
  552. return -ENOMEM;
  553. tc->dev = dev;
  554. tc->i2c = client;
  555. ret = drm_of_find_panel_or_bridge(dev->of_node, TC358775_LVDS_OUT0,
  556. 0, &panel, NULL);
  557. if (ret < 0)
  558. return ret;
  559. if (!panel)
  560. return -ENODEV;
  561. tc->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
  562. if (IS_ERR(tc->panel_bridge))
  563. return PTR_ERR(tc->panel_bridge);
  564. ret = tc358775_parse_dt(dev->of_node, tc);
  565. if (ret)
  566. return ret;
  567. tc->vddio = devm_regulator_get(dev, "vddio-supply");
  568. if (IS_ERR(tc->vddio)) {
  569. ret = PTR_ERR(tc->vddio);
  570. dev_err(dev, "vddio-supply not found\n");
  571. return ret;
  572. }
  573. tc->vdd = devm_regulator_get(dev, "vdd-supply");
  574. if (IS_ERR(tc->vdd)) {
  575. ret = PTR_ERR(tc->vdd);
  576. dev_err(dev, "vdd-supply not found\n");
  577. return ret;
  578. }
  579. tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH);
  580. if (IS_ERR(tc->stby_gpio)) {
  581. ret = PTR_ERR(tc->stby_gpio);
  582. dev_err(dev, "cannot get stby-gpio %d\n", ret);
  583. return ret;
  584. }
  585. tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
  586. if (IS_ERR(tc->reset_gpio)) {
  587. ret = PTR_ERR(tc->reset_gpio);
  588. dev_err(dev, "cannot get reset-gpios %d\n", ret);
  589. return ret;
  590. }
  591. tc->bridge.funcs = &tc_bridge_funcs;
  592. tc->bridge.of_node = dev->of_node;
  593. drm_bridge_add(&tc->bridge);
  594. i2c_set_clientdata(client, tc);
  595. return 0;
  596. }
  597. static int tc_remove(struct i2c_client *client)
  598. {
  599. struct tc_data *tc = i2c_get_clientdata(client);
  600. drm_bridge_remove(&tc->bridge);
  601. return 0;
  602. }
  603. static const struct i2c_device_id tc358775_i2c_ids[] = {
  604. { "tc358775", 0 },
  605. { }
  606. };
  607. MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
  608. static const struct of_device_id tc358775_of_ids[] = {
  609. { .compatible = "toshiba,tc358775", },
  610. { }
  611. };
  612. MODULE_DEVICE_TABLE(of, tc358775_of_ids);
  613. static struct i2c_driver tc358775_driver = {
  614. .driver = {
  615. .name = "tc358775",
  616. .of_match_table = tc358775_of_ids,
  617. },
  618. .id_table = tc358775_i2c_ids,
  619. .probe = tc_probe,
  620. .remove = tc_remove,
  621. };
  622. module_i2c_driver(tc358775_driver);
  623. MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>");
  624. MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");
  625. MODULE_LICENSE("GPL v2");