tc358767.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * tc358767 eDP bridge driver
  4. *
  5. * Copyright (C) 2016 CogentEmbedded Inc
  6. * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
  7. *
  8. * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
  9. *
  10. * Copyright (C) 2016 Zodiac Inflight Innovations
  11. *
  12. * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
  13. *
  14. * Copyright (C) 2012 Texas Instruments
  15. * Author: Rob Clark <robdclark@gmail.com>
  16. */
  17. #include <linux/bitfield.h>
  18. #include <linux/clk.h>
  19. #include <linux/device.h>
  20. #include <linux/gpio/consumer.h>
  21. #include <linux/i2c.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/regmap.h>
  25. #include <linux/slab.h>
  26. #include <drm/drm_atomic_helper.h>
  27. #include <drm/drm_bridge.h>
  28. #include <drm/drm_dp_helper.h>
  29. #include <drm/drm_edid.h>
  30. #include <drm/drm_of.h>
  31. #include <drm/drm_panel.h>
  32. #include <drm/drm_print.h>
  33. #include <drm/drm_probe_helper.h>
  34. /* Registers */
  35. /* Display Parallel Interface */
  36. #define DPIPXLFMT 0x0440
  37. #define VS_POL_ACTIVE_LOW (1 << 10)
  38. #define HS_POL_ACTIVE_LOW (1 << 9)
  39. #define DE_POL_ACTIVE_HIGH (0 << 8)
  40. #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
  41. #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
  42. #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
  43. #define DPI_BPP_RGB888 (0 << 0)
  44. #define DPI_BPP_RGB666 (1 << 0)
  45. #define DPI_BPP_RGB565 (2 << 0)
  46. /* Video Path */
  47. #define VPCTRL0 0x0450
  48. #define VSDELAY GENMASK(31, 20)
  49. #define OPXLFMT_RGB666 (0 << 8)
  50. #define OPXLFMT_RGB888 (1 << 8)
  51. #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
  52. #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
  53. #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
  54. #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
  55. #define HTIM01 0x0454
  56. #define HPW GENMASK(8, 0)
  57. #define HBPR GENMASK(24, 16)
  58. #define HTIM02 0x0458
  59. #define HDISPR GENMASK(10, 0)
  60. #define HFPR GENMASK(24, 16)
  61. #define VTIM01 0x045c
  62. #define VSPR GENMASK(7, 0)
  63. #define VBPR GENMASK(23, 16)
  64. #define VTIM02 0x0460
  65. #define VFPR GENMASK(23, 16)
  66. #define VDISPR GENMASK(10, 0)
  67. #define VFUEN0 0x0464
  68. #define VFUEN BIT(0) /* Video Frame Timing Upload */
  69. /* System */
  70. #define TC_IDREG 0x0500
  71. #define SYSSTAT 0x0508
  72. #define SYSCTRL 0x0510
  73. #define DP0_AUDSRC_NO_INPUT (0 << 3)
  74. #define DP0_AUDSRC_I2S_RX (1 << 3)
  75. #define DP0_VIDSRC_NO_INPUT (0 << 0)
  76. #define DP0_VIDSRC_DSI_RX (1 << 0)
  77. #define DP0_VIDSRC_DPI_RX (2 << 0)
  78. #define DP0_VIDSRC_COLOR_BAR (3 << 0)
  79. #define SYSRSTENB 0x050c
  80. #define ENBI2C (1 << 0)
  81. #define ENBLCD0 (1 << 2)
  82. #define ENBBM (1 << 3)
  83. #define ENBDSIRX (1 << 4)
  84. #define ENBREG (1 << 5)
  85. #define ENBHDCP (1 << 8)
  86. #define GPIOM 0x0540
  87. #define GPIOC 0x0544
  88. #define GPIOO 0x0548
  89. #define GPIOI 0x054c
  90. #define INTCTL_G 0x0560
  91. #define INTSTS_G 0x0564
  92. #define INT_SYSERR BIT(16)
  93. #define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10))
  94. #define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11))
  95. #define INT_GP0_LCNT 0x0584
  96. #define INT_GP1_LCNT 0x0588
  97. /* Control */
  98. #define DP0CTL 0x0600
  99. #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
  100. #define EF_EN BIT(5) /* Enable Enhanced Framing */
  101. #define VID_EN BIT(1) /* Video transmission enable */
  102. #define DP_EN BIT(0) /* Enable DPTX function */
  103. /* Clocks */
  104. #define DP0_VIDMNGEN0 0x0610
  105. #define DP0_VIDMNGEN1 0x0614
  106. #define DP0_VMNGENSTATUS 0x0618
  107. /* Main Channel */
  108. #define DP0_SECSAMPLE 0x0640
  109. #define DP0_VIDSYNCDELAY 0x0644
  110. #define VID_SYNC_DLY GENMASK(15, 0)
  111. #define THRESH_DLY GENMASK(31, 16)
  112. #define DP0_TOTALVAL 0x0648
  113. #define H_TOTAL GENMASK(15, 0)
  114. #define V_TOTAL GENMASK(31, 16)
  115. #define DP0_STARTVAL 0x064c
  116. #define H_START GENMASK(15, 0)
  117. #define V_START GENMASK(31, 16)
  118. #define DP0_ACTIVEVAL 0x0650
  119. #define H_ACT GENMASK(15, 0)
  120. #define V_ACT GENMASK(31, 16)
  121. #define DP0_SYNCVAL 0x0654
  122. #define VS_WIDTH GENMASK(30, 16)
  123. #define HS_WIDTH GENMASK(14, 0)
  124. #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
  125. #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
  126. #define DP0_MISC 0x0658
  127. #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
  128. #define MAX_TU_SYMBOL GENMASK(28, 23)
  129. #define TU_SIZE GENMASK(21, 16)
  130. #define BPC_6 (0 << 5)
  131. #define BPC_8 (1 << 5)
  132. /* AUX channel */
  133. #define DP0_AUXCFG0 0x0660
  134. #define DP0_AUXCFG0_BSIZE GENMASK(11, 8)
  135. #define DP0_AUXCFG0_ADDR_ONLY BIT(4)
  136. #define DP0_AUXCFG1 0x0664
  137. #define AUX_RX_FILTER_EN BIT(16)
  138. #define DP0_AUXADDR 0x0668
  139. #define DP0_AUXWDATA(i) (0x066c + (i) * 4)
  140. #define DP0_AUXRDATA(i) (0x067c + (i) * 4)
  141. #define DP0_AUXSTATUS 0x068c
  142. #define AUX_BYTES GENMASK(15, 8)
  143. #define AUX_STATUS GENMASK(7, 4)
  144. #define AUX_TIMEOUT BIT(1)
  145. #define AUX_BUSY BIT(0)
  146. #define DP0_AUXI2CADR 0x0698
  147. /* Link Training */
  148. #define DP0_SRCCTRL 0x06a0
  149. #define DP0_SRCCTRL_SCRMBLDIS BIT(13)
  150. #define DP0_SRCCTRL_EN810B BIT(12)
  151. #define DP0_SRCCTRL_NOTP (0 << 8)
  152. #define DP0_SRCCTRL_TP1 (1 << 8)
  153. #define DP0_SRCCTRL_TP2 (2 << 8)
  154. #define DP0_SRCCTRL_LANESKEW BIT(7)
  155. #define DP0_SRCCTRL_SSCG BIT(3)
  156. #define DP0_SRCCTRL_LANES_1 (0 << 2)
  157. #define DP0_SRCCTRL_LANES_2 (1 << 2)
  158. #define DP0_SRCCTRL_BW27 (1 << 1)
  159. #define DP0_SRCCTRL_BW162 (0 << 1)
  160. #define DP0_SRCCTRL_AUTOCORRECT BIT(0)
  161. #define DP0_LTSTAT 0x06d0
  162. #define LT_LOOPDONE BIT(13)
  163. #define LT_STATUS_MASK (0x1f << 8)
  164. #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
  165. #define LT_INTERLANE_ALIGN_DONE BIT(3)
  166. #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
  167. #define DP0_SNKLTCHGREQ 0x06d4
  168. #define DP0_LTLOOPCTRL 0x06d8
  169. #define DP0_SNKLTCTRL 0x06e4
  170. #define DP1_SRCCTRL 0x07a0
  171. /* PHY */
  172. #define DP_PHY_CTRL 0x0800
  173. #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
  174. #define BGREN BIT(25) /* AUX PHY BGR Enable */
  175. #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
  176. #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
  177. #define PHY_RDY BIT(16) /* PHY Main Channels Ready */
  178. #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
  179. #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
  180. #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
  181. #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
  182. /* PLL */
  183. #define DP0_PLLCTRL 0x0900
  184. #define DP1_PLLCTRL 0x0904 /* not defined in DS */
  185. #define PXL_PLLCTRL 0x0908
  186. #define PLLUPDATE BIT(2)
  187. #define PLLBYP BIT(1)
  188. #define PLLEN BIT(0)
  189. #define PXL_PLLPARAM 0x0914
  190. #define IN_SEL_REFCLK (0 << 14)
  191. #define SYS_PLLPARAM 0x0918
  192. #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
  193. #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
  194. #define REF_FREQ_26M (2 << 8) /* 26 MHz */
  195. #define REF_FREQ_13M (3 << 8) /* 13 MHz */
  196. #define SYSCLK_SEL_LSCLK (0 << 4)
  197. #define LSCLK_DIV_1 (0 << 0)
  198. #define LSCLK_DIV_2 (1 << 0)
  199. /* Test & Debug */
  200. #define TSTCTL 0x0a00
  201. #define COLOR_R GENMASK(31, 24)
  202. #define COLOR_G GENMASK(23, 16)
  203. #define COLOR_B GENMASK(15, 8)
  204. #define ENI2CFILTER BIT(4)
  205. #define COLOR_BAR_MODE GENMASK(1, 0)
  206. #define COLOR_BAR_MODE_BARS 2
  207. #define PLL_DBG 0x0a04
  208. static bool tc_test_pattern;
  209. module_param_named(test, tc_test_pattern, bool, 0644);
  210. struct tc_edp_link {
  211. u8 dpcd[DP_RECEIVER_CAP_SIZE];
  212. unsigned int rate;
  213. u8 num_lanes;
  214. u8 assr;
  215. bool scrambler_dis;
  216. bool spread;
  217. };
  218. struct tc_data {
  219. struct device *dev;
  220. struct regmap *regmap;
  221. struct drm_dp_aux aux;
  222. struct drm_bridge bridge;
  223. struct drm_bridge *panel_bridge;
  224. struct drm_connector connector;
  225. /* link settings */
  226. struct tc_edp_link link;
  227. /* current mode */
  228. struct drm_display_mode mode;
  229. u32 rev;
  230. u8 assr;
  231. struct gpio_desc *sd_gpio;
  232. struct gpio_desc *reset_gpio;
  233. struct clk *refclk;
  234. /* do we have IRQ */
  235. bool have_irq;
  236. /* HPD pin number (0 or 1) or -ENODEV */
  237. int hpd_pin;
  238. };
  239. static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
  240. {
  241. return container_of(a, struct tc_data, aux);
  242. }
  243. static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
  244. {
  245. return container_of(b, struct tc_data, bridge);
  246. }
  247. static inline struct tc_data *connector_to_tc(struct drm_connector *c)
  248. {
  249. return container_of(c, struct tc_data, connector);
  250. }
  251. static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
  252. unsigned int cond_mask,
  253. unsigned int cond_value,
  254. unsigned long sleep_us, u64 timeout_us)
  255. {
  256. unsigned int val;
  257. return regmap_read_poll_timeout(tc->regmap, addr, val,
  258. (val & cond_mask) == cond_value,
  259. sleep_us, timeout_us);
  260. }
  261. static int tc_aux_wait_busy(struct tc_data *tc)
  262. {
  263. return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
  264. }
  265. static int tc_aux_write_data(struct tc_data *tc, const void *data,
  266. size_t size)
  267. {
  268. u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
  269. int ret, count = ALIGN(size, sizeof(u32));
  270. memcpy(auxwdata, data, size);
  271. ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
  272. if (ret)
  273. return ret;
  274. return size;
  275. }
  276. static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
  277. {
  278. u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
  279. int ret, count = ALIGN(size, sizeof(u32));
  280. ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
  281. if (ret)
  282. return ret;
  283. memcpy(data, auxrdata, size);
  284. return size;
  285. }
  286. static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
  287. {
  288. u32 auxcfg0 = msg->request;
  289. if (size)
  290. auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
  291. else
  292. auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
  293. return auxcfg0;
  294. }
  295. static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
  296. struct drm_dp_aux_msg *msg)
  297. {
  298. struct tc_data *tc = aux_to_tc(aux);
  299. size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
  300. u8 request = msg->request & ~DP_AUX_I2C_MOT;
  301. u32 auxstatus;
  302. int ret;
  303. ret = tc_aux_wait_busy(tc);
  304. if (ret)
  305. return ret;
  306. switch (request) {
  307. case DP_AUX_NATIVE_READ:
  308. case DP_AUX_I2C_READ:
  309. break;
  310. case DP_AUX_NATIVE_WRITE:
  311. case DP_AUX_I2C_WRITE:
  312. if (size) {
  313. ret = tc_aux_write_data(tc, msg->buffer, size);
  314. if (ret < 0)
  315. return ret;
  316. }
  317. break;
  318. default:
  319. return -EINVAL;
  320. }
  321. /* Store address */
  322. ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
  323. if (ret)
  324. return ret;
  325. /* Start transfer */
  326. ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
  327. if (ret)
  328. return ret;
  329. ret = tc_aux_wait_busy(tc);
  330. if (ret)
  331. return ret;
  332. ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
  333. if (ret)
  334. return ret;
  335. if (auxstatus & AUX_TIMEOUT)
  336. return -ETIMEDOUT;
  337. /*
  338. * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
  339. * reports 1 byte transferred in its status. To deal we that
  340. * we ignore aux_bytes field if we know that this was an
  341. * address-only transfer
  342. */
  343. if (size)
  344. size = FIELD_GET(AUX_BYTES, auxstatus);
  345. msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
  346. switch (request) {
  347. case DP_AUX_NATIVE_READ:
  348. case DP_AUX_I2C_READ:
  349. if (size)
  350. return tc_aux_read_data(tc, msg->buffer, size);
  351. break;
  352. }
  353. return size;
  354. }
  355. static const char * const training_pattern1_errors[] = {
  356. "No errors",
  357. "Aux write error",
  358. "Aux read error",
  359. "Max voltage reached error",
  360. "Loop counter expired error",
  361. "res", "res", "res"
  362. };
  363. static const char * const training_pattern2_errors[] = {
  364. "No errors",
  365. "Aux write error",
  366. "Aux read error",
  367. "Clock recovery failed error",
  368. "Loop counter expired error",
  369. "res", "res", "res"
  370. };
  371. static u32 tc_srcctrl(struct tc_data *tc)
  372. {
  373. /*
  374. * No training pattern, skew lane 1 data by two LSCLK cycles with
  375. * respect to lane 0 data, AutoCorrect Mode = 0
  376. */
  377. u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
  378. if (tc->link.scrambler_dis)
  379. reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
  380. if (tc->link.spread)
  381. reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
  382. if (tc->link.num_lanes == 2)
  383. reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
  384. if (tc->link.rate != 162000)
  385. reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
  386. return reg;
  387. }
  388. static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
  389. {
  390. int ret;
  391. ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
  392. if (ret)
  393. return ret;
  394. /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
  395. usleep_range(3000, 6000);
  396. return 0;
  397. }
  398. static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
  399. {
  400. int ret;
  401. int i_pre, best_pre = 1;
  402. int i_post, best_post = 1;
  403. int div, best_div = 1;
  404. int mul, best_mul = 1;
  405. int delta, best_delta;
  406. int ext_div[] = {1, 2, 3, 5, 7};
  407. int best_pixelclock = 0;
  408. int vco_hi = 0;
  409. u32 pxl_pllparam;
  410. dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
  411. refclk);
  412. best_delta = pixelclock;
  413. /* Loop over all possible ext_divs, skipping invalid configurations */
  414. for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
  415. /*
  416. * refclk / ext_pre_div should be in the 1 to 200 MHz range.
  417. * We don't allow any refclk > 200 MHz, only check lower bounds.
  418. */
  419. if (refclk / ext_div[i_pre] < 1000000)
  420. continue;
  421. for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
  422. for (div = 1; div <= 16; div++) {
  423. u32 clk;
  424. u64 tmp;
  425. tmp = pixelclock * ext_div[i_pre] *
  426. ext_div[i_post] * div;
  427. do_div(tmp, refclk);
  428. mul = tmp;
  429. /* Check limits */
  430. if ((mul < 1) || (mul > 128))
  431. continue;
  432. clk = (refclk / ext_div[i_pre] / div) * mul;
  433. /*
  434. * refclk * mul / (ext_pre_div * pre_div)
  435. * should be in the 150 to 650 MHz range
  436. */
  437. if ((clk > 650000000) || (clk < 150000000))
  438. continue;
  439. clk = clk / ext_div[i_post];
  440. delta = clk - pixelclock;
  441. if (abs(delta) < abs(best_delta)) {
  442. best_pre = i_pre;
  443. best_post = i_post;
  444. best_div = div;
  445. best_mul = mul;
  446. best_delta = delta;
  447. best_pixelclock = clk;
  448. }
  449. }
  450. }
  451. }
  452. if (best_pixelclock == 0) {
  453. dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
  454. pixelclock);
  455. return -EINVAL;
  456. }
  457. dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
  458. best_delta);
  459. dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
  460. ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
  461. /* if VCO >= 300 MHz */
  462. if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
  463. vco_hi = 1;
  464. /* see DS */
  465. if (best_div == 16)
  466. best_div = 0;
  467. if (best_mul == 128)
  468. best_mul = 0;
  469. /* Power up PLL and switch to bypass */
  470. ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
  471. if (ret)
  472. return ret;
  473. pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
  474. pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
  475. pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
  476. pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
  477. pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
  478. pxl_pllparam |= best_mul; /* Multiplier for PLL */
  479. ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
  480. if (ret)
  481. return ret;
  482. /* Force PLL parameter update and disable bypass */
  483. return tc_pllupdate(tc, PXL_PLLCTRL);
  484. }
  485. static int tc_pxl_pll_dis(struct tc_data *tc)
  486. {
  487. /* Enable PLL bypass, power down PLL */
  488. return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
  489. }
  490. static int tc_stream_clock_calc(struct tc_data *tc)
  491. {
  492. /*
  493. * If the Stream clock and Link Symbol clock are
  494. * asynchronous with each other, the value of M changes over
  495. * time. This way of generating link clock and stream
  496. * clock is called Asynchronous Clock mode. The value M
  497. * must change while the value N stays constant. The
  498. * value of N in this Asynchronous Clock mode must be set
  499. * to 2^15 or 32,768.
  500. *
  501. * LSCLK = 1/10 of high speed link clock
  502. *
  503. * f_STRMCLK = M/N * f_LSCLK
  504. * M/N = f_STRMCLK / f_LSCLK
  505. *
  506. */
  507. return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
  508. }
  509. static int tc_set_syspllparam(struct tc_data *tc)
  510. {
  511. unsigned long rate;
  512. u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
  513. rate = clk_get_rate(tc->refclk);
  514. switch (rate) {
  515. case 38400000:
  516. pllparam |= REF_FREQ_38M4;
  517. break;
  518. case 26000000:
  519. pllparam |= REF_FREQ_26M;
  520. break;
  521. case 19200000:
  522. pllparam |= REF_FREQ_19M2;
  523. break;
  524. case 13000000:
  525. pllparam |= REF_FREQ_13M;
  526. break;
  527. default:
  528. dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
  529. return -EINVAL;
  530. }
  531. return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
  532. }
  533. static int tc_aux_link_setup(struct tc_data *tc)
  534. {
  535. int ret;
  536. u32 dp0_auxcfg1;
  537. /* Setup DP-PHY / PLL */
  538. ret = tc_set_syspllparam(tc);
  539. if (ret)
  540. goto err;
  541. ret = regmap_write(tc->regmap, DP_PHY_CTRL,
  542. BGREN | PWR_SW_EN | PHY_A0_EN);
  543. if (ret)
  544. goto err;
  545. /*
  546. * Initially PLLs are in bypass. Force PLL parameter update,
  547. * disable PLL bypass, enable PLL
  548. */
  549. ret = tc_pllupdate(tc, DP0_PLLCTRL);
  550. if (ret)
  551. goto err;
  552. ret = tc_pllupdate(tc, DP1_PLLCTRL);
  553. if (ret)
  554. goto err;
  555. ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
  556. if (ret == -ETIMEDOUT) {
  557. dev_err(tc->dev, "Timeout waiting for PHY to become ready");
  558. return ret;
  559. } else if (ret) {
  560. goto err;
  561. }
  562. /* Setup AUX link */
  563. dp0_auxcfg1 = AUX_RX_FILTER_EN;
  564. dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
  565. dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
  566. ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
  567. if (ret)
  568. goto err;
  569. return 0;
  570. err:
  571. dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
  572. return ret;
  573. }
  574. static int tc_get_display_props(struct tc_data *tc)
  575. {
  576. u8 revision, num_lanes;
  577. unsigned int rate;
  578. int ret;
  579. u8 reg;
  580. /* Read DP Rx Link Capability */
  581. ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
  582. DP_RECEIVER_CAP_SIZE);
  583. if (ret < 0)
  584. goto err_dpcd_read;
  585. revision = tc->link.dpcd[DP_DPCD_REV];
  586. rate = drm_dp_max_link_rate(tc->link.dpcd);
  587. num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
  588. if (rate != 162000 && rate != 270000) {
  589. dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
  590. rate = 270000;
  591. }
  592. tc->link.rate = rate;
  593. if (num_lanes > 2) {
  594. dev_dbg(tc->dev, "Falling to 2 lanes\n");
  595. num_lanes = 2;
  596. }
  597. tc->link.num_lanes = num_lanes;
  598. ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
  599. if (ret < 0)
  600. goto err_dpcd_read;
  601. tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
  602. ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);
  603. if (ret < 0)
  604. goto err_dpcd_read;
  605. tc->link.scrambler_dis = false;
  606. /* read assr */
  607. ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);
  608. if (ret < 0)
  609. goto err_dpcd_read;
  610. tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
  611. dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
  612. revision >> 4, revision & 0x0f,
  613. (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
  614. tc->link.num_lanes,
  615. drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
  616. "enhanced" : "default");
  617. dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
  618. tc->link.spread ? "0.5%" : "0.0%",
  619. tc->link.scrambler_dis ? "disabled" : "enabled");
  620. dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
  621. tc->link.assr, tc->assr);
  622. return 0;
  623. err_dpcd_read:
  624. dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
  625. return ret;
  626. }
  627. static int tc_set_video_mode(struct tc_data *tc,
  628. const struct drm_display_mode *mode)
  629. {
  630. int ret;
  631. int vid_sync_dly;
  632. int max_tu_symbol;
  633. int left_margin = mode->htotal - mode->hsync_end;
  634. int right_margin = mode->hsync_start - mode->hdisplay;
  635. int hsync_len = mode->hsync_end - mode->hsync_start;
  636. int upper_margin = mode->vtotal - mode->vsync_end;
  637. int lower_margin = mode->vsync_start - mode->vdisplay;
  638. int vsync_len = mode->vsync_end - mode->vsync_start;
  639. u32 dp0_syncval;
  640. u32 bits_per_pixel = 24;
  641. u32 in_bw, out_bw;
  642. /*
  643. * Recommended maximum number of symbols transferred in a transfer unit:
  644. * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
  645. * (output active video bandwidth in bytes))
  646. * Must be less than tu_size.
  647. */
  648. in_bw = mode->clock * bits_per_pixel / 8;
  649. out_bw = tc->link.num_lanes * tc->link.rate;
  650. max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
  651. dev_dbg(tc->dev, "set mode %dx%d\n",
  652. mode->hdisplay, mode->vdisplay);
  653. dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
  654. left_margin, right_margin, hsync_len);
  655. dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
  656. upper_margin, lower_margin, vsync_len);
  657. dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
  658. /*
  659. * LCD Ctl Frame Size
  660. * datasheet is not clear of vsdelay in case of DPI
  661. * assume we do not need any delay when DPI is a source of
  662. * sync signals
  663. */
  664. ret = regmap_write(tc->regmap, VPCTRL0,
  665. FIELD_PREP(VSDELAY, 0) |
  666. OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
  667. if (ret)
  668. return ret;
  669. ret = regmap_write(tc->regmap, HTIM01,
  670. FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
  671. FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
  672. if (ret)
  673. return ret;
  674. ret = regmap_write(tc->regmap, HTIM02,
  675. FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
  676. FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
  677. if (ret)
  678. return ret;
  679. ret = regmap_write(tc->regmap, VTIM01,
  680. FIELD_PREP(VBPR, upper_margin) |
  681. FIELD_PREP(VSPR, vsync_len));
  682. if (ret)
  683. return ret;
  684. ret = regmap_write(tc->regmap, VTIM02,
  685. FIELD_PREP(VFPR, lower_margin) |
  686. FIELD_PREP(VDISPR, mode->vdisplay));
  687. if (ret)
  688. return ret;
  689. ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
  690. if (ret)
  691. return ret;
  692. /* Test pattern settings */
  693. ret = regmap_write(tc->regmap, TSTCTL,
  694. FIELD_PREP(COLOR_R, 120) |
  695. FIELD_PREP(COLOR_G, 20) |
  696. FIELD_PREP(COLOR_B, 99) |
  697. ENI2CFILTER |
  698. FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
  699. if (ret)
  700. return ret;
  701. /* DP Main Stream Attributes */
  702. vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
  703. ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
  704. FIELD_PREP(THRESH_DLY, max_tu_symbol) |
  705. FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
  706. ret = regmap_write(tc->regmap, DP0_TOTALVAL,
  707. FIELD_PREP(H_TOTAL, mode->htotal) |
  708. FIELD_PREP(V_TOTAL, mode->vtotal));
  709. if (ret)
  710. return ret;
  711. ret = regmap_write(tc->regmap, DP0_STARTVAL,
  712. FIELD_PREP(H_START, left_margin + hsync_len) |
  713. FIELD_PREP(V_START, upper_margin + vsync_len));
  714. if (ret)
  715. return ret;
  716. ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
  717. FIELD_PREP(V_ACT, mode->vdisplay) |
  718. FIELD_PREP(H_ACT, mode->hdisplay));
  719. if (ret)
  720. return ret;
  721. dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
  722. FIELD_PREP(HS_WIDTH, hsync_len);
  723. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  724. dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
  725. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  726. dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
  727. ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
  728. if (ret)
  729. return ret;
  730. ret = regmap_write(tc->regmap, DPIPXLFMT,
  731. VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
  732. DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 |
  733. DPI_BPP_RGB888);
  734. if (ret)
  735. return ret;
  736. ret = regmap_write(tc->regmap, DP0_MISC,
  737. FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
  738. FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
  739. BPC_8);
  740. if (ret)
  741. return ret;
  742. return 0;
  743. }
  744. static int tc_wait_link_training(struct tc_data *tc)
  745. {
  746. u32 value;
  747. int ret;
  748. ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
  749. LT_LOOPDONE, 500, 100000);
  750. if (ret) {
  751. dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
  752. return ret;
  753. }
  754. ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
  755. if (ret)
  756. return ret;
  757. return (value >> 8) & 0x7;
  758. }
  759. static int tc_main_link_enable(struct tc_data *tc)
  760. {
  761. struct drm_dp_aux *aux = &tc->aux;
  762. struct device *dev = tc->dev;
  763. u32 dp_phy_ctrl;
  764. u32 value;
  765. int ret;
  766. u8 tmp[DP_LINK_STATUS_SIZE];
  767. dev_dbg(tc->dev, "link enable\n");
  768. ret = regmap_read(tc->regmap, DP0CTL, &value);
  769. if (ret)
  770. return ret;
  771. if (WARN_ON(value & DP_EN)) {
  772. ret = regmap_write(tc->regmap, DP0CTL, 0);
  773. if (ret)
  774. return ret;
  775. }
  776. ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
  777. if (ret)
  778. return ret;
  779. /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
  780. ret = regmap_write(tc->regmap, DP1_SRCCTRL,
  781. (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
  782. ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
  783. if (ret)
  784. return ret;
  785. ret = tc_set_syspllparam(tc);
  786. if (ret)
  787. return ret;
  788. /* Setup Main Link */
  789. dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
  790. if (tc->link.num_lanes == 2)
  791. dp_phy_ctrl |= PHY_2LANE;
  792. ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
  793. if (ret)
  794. return ret;
  795. /* PLL setup */
  796. ret = tc_pllupdate(tc, DP0_PLLCTRL);
  797. if (ret)
  798. return ret;
  799. ret = tc_pllupdate(tc, DP1_PLLCTRL);
  800. if (ret)
  801. return ret;
  802. /* Reset/Enable Main Links */
  803. dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
  804. ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
  805. usleep_range(100, 200);
  806. dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
  807. ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
  808. ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
  809. if (ret) {
  810. dev_err(dev, "timeout waiting for phy become ready");
  811. return ret;
  812. }
  813. /* Set misc: 8 bits per color */
  814. ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
  815. if (ret)
  816. return ret;
  817. /*
  818. * ASSR mode
  819. * on TC358767 side ASSR configured through strap pin
  820. * seems there is no way to change this setting from SW
  821. *
  822. * check is tc configured for same mode
  823. */
  824. if (tc->assr != tc->link.assr) {
  825. dev_dbg(dev, "Trying to set display to ASSR: %d\n",
  826. tc->assr);
  827. /* try to set ASSR on display side */
  828. tmp[0] = tc->assr;
  829. ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
  830. if (ret < 0)
  831. goto err_dpcd_read;
  832. /* read back */
  833. ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
  834. if (ret < 0)
  835. goto err_dpcd_read;
  836. if (tmp[0] != tc->assr) {
  837. dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
  838. tc->assr);
  839. /* trying with disabled scrambler */
  840. tc->link.scrambler_dis = true;
  841. }
  842. }
  843. /* Setup Link & DPRx Config for Training */
  844. tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
  845. tmp[1] = tc->link.num_lanes;
  846. if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
  847. tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  848. ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
  849. if (ret < 0)
  850. goto err_dpcd_write;
  851. /* DOWNSPREAD_CTRL */
  852. tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
  853. /* MAIN_LINK_CHANNEL_CODING_SET */
  854. tmp[1] = DP_SET_ANSI_8B10B;
  855. ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
  856. if (ret < 0)
  857. goto err_dpcd_write;
  858. /* Reset voltage-swing & pre-emphasis */
  859. tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
  860. DP_TRAIN_PRE_EMPH_LEVEL_0;
  861. ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
  862. if (ret < 0)
  863. goto err_dpcd_write;
  864. /* Clock-Recovery */
  865. /* Set DPCD 0x102 for Training Pattern 1 */
  866. ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
  867. DP_LINK_SCRAMBLING_DISABLE |
  868. DP_TRAINING_PATTERN_1);
  869. if (ret)
  870. return ret;
  871. ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
  872. (15 << 28) | /* Defer Iteration Count */
  873. (15 << 24) | /* Loop Iteration Count */
  874. (0xd << 0)); /* Loop Timer Delay */
  875. if (ret)
  876. return ret;
  877. ret = regmap_write(tc->regmap, DP0_SRCCTRL,
  878. tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
  879. DP0_SRCCTRL_AUTOCORRECT |
  880. DP0_SRCCTRL_TP1);
  881. if (ret)
  882. return ret;
  883. /* Enable DP0 to start Link Training */
  884. ret = regmap_write(tc->regmap, DP0CTL,
  885. (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
  886. EF_EN : 0) | DP_EN);
  887. if (ret)
  888. return ret;
  889. /* wait */
  890. ret = tc_wait_link_training(tc);
  891. if (ret < 0)
  892. return ret;
  893. if (ret) {
  894. dev_err(tc->dev, "Link training phase 1 failed: %s\n",
  895. training_pattern1_errors[ret]);
  896. return -ENODEV;
  897. }
  898. /* Channel Equalization */
  899. /* Set DPCD 0x102 for Training Pattern 2 */
  900. ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
  901. DP_LINK_SCRAMBLING_DISABLE |
  902. DP_TRAINING_PATTERN_2);
  903. if (ret)
  904. return ret;
  905. ret = regmap_write(tc->regmap, DP0_SRCCTRL,
  906. tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
  907. DP0_SRCCTRL_AUTOCORRECT |
  908. DP0_SRCCTRL_TP2);
  909. if (ret)
  910. return ret;
  911. /* wait */
  912. ret = tc_wait_link_training(tc);
  913. if (ret < 0)
  914. return ret;
  915. if (ret) {
  916. dev_err(tc->dev, "Link training phase 2 failed: %s\n",
  917. training_pattern2_errors[ret]);
  918. return -ENODEV;
  919. }
  920. /*
  921. * Toshiba's documentation suggests to first clear DPCD 0x102, then
  922. * clear the training pattern bit in DP0_SRCCTRL. Testing shows
  923. * that the link sometimes drops if those steps are done in that order,
  924. * but if the steps are done in reverse order, the link stays up.
  925. *
  926. * So we do the steps differently than documented here.
  927. */
  928. /* Clear Training Pattern, set AutoCorrect Mode = 1 */
  929. ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
  930. DP0_SRCCTRL_AUTOCORRECT);
  931. if (ret)
  932. return ret;
  933. /* Clear DPCD 0x102 */
  934. /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
  935. tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
  936. ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
  937. if (ret < 0)
  938. goto err_dpcd_write;
  939. /* Check link status */
  940. ret = drm_dp_dpcd_read_link_status(aux, tmp);
  941. if (ret < 0)
  942. goto err_dpcd_read;
  943. ret = 0;
  944. value = tmp[0] & DP_CHANNEL_EQ_BITS;
  945. if (value != DP_CHANNEL_EQ_BITS) {
  946. dev_err(tc->dev, "Lane 0 failed: %x\n", value);
  947. ret = -ENODEV;
  948. }
  949. if (tc->link.num_lanes == 2) {
  950. value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
  951. if (value != DP_CHANNEL_EQ_BITS) {
  952. dev_err(tc->dev, "Lane 1 failed: %x\n", value);
  953. ret = -ENODEV;
  954. }
  955. if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
  956. dev_err(tc->dev, "Interlane align failed\n");
  957. ret = -ENODEV;
  958. }
  959. }
  960. if (ret) {
  961. dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]);
  962. dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]);
  963. dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
  964. dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]);
  965. dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]);
  966. dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]);
  967. return ret;
  968. }
  969. return 0;
  970. err_dpcd_read:
  971. dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
  972. return ret;
  973. err_dpcd_write:
  974. dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
  975. return ret;
  976. }
  977. static int tc_main_link_disable(struct tc_data *tc)
  978. {
  979. int ret;
  980. dev_dbg(tc->dev, "link disable\n");
  981. ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
  982. if (ret)
  983. return ret;
  984. return regmap_write(tc->regmap, DP0CTL, 0);
  985. }
  986. static int tc_stream_enable(struct tc_data *tc)
  987. {
  988. int ret;
  989. u32 value;
  990. dev_dbg(tc->dev, "enable video stream\n");
  991. /* PXL PLL setup */
  992. if (tc_test_pattern) {
  993. ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
  994. 1000 * tc->mode.clock);
  995. if (ret)
  996. return ret;
  997. }
  998. ret = tc_set_video_mode(tc, &tc->mode);
  999. if (ret)
  1000. return ret;
  1001. /* Set M/N */
  1002. ret = tc_stream_clock_calc(tc);
  1003. if (ret)
  1004. return ret;
  1005. value = VID_MN_GEN | DP_EN;
  1006. if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
  1007. value |= EF_EN;
  1008. ret = regmap_write(tc->regmap, DP0CTL, value);
  1009. if (ret)
  1010. return ret;
  1011. /*
  1012. * VID_EN assertion should be delayed by at least N * LSCLK
  1013. * cycles from the time VID_MN_GEN is enabled in order to
  1014. * generate stable values for VID_M. LSCLK is 270 MHz or
  1015. * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
  1016. * so a delay of at least 203 us should suffice.
  1017. */
  1018. usleep_range(500, 1000);
  1019. value |= VID_EN;
  1020. ret = regmap_write(tc->regmap, DP0CTL, value);
  1021. if (ret)
  1022. return ret;
  1023. /* Set input interface */
  1024. value = DP0_AUDSRC_NO_INPUT;
  1025. if (tc_test_pattern)
  1026. value |= DP0_VIDSRC_COLOR_BAR;
  1027. else
  1028. value |= DP0_VIDSRC_DPI_RX;
  1029. ret = regmap_write(tc->regmap, SYSCTRL, value);
  1030. if (ret)
  1031. return ret;
  1032. return 0;
  1033. }
  1034. static int tc_stream_disable(struct tc_data *tc)
  1035. {
  1036. int ret;
  1037. dev_dbg(tc->dev, "disable video stream\n");
  1038. ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
  1039. if (ret)
  1040. return ret;
  1041. tc_pxl_pll_dis(tc);
  1042. return 0;
  1043. }
  1044. static void tc_bridge_enable(struct drm_bridge *bridge)
  1045. {
  1046. struct tc_data *tc = bridge_to_tc(bridge);
  1047. int ret;
  1048. ret = tc_get_display_props(tc);
  1049. if (ret < 0) {
  1050. dev_err(tc->dev, "failed to read display props: %d\n", ret);
  1051. return;
  1052. }
  1053. ret = tc_main_link_enable(tc);
  1054. if (ret < 0) {
  1055. dev_err(tc->dev, "main link enable error: %d\n", ret);
  1056. return;
  1057. }
  1058. ret = tc_stream_enable(tc);
  1059. if (ret < 0) {
  1060. dev_err(tc->dev, "main link stream start error: %d\n", ret);
  1061. tc_main_link_disable(tc);
  1062. return;
  1063. }
  1064. }
  1065. static void tc_bridge_disable(struct drm_bridge *bridge)
  1066. {
  1067. struct tc_data *tc = bridge_to_tc(bridge);
  1068. int ret;
  1069. ret = tc_stream_disable(tc);
  1070. if (ret < 0)
  1071. dev_err(tc->dev, "main link stream stop error: %d\n", ret);
  1072. ret = tc_main_link_disable(tc);
  1073. if (ret < 0)
  1074. dev_err(tc->dev, "main link disable error: %d\n", ret);
  1075. }
  1076. static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
  1077. const struct drm_display_mode *mode,
  1078. struct drm_display_mode *adj)
  1079. {
  1080. /* Fixup sync polarities, both hsync and vsync are active low */
  1081. adj->flags = mode->flags;
  1082. adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
  1083. adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  1084. return true;
  1085. }
  1086. static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
  1087. const struct drm_display_info *info,
  1088. const struct drm_display_mode *mode)
  1089. {
  1090. struct tc_data *tc = bridge_to_tc(bridge);
  1091. u32 req, avail;
  1092. u32 bits_per_pixel = 24;
  1093. /* DPI interface clock limitation: upto 154 MHz */
  1094. if (mode->clock > 154000)
  1095. return MODE_CLOCK_HIGH;
  1096. req = mode->clock * bits_per_pixel / 8;
  1097. avail = tc->link.num_lanes * tc->link.rate;
  1098. if (req > avail)
  1099. return MODE_BAD;
  1100. return MODE_OK;
  1101. }
  1102. static void tc_bridge_mode_set(struct drm_bridge *bridge,
  1103. const struct drm_display_mode *mode,
  1104. const struct drm_display_mode *adj)
  1105. {
  1106. struct tc_data *tc = bridge_to_tc(bridge);
  1107. tc->mode = *mode;
  1108. }
  1109. static struct edid *tc_get_edid(struct drm_bridge *bridge,
  1110. struct drm_connector *connector)
  1111. {
  1112. struct tc_data *tc = bridge_to_tc(bridge);
  1113. return drm_get_edid(connector, &tc->aux.ddc);
  1114. }
  1115. static int tc_connector_get_modes(struct drm_connector *connector)
  1116. {
  1117. struct tc_data *tc = connector_to_tc(connector);
  1118. int num_modes;
  1119. struct edid *edid;
  1120. int ret;
  1121. ret = tc_get_display_props(tc);
  1122. if (ret < 0) {
  1123. dev_err(tc->dev, "failed to read display props: %d\n", ret);
  1124. return 0;
  1125. }
  1126. if (tc->panel_bridge) {
  1127. num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
  1128. if (num_modes > 0)
  1129. return num_modes;
  1130. }
  1131. edid = tc_get_edid(&tc->bridge, connector);
  1132. num_modes = drm_add_edid_modes(connector, edid);
  1133. kfree(edid);
  1134. return num_modes;
  1135. }
  1136. static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
  1137. .get_modes = tc_connector_get_modes,
  1138. };
  1139. static enum drm_connector_status tc_bridge_detect(struct drm_bridge *bridge)
  1140. {
  1141. struct tc_data *tc = bridge_to_tc(bridge);
  1142. bool conn;
  1143. u32 val;
  1144. int ret;
  1145. ret = regmap_read(tc->regmap, GPIOI, &val);
  1146. if (ret)
  1147. return connector_status_unknown;
  1148. conn = val & BIT(tc->hpd_pin);
  1149. if (conn)
  1150. return connector_status_connected;
  1151. else
  1152. return connector_status_disconnected;
  1153. }
  1154. static enum drm_connector_status
  1155. tc_connector_detect(struct drm_connector *connector, bool force)
  1156. {
  1157. struct tc_data *tc = connector_to_tc(connector);
  1158. if (tc->hpd_pin >= 0)
  1159. return tc_bridge_detect(&tc->bridge);
  1160. if (tc->panel_bridge)
  1161. return connector_status_connected;
  1162. else
  1163. return connector_status_unknown;
  1164. }
  1165. static const struct drm_connector_funcs tc_connector_funcs = {
  1166. .detect = tc_connector_detect,
  1167. .fill_modes = drm_helper_probe_single_connector_modes,
  1168. .destroy = drm_connector_cleanup,
  1169. .reset = drm_atomic_helper_connector_reset,
  1170. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  1171. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  1172. };
  1173. static int tc_bridge_attach(struct drm_bridge *bridge,
  1174. enum drm_bridge_attach_flags flags)
  1175. {
  1176. u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  1177. struct tc_data *tc = bridge_to_tc(bridge);
  1178. struct drm_device *drm = bridge->dev;
  1179. int ret;
  1180. if (tc->panel_bridge) {
  1181. /* If a connector is required then this driver shall create it */
  1182. ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
  1183. &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
  1184. if (ret)
  1185. return ret;
  1186. }
  1187. if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
  1188. return 0;
  1189. /* Create DP/eDP connector */
  1190. drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
  1191. ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
  1192. if (ret)
  1193. return ret;
  1194. /* Don't poll if don't have HPD connected */
  1195. if (tc->hpd_pin >= 0) {
  1196. if (tc->have_irq)
  1197. tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
  1198. else
  1199. tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
  1200. DRM_CONNECTOR_POLL_DISCONNECT;
  1201. }
  1202. drm_display_info_set_bus_formats(&tc->connector.display_info,
  1203. &bus_format, 1);
  1204. tc->connector.display_info.bus_flags =
  1205. DRM_BUS_FLAG_DE_HIGH |
  1206. DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
  1207. DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
  1208. drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
  1209. return 0;
  1210. }
  1211. static const struct drm_bridge_funcs tc_bridge_funcs = {
  1212. .attach = tc_bridge_attach,
  1213. .mode_valid = tc_mode_valid,
  1214. .mode_set = tc_bridge_mode_set,
  1215. .enable = tc_bridge_enable,
  1216. .disable = tc_bridge_disable,
  1217. .mode_fixup = tc_bridge_mode_fixup,
  1218. .detect = tc_bridge_detect,
  1219. .get_edid = tc_get_edid,
  1220. };
  1221. static bool tc_readable_reg(struct device *dev, unsigned int reg)
  1222. {
  1223. return reg != SYSCTRL;
  1224. }
  1225. static const struct regmap_range tc_volatile_ranges[] = {
  1226. regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
  1227. regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
  1228. regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
  1229. regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
  1230. regmap_reg_range(VFUEN0, VFUEN0),
  1231. regmap_reg_range(INTSTS_G, INTSTS_G),
  1232. regmap_reg_range(GPIOI, GPIOI),
  1233. };
  1234. static const struct regmap_access_table tc_volatile_table = {
  1235. .yes_ranges = tc_volatile_ranges,
  1236. .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
  1237. };
  1238. static bool tc_writeable_reg(struct device *dev, unsigned int reg)
  1239. {
  1240. return (reg != TC_IDREG) &&
  1241. (reg != DP0_LTSTAT) &&
  1242. (reg != DP0_SNKLTCHGREQ);
  1243. }
  1244. static const struct regmap_config tc_regmap_config = {
  1245. .name = "tc358767",
  1246. .reg_bits = 16,
  1247. .val_bits = 32,
  1248. .reg_stride = 4,
  1249. .max_register = PLL_DBG,
  1250. .cache_type = REGCACHE_RBTREE,
  1251. .readable_reg = tc_readable_reg,
  1252. .volatile_table = &tc_volatile_table,
  1253. .writeable_reg = tc_writeable_reg,
  1254. .reg_format_endian = REGMAP_ENDIAN_BIG,
  1255. .val_format_endian = REGMAP_ENDIAN_LITTLE,
  1256. };
  1257. static irqreturn_t tc_irq_handler(int irq, void *arg)
  1258. {
  1259. struct tc_data *tc = arg;
  1260. u32 val;
  1261. int r;
  1262. r = regmap_read(tc->regmap, INTSTS_G, &val);
  1263. if (r)
  1264. return IRQ_NONE;
  1265. if (!val)
  1266. return IRQ_NONE;
  1267. if (val & INT_SYSERR) {
  1268. u32 stat = 0;
  1269. regmap_read(tc->regmap, SYSSTAT, &stat);
  1270. dev_err(tc->dev, "syserr %x\n", stat);
  1271. }
  1272. if (tc->hpd_pin >= 0 && tc->bridge.dev) {
  1273. /*
  1274. * H is triggered when the GPIO goes high.
  1275. *
  1276. * LC is triggered when the GPIO goes low and stays low for
  1277. * the duration of LCNT
  1278. */
  1279. bool h = val & INT_GPIO_H(tc->hpd_pin);
  1280. bool lc = val & INT_GPIO_LC(tc->hpd_pin);
  1281. dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
  1282. h ? "H" : "", lc ? "LC" : "");
  1283. if (h || lc)
  1284. drm_kms_helper_hotplug_event(tc->bridge.dev);
  1285. }
  1286. regmap_write(tc->regmap, INTSTS_G, val);
  1287. return IRQ_HANDLED;
  1288. }
  1289. static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
  1290. {
  1291. struct device *dev = &client->dev;
  1292. struct drm_panel *panel;
  1293. struct tc_data *tc;
  1294. int ret;
  1295. tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
  1296. if (!tc)
  1297. return -ENOMEM;
  1298. tc->dev = dev;
  1299. /* port@2 is the output port */
  1300. ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL);
  1301. if (ret && ret != -ENODEV)
  1302. return ret;
  1303. if (panel) {
  1304. struct drm_bridge *panel_bridge;
  1305. panel_bridge = devm_drm_panel_bridge_add(dev, panel);
  1306. if (IS_ERR(panel_bridge))
  1307. return PTR_ERR(panel_bridge);
  1308. tc->panel_bridge = panel_bridge;
  1309. tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
  1310. } else {
  1311. tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
  1312. }
  1313. /* Shut down GPIO is optional */
  1314. tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
  1315. if (IS_ERR(tc->sd_gpio))
  1316. return PTR_ERR(tc->sd_gpio);
  1317. if (tc->sd_gpio) {
  1318. gpiod_set_value_cansleep(tc->sd_gpio, 0);
  1319. usleep_range(5000, 10000);
  1320. }
  1321. /* Reset GPIO is optional */
  1322. tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
  1323. if (IS_ERR(tc->reset_gpio))
  1324. return PTR_ERR(tc->reset_gpio);
  1325. if (tc->reset_gpio) {
  1326. gpiod_set_value_cansleep(tc->reset_gpio, 1);
  1327. usleep_range(5000, 10000);
  1328. }
  1329. tc->refclk = devm_clk_get(dev, "ref");
  1330. if (IS_ERR(tc->refclk)) {
  1331. ret = PTR_ERR(tc->refclk);
  1332. dev_err(dev, "Failed to get refclk: %d\n", ret);
  1333. return ret;
  1334. }
  1335. tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
  1336. if (IS_ERR(tc->regmap)) {
  1337. ret = PTR_ERR(tc->regmap);
  1338. dev_err(dev, "Failed to initialize regmap: %d\n", ret);
  1339. return ret;
  1340. }
  1341. ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
  1342. &tc->hpd_pin);
  1343. if (ret) {
  1344. tc->hpd_pin = -ENODEV;
  1345. } else {
  1346. if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
  1347. dev_err(dev, "failed to parse HPD number\n");
  1348. return ret;
  1349. }
  1350. }
  1351. if (client->irq > 0) {
  1352. /* enable SysErr */
  1353. regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
  1354. ret = devm_request_threaded_irq(dev, client->irq,
  1355. NULL, tc_irq_handler,
  1356. IRQF_ONESHOT,
  1357. "tc358767-irq", tc);
  1358. if (ret) {
  1359. dev_err(dev, "failed to register dp interrupt\n");
  1360. return ret;
  1361. }
  1362. tc->have_irq = true;
  1363. }
  1364. ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
  1365. if (ret) {
  1366. dev_err(tc->dev, "can not read device ID: %d\n", ret);
  1367. return ret;
  1368. }
  1369. if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
  1370. dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
  1371. return -EINVAL;
  1372. }
  1373. tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
  1374. if (!tc->reset_gpio) {
  1375. /*
  1376. * If the reset pin isn't present, do a software reset. It isn't
  1377. * as thorough as the hardware reset, as we can't reset the I2C
  1378. * communication block for obvious reasons, but it's getting the
  1379. * chip into a defined state.
  1380. */
  1381. regmap_update_bits(tc->regmap, SYSRSTENB,
  1382. ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
  1383. 0);
  1384. regmap_update_bits(tc->regmap, SYSRSTENB,
  1385. ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
  1386. ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
  1387. usleep_range(5000, 10000);
  1388. }
  1389. if (tc->hpd_pin >= 0) {
  1390. u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
  1391. u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
  1392. /* Set LCNT to 2ms */
  1393. regmap_write(tc->regmap, lcnt_reg,
  1394. clk_get_rate(tc->refclk) * 2 / 1000);
  1395. /* We need the "alternate" mode for HPD */
  1396. regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
  1397. if (tc->have_irq) {
  1398. /* enable H & LC */
  1399. regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
  1400. }
  1401. }
  1402. ret = tc_aux_link_setup(tc);
  1403. if (ret)
  1404. return ret;
  1405. /* Register DP AUX channel */
  1406. tc->aux.name = "TC358767 AUX i2c adapter";
  1407. tc->aux.dev = tc->dev;
  1408. tc->aux.transfer = tc_aux_transfer;
  1409. ret = drm_dp_aux_register(&tc->aux);
  1410. if (ret)
  1411. return ret;
  1412. tc->bridge.funcs = &tc_bridge_funcs;
  1413. if (tc->hpd_pin >= 0)
  1414. tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
  1415. tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
  1416. tc->bridge.of_node = dev->of_node;
  1417. drm_bridge_add(&tc->bridge);
  1418. i2c_set_clientdata(client, tc);
  1419. return 0;
  1420. }
  1421. static int tc_remove(struct i2c_client *client)
  1422. {
  1423. struct tc_data *tc = i2c_get_clientdata(client);
  1424. drm_bridge_remove(&tc->bridge);
  1425. drm_dp_aux_unregister(&tc->aux);
  1426. return 0;
  1427. }
  1428. static const struct i2c_device_id tc358767_i2c_ids[] = {
  1429. { "tc358767", 0 },
  1430. { }
  1431. };
  1432. MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
  1433. static const struct of_device_id tc358767_of_ids[] = {
  1434. { .compatible = "toshiba,tc358767", },
  1435. { }
  1436. };
  1437. MODULE_DEVICE_TABLE(of, tc358767_of_ids);
  1438. static struct i2c_driver tc358767_driver = {
  1439. .driver = {
  1440. .name = "tc358767",
  1441. .of_match_table = tc358767_of_ids,
  1442. },
  1443. .id_table = tc358767_i2c_ids,
  1444. .probe = tc_probe,
  1445. .remove = tc_remove,
  1446. };
  1447. module_i2c_driver(tc358767_driver);
  1448. MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
  1449. MODULE_DESCRIPTION("tc358767 eDP encoder driver");
  1450. MODULE_LICENSE("GPL");