dw-mipi-dsi.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
  4. * Copyright (C) STMicroelectronics SA 2017
  5. *
  6. * Modified by Philippe Cornu <philippe.cornu@st.com>
  7. * This generic Synopsys DesignWare MIPI DSI host driver is based on the
  8. * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/component.h>
  12. #include <linux/debugfs.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/module.h>
  15. #include <linux/of_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/reset.h>
  18. #include <video/mipi_display.h>
  19. #include <drm/bridge/dw_mipi_dsi.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_bridge.h>
  22. #include <drm/drm_crtc.h>
  23. #include <drm/drm_mipi_dsi.h>
  24. #include <drm/drm_modes.h>
  25. #include <drm/drm_of.h>
  26. #include <drm/drm_print.h>
  27. #define HWVER_131 0x31333100 /* IP version 1.31 */
  28. #define DSI_VERSION 0x00
  29. #define VERSION GENMASK(31, 8)
  30. #define DSI_PWR_UP 0x04
  31. #define RESET 0
  32. #define POWERUP BIT(0)
  33. #define DSI_CLKMGR_CFG 0x08
  34. #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
  35. #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
  36. #define DSI_DPI_VCID 0x0c
  37. #define DPI_VCID(vcid) ((vcid) & 0x3)
  38. #define DSI_DPI_COLOR_CODING 0x10
  39. #define LOOSELY18_EN BIT(8)
  40. #define DPI_COLOR_CODING_16BIT_1 0x0
  41. #define DPI_COLOR_CODING_16BIT_2 0x1
  42. #define DPI_COLOR_CODING_16BIT_3 0x2
  43. #define DPI_COLOR_CODING_18BIT_1 0x3
  44. #define DPI_COLOR_CODING_18BIT_2 0x4
  45. #define DPI_COLOR_CODING_24BIT 0x5
  46. #define DSI_DPI_CFG_POL 0x14
  47. #define COLORM_ACTIVE_LOW BIT(4)
  48. #define SHUTD_ACTIVE_LOW BIT(3)
  49. #define HSYNC_ACTIVE_LOW BIT(2)
  50. #define VSYNC_ACTIVE_LOW BIT(1)
  51. #define DATAEN_ACTIVE_LOW BIT(0)
  52. #define DSI_DPI_LP_CMD_TIM 0x18
  53. #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
  54. #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
  55. #define DSI_DBI_VCID 0x1c
  56. #define DSI_DBI_CFG 0x20
  57. #define DSI_DBI_PARTITIONING_EN 0x24
  58. #define DSI_DBI_CMDSIZE 0x28
  59. #define DSI_PCKHDL_CFG 0x2c
  60. #define CRC_RX_EN BIT(4)
  61. #define ECC_RX_EN BIT(3)
  62. #define BTA_EN BIT(2)
  63. #define EOTP_RX_EN BIT(1)
  64. #define EOTP_TX_EN BIT(0)
  65. #define DSI_GEN_VCID 0x30
  66. #define DSI_MODE_CFG 0x34
  67. #define ENABLE_VIDEO_MODE 0
  68. #define ENABLE_CMD_MODE BIT(0)
  69. #define DSI_VID_MODE_CFG 0x38
  70. #define ENABLE_LOW_POWER (0x3f << 8)
  71. #define ENABLE_LOW_POWER_MASK (0x3f << 8)
  72. #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
  73. #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
  74. #define VID_MODE_TYPE_BURST 0x2
  75. #define VID_MODE_TYPE_MASK 0x3
  76. #define ENABLE_LOW_POWER_CMD BIT(15)
  77. #define VID_MODE_VPG_ENABLE BIT(16)
  78. #define VID_MODE_VPG_MODE BIT(20)
  79. #define VID_MODE_VPG_HORIZONTAL BIT(24)
  80. #define DSI_VID_PKT_SIZE 0x3c
  81. #define VID_PKT_SIZE(p) ((p) & 0x3fff)
  82. #define DSI_VID_NUM_CHUNKS 0x40
  83. #define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
  84. #define DSI_VID_NULL_SIZE 0x44
  85. #define VID_NULL_SIZE(b) ((b) & 0x1fff)
  86. #define DSI_VID_HSA_TIME 0x48
  87. #define DSI_VID_HBP_TIME 0x4c
  88. #define DSI_VID_HLINE_TIME 0x50
  89. #define DSI_VID_VSA_LINES 0x54
  90. #define DSI_VID_VBP_LINES 0x58
  91. #define DSI_VID_VFP_LINES 0x5c
  92. #define DSI_VID_VACTIVE_LINES 0x60
  93. #define DSI_EDPI_CMD_SIZE 0x64
  94. #define DSI_CMD_MODE_CFG 0x68
  95. #define MAX_RD_PKT_SIZE_LP BIT(24)
  96. #define DCS_LW_TX_LP BIT(19)
  97. #define DCS_SR_0P_TX_LP BIT(18)
  98. #define DCS_SW_1P_TX_LP BIT(17)
  99. #define DCS_SW_0P_TX_LP BIT(16)
  100. #define GEN_LW_TX_LP BIT(14)
  101. #define GEN_SR_2P_TX_LP BIT(13)
  102. #define GEN_SR_1P_TX_LP BIT(12)
  103. #define GEN_SR_0P_TX_LP BIT(11)
  104. #define GEN_SW_2P_TX_LP BIT(10)
  105. #define GEN_SW_1P_TX_LP BIT(9)
  106. #define GEN_SW_0P_TX_LP BIT(8)
  107. #define ACK_RQST_EN BIT(1)
  108. #define TEAR_FX_EN BIT(0)
  109. #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
  110. DCS_LW_TX_LP | \
  111. DCS_SR_0P_TX_LP | \
  112. DCS_SW_1P_TX_LP | \
  113. DCS_SW_0P_TX_LP | \
  114. GEN_LW_TX_LP | \
  115. GEN_SR_2P_TX_LP | \
  116. GEN_SR_1P_TX_LP | \
  117. GEN_SR_0P_TX_LP | \
  118. GEN_SW_2P_TX_LP | \
  119. GEN_SW_1P_TX_LP | \
  120. GEN_SW_0P_TX_LP)
  121. #define DSI_GEN_HDR 0x6c
  122. #define DSI_GEN_PLD_DATA 0x70
  123. #define DSI_CMD_PKT_STATUS 0x74
  124. #define GEN_RD_CMD_BUSY BIT(6)
  125. #define GEN_PLD_R_FULL BIT(5)
  126. #define GEN_PLD_R_EMPTY BIT(4)
  127. #define GEN_PLD_W_FULL BIT(3)
  128. #define GEN_PLD_W_EMPTY BIT(2)
  129. #define GEN_CMD_FULL BIT(1)
  130. #define GEN_CMD_EMPTY BIT(0)
  131. #define DSI_TO_CNT_CFG 0x78
  132. #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
  133. #define LPRX_TO_CNT(p) ((p) & 0xffff)
  134. #define DSI_HS_RD_TO_CNT 0x7c
  135. #define DSI_LP_RD_TO_CNT 0x80
  136. #define DSI_HS_WR_TO_CNT 0x84
  137. #define DSI_LP_WR_TO_CNT 0x88
  138. #define DSI_BTA_TO_CNT 0x8c
  139. #define DSI_LPCLK_CTRL 0x94
  140. #define AUTO_CLKLANE_CTRL BIT(1)
  141. #define PHY_TXREQUESTCLKHS BIT(0)
  142. #define DSI_PHY_TMR_LPCLK_CFG 0x98
  143. #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
  144. #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
  145. #define DSI_PHY_TMR_CFG 0x9c
  146. #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
  147. #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
  148. #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
  149. #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
  150. #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
  151. #define DSI_PHY_RSTZ 0xa0
  152. #define PHY_DISFORCEPLL 0
  153. #define PHY_ENFORCEPLL BIT(3)
  154. #define PHY_DISABLECLK 0
  155. #define PHY_ENABLECLK BIT(2)
  156. #define PHY_RSTZ 0
  157. #define PHY_UNRSTZ BIT(1)
  158. #define PHY_SHUTDOWNZ 0
  159. #define PHY_UNSHUTDOWNZ BIT(0)
  160. #define DSI_PHY_IF_CFG 0xa4
  161. #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
  162. #define N_LANES(n) (((n) - 1) & 0x3)
  163. #define DSI_PHY_ULPS_CTRL 0xa8
  164. #define DSI_PHY_TX_TRIGGERS 0xac
  165. #define DSI_PHY_STATUS 0xb0
  166. #define PHY_STOP_STATE_CLK_LANE BIT(2)
  167. #define PHY_LOCK BIT(0)
  168. #define DSI_PHY_TST_CTRL0 0xb4
  169. #define PHY_TESTCLK BIT(1)
  170. #define PHY_UNTESTCLK 0
  171. #define PHY_TESTCLR BIT(0)
  172. #define PHY_UNTESTCLR 0
  173. #define DSI_PHY_TST_CTRL1 0xb8
  174. #define PHY_TESTEN BIT(16)
  175. #define PHY_UNTESTEN 0
  176. #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
  177. #define PHY_TESTDIN(n) ((n) & 0xff)
  178. #define DSI_INT_ST0 0xbc
  179. #define DSI_INT_ST1 0xc0
  180. #define DSI_INT_MSK0 0xc4
  181. #define DSI_INT_MSK1 0xc8
  182. #define DSI_PHY_TMR_RD_CFG 0xf4
  183. #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
  184. #define PHY_STATUS_TIMEOUT_US 10000
  185. #define CMD_PKT_STATUS_TIMEOUT_US 20000
  186. #ifdef CONFIG_DEBUG_FS
  187. #define VPG_DEFS(name, dsi) \
  188. ((void __force *)&((*dsi).vpg_defs.name))
  189. #define REGISTER(name, mask, dsi) \
  190. { #name, VPG_DEFS(name, dsi), mask, dsi }
  191. struct debugfs_entries {
  192. const char *name;
  193. bool *reg;
  194. u32 mask;
  195. struct dw_mipi_dsi *dsi;
  196. };
  197. #endif /* CONFIG_DEBUG_FS */
  198. struct dw_mipi_dsi {
  199. struct drm_bridge bridge;
  200. struct mipi_dsi_host dsi_host;
  201. struct drm_bridge *panel_bridge;
  202. struct device *dev;
  203. void __iomem *base;
  204. struct clk *pclk;
  205. unsigned int lane_mbps; /* per lane */
  206. u32 channel;
  207. u32 lanes;
  208. u32 format;
  209. unsigned long mode_flags;
  210. #ifdef CONFIG_DEBUG_FS
  211. struct dentry *debugfs;
  212. struct debugfs_entries *debugfs_vpg;
  213. struct {
  214. bool vpg;
  215. bool vpg_horizontal;
  216. bool vpg_ber_pattern;
  217. } vpg_defs;
  218. #endif /* CONFIG_DEBUG_FS */
  219. struct dw_mipi_dsi *master; /* dual-dsi master ptr */
  220. struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
  221. const struct dw_mipi_dsi_plat_data *plat_data;
  222. };
  223. /*
  224. * Check if either a link to a master or slave is present
  225. */
  226. static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi)
  227. {
  228. return dsi->slave || dsi->master;
  229. }
  230. /*
  231. * The controller should generate 2 frames before
  232. * preparing the peripheral.
  233. */
  234. static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode)
  235. {
  236. int refresh, two_frames;
  237. refresh = drm_mode_vrefresh(mode);
  238. two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
  239. msleep(two_frames);
  240. }
  241. static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
  242. {
  243. return container_of(host, struct dw_mipi_dsi, dsi_host);
  244. }
  245. static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
  246. {
  247. return container_of(bridge, struct dw_mipi_dsi, bridge);
  248. }
  249. static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
  250. {
  251. writel(val, dsi->base + reg);
  252. }
  253. static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
  254. {
  255. return readl(dsi->base + reg);
  256. }
  257. static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
  258. struct mipi_dsi_device *device)
  259. {
  260. struct dw_mipi_dsi *dsi = host_to_dsi(host);
  261. const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
  262. struct drm_bridge *bridge;
  263. struct drm_panel *panel;
  264. int ret;
  265. if (device->lanes > dsi->plat_data->max_data_lanes) {
  266. dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
  267. device->lanes);
  268. return -EINVAL;
  269. }
  270. dsi->lanes = device->lanes;
  271. dsi->channel = device->channel;
  272. dsi->format = device->format;
  273. dsi->mode_flags = device->mode_flags;
  274. ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
  275. &panel, &bridge);
  276. if (ret)
  277. return ret;
  278. if (panel) {
  279. bridge = drm_panel_bridge_add_typed(panel,
  280. DRM_MODE_CONNECTOR_DSI);
  281. if (IS_ERR(bridge))
  282. return PTR_ERR(bridge);
  283. }
  284. dsi->panel_bridge = bridge;
  285. drm_bridge_add(&dsi->bridge);
  286. if (pdata->host_ops && pdata->host_ops->attach) {
  287. ret = pdata->host_ops->attach(pdata->priv_data, device);
  288. if (ret < 0)
  289. return ret;
  290. }
  291. return 0;
  292. }
  293. static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
  294. struct mipi_dsi_device *device)
  295. {
  296. struct dw_mipi_dsi *dsi = host_to_dsi(host);
  297. const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
  298. int ret;
  299. if (pdata->host_ops && pdata->host_ops->detach) {
  300. ret = pdata->host_ops->detach(pdata->priv_data, device);
  301. if (ret < 0)
  302. return ret;
  303. }
  304. drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
  305. drm_bridge_remove(&dsi->bridge);
  306. return 0;
  307. }
  308. static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
  309. const struct mipi_dsi_msg *msg)
  310. {
  311. bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
  312. u32 val = 0;
  313. /*
  314. * TODO dw drv improvements
  315. * largest packet sizes during hfp or during vsa/vpb/vfp
  316. * should be computed according to byte lane, lane number and only
  317. * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
  318. */
  319. dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16)
  320. | INVACT_LPCMD_TIME(4));
  321. if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
  322. val |= ACK_RQST_EN;
  323. if (lpm)
  324. val |= CMD_MODE_ALL_LP;
  325. dsi_write(dsi, DSI_CMD_MODE_CFG, val);
  326. val = dsi_read(dsi, DSI_VID_MODE_CFG);
  327. if (lpm)
  328. val |= ENABLE_LOW_POWER_CMD;
  329. else
  330. val &= ~ENABLE_LOW_POWER_CMD;
  331. dsi_write(dsi, DSI_VID_MODE_CFG, val);
  332. }
  333. static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
  334. {
  335. int ret;
  336. u32 val, mask;
  337. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  338. val, !(val & GEN_CMD_FULL), 1000,
  339. CMD_PKT_STATUS_TIMEOUT_US);
  340. if (ret) {
  341. dev_err(dsi->dev, "failed to get available command FIFO\n");
  342. return ret;
  343. }
  344. dsi_write(dsi, DSI_GEN_HDR, hdr_val);
  345. mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
  346. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  347. val, (val & mask) == mask,
  348. 1000, CMD_PKT_STATUS_TIMEOUT_US);
  349. if (ret) {
  350. dev_err(dsi->dev, "failed to write command FIFO\n");
  351. return ret;
  352. }
  353. return 0;
  354. }
  355. static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
  356. const struct mipi_dsi_packet *packet)
  357. {
  358. const u8 *tx_buf = packet->payload;
  359. int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
  360. __le32 word;
  361. u32 val;
  362. while (len) {
  363. if (len < pld_data_bytes) {
  364. word = 0;
  365. memcpy(&word, tx_buf, len);
  366. dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
  367. len = 0;
  368. } else {
  369. memcpy(&word, tx_buf, pld_data_bytes);
  370. dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
  371. tx_buf += pld_data_bytes;
  372. len -= pld_data_bytes;
  373. }
  374. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  375. val, !(val & GEN_PLD_W_FULL), 1000,
  376. CMD_PKT_STATUS_TIMEOUT_US);
  377. if (ret) {
  378. dev_err(dsi->dev,
  379. "failed to get available write payload FIFO\n");
  380. return ret;
  381. }
  382. }
  383. word = 0;
  384. memcpy(&word, packet->header, sizeof(packet->header));
  385. return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
  386. }
  387. static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
  388. const struct mipi_dsi_msg *msg)
  389. {
  390. int i, j, ret, len = msg->rx_len;
  391. u8 *buf = msg->rx_buf;
  392. u32 val;
  393. /* Wait end of the read operation */
  394. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  395. val, !(val & GEN_RD_CMD_BUSY),
  396. 1000, CMD_PKT_STATUS_TIMEOUT_US);
  397. if (ret) {
  398. dev_err(dsi->dev, "Timeout during read operation\n");
  399. return ret;
  400. }
  401. for (i = 0; i < len; i += 4) {
  402. /* Read fifo must not be empty before all bytes are read */
  403. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  404. val, !(val & GEN_PLD_R_EMPTY),
  405. 1000, CMD_PKT_STATUS_TIMEOUT_US);
  406. if (ret) {
  407. dev_err(dsi->dev, "Read payload FIFO is empty\n");
  408. return ret;
  409. }
  410. val = dsi_read(dsi, DSI_GEN_PLD_DATA);
  411. for (j = 0; j < 4 && j + i < len; j++)
  412. buf[i + j] = val >> (8 * j);
  413. }
  414. return ret;
  415. }
  416. static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
  417. const struct mipi_dsi_msg *msg)
  418. {
  419. struct dw_mipi_dsi *dsi = host_to_dsi(host);
  420. struct mipi_dsi_packet packet;
  421. int ret, nb_bytes;
  422. ret = mipi_dsi_create_packet(&packet, msg);
  423. if (ret) {
  424. dev_err(dsi->dev, "failed to create packet: %d\n", ret);
  425. return ret;
  426. }
  427. dw_mipi_message_config(dsi, msg);
  428. if (dsi->slave)
  429. dw_mipi_message_config(dsi->slave, msg);
  430. ret = dw_mipi_dsi_write(dsi, &packet);
  431. if (ret)
  432. return ret;
  433. if (dsi->slave) {
  434. ret = dw_mipi_dsi_write(dsi->slave, &packet);
  435. if (ret)
  436. return ret;
  437. }
  438. if (msg->rx_buf && msg->rx_len) {
  439. ret = dw_mipi_dsi_read(dsi, msg);
  440. if (ret)
  441. return ret;
  442. nb_bytes = msg->rx_len;
  443. } else {
  444. nb_bytes = packet.size;
  445. }
  446. return nb_bytes;
  447. }
  448. static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
  449. .attach = dw_mipi_dsi_host_attach,
  450. .detach = dw_mipi_dsi_host_detach,
  451. .transfer = dw_mipi_dsi_host_transfer,
  452. };
  453. static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
  454. {
  455. u32 val;
  456. /*
  457. * TODO dw drv improvements
  458. * enabling low power is panel-dependent, we should use the
  459. * panel configuration here...
  460. */
  461. val = ENABLE_LOW_POWER;
  462. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  463. val |= VID_MODE_TYPE_BURST;
  464. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  465. val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
  466. else
  467. val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
  468. #ifdef CONFIG_DEBUG_FS
  469. if (dsi->vpg_defs.vpg) {
  470. val |= VID_MODE_VPG_ENABLE;
  471. val |= dsi->vpg_defs.vpg_horizontal ?
  472. VID_MODE_VPG_HORIZONTAL : 0;
  473. val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0;
  474. }
  475. #endif /* CONFIG_DEBUG_FS */
  476. dsi_write(dsi, DSI_VID_MODE_CFG, val);
  477. }
  478. static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
  479. unsigned long mode_flags)
  480. {
  481. u32 val;
  482. dsi_write(dsi, DSI_PWR_UP, RESET);
  483. if (mode_flags & MIPI_DSI_MODE_VIDEO) {
  484. dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
  485. dw_mipi_dsi_video_mode_config(dsi);
  486. } else {
  487. dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
  488. }
  489. val = PHY_TXREQUESTCLKHS;
  490. if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
  491. val |= AUTO_CLKLANE_CTRL;
  492. dsi_write(dsi, DSI_LPCLK_CTRL, val);
  493. dsi_write(dsi, DSI_PWR_UP, POWERUP);
  494. }
  495. static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
  496. {
  497. dsi_write(dsi, DSI_PWR_UP, RESET);
  498. dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
  499. }
  500. static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
  501. {
  502. const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
  503. unsigned int esc_rate; /* in MHz */
  504. u32 esc_clk_division;
  505. int ret;
  506. /*
  507. * The maximum permitted escape clock is 20MHz and it is derived from
  508. * lanebyteclk, which is running at "lane_mbps / 8".
  509. */
  510. if (phy_ops->get_esc_clk_rate) {
  511. ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data,
  512. &esc_rate);
  513. if (ret)
  514. DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n");
  515. } else
  516. esc_rate = 20; /* Default to 20MHz */
  517. /*
  518. * We want :
  519. * (lane_mbps >> 3) / esc_clk_division < X
  520. * which is:
  521. * (lane_mbps >> 3) / X > esc_clk_division
  522. */
  523. esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
  524. dsi_write(dsi, DSI_PWR_UP, RESET);
  525. /*
  526. * TODO dw drv improvements
  527. * timeout clock division should be computed with the
  528. * high speed transmission counter timeout and byte lane...
  529. */
  530. dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
  531. TX_ESC_CLK_DIVISION(esc_clk_division));
  532. }
  533. static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
  534. const struct drm_display_mode *mode)
  535. {
  536. u32 val = 0, color = 0;
  537. switch (dsi->format) {
  538. case MIPI_DSI_FMT_RGB888:
  539. color = DPI_COLOR_CODING_24BIT;
  540. break;
  541. case MIPI_DSI_FMT_RGB666:
  542. color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
  543. break;
  544. case MIPI_DSI_FMT_RGB666_PACKED:
  545. color = DPI_COLOR_CODING_18BIT_1;
  546. break;
  547. case MIPI_DSI_FMT_RGB565:
  548. color = DPI_COLOR_CODING_16BIT_1;
  549. break;
  550. }
  551. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  552. val |= VSYNC_ACTIVE_LOW;
  553. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  554. val |= HSYNC_ACTIVE_LOW;
  555. dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
  556. dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
  557. dsi_write(dsi, DSI_DPI_CFG_POL, val);
  558. }
  559. static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
  560. {
  561. dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
  562. }
  563. static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
  564. const struct drm_display_mode *mode)
  565. {
  566. /*
  567. * TODO dw drv improvements
  568. * only burst mode is supported here. For non-burst video modes,
  569. * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
  570. * DSI_VNPCR.NPSIZE... especially because this driver supports
  571. * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
  572. */
  573. dsi_write(dsi, DSI_VID_PKT_SIZE,
  574. dw_mipi_is_dual_mode(dsi) ?
  575. VID_PKT_SIZE(mode->hdisplay / 2) :
  576. VID_PKT_SIZE(mode->hdisplay));
  577. }
  578. static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
  579. {
  580. /*
  581. * TODO dw drv improvements
  582. * compute high speed transmission counter timeout according
  583. * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
  584. */
  585. dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
  586. /*
  587. * TODO dw drv improvements
  588. * the Bus-Turn-Around Timeout Counter should be computed
  589. * according to byte lane...
  590. */
  591. dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
  592. dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
  593. }
  594. /* Get lane byte clock cycles. */
  595. static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
  596. const struct drm_display_mode *mode,
  597. u32 hcomponent)
  598. {
  599. u32 frac, lbcc;
  600. lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
  601. frac = lbcc % mode->clock;
  602. lbcc = lbcc / mode->clock;
  603. if (frac)
  604. lbcc++;
  605. return lbcc;
  606. }
  607. static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
  608. const struct drm_display_mode *mode)
  609. {
  610. u32 htotal, hsa, hbp, lbcc;
  611. htotal = mode->htotal;
  612. hsa = mode->hsync_end - mode->hsync_start;
  613. hbp = mode->htotal - mode->hsync_end;
  614. /*
  615. * TODO dw drv improvements
  616. * computations below may be improved...
  617. */
  618. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
  619. dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
  620. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
  621. dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
  622. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
  623. dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
  624. }
  625. static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
  626. const struct drm_display_mode *mode)
  627. {
  628. u32 vactive, vsa, vfp, vbp;
  629. vactive = mode->vdisplay;
  630. vsa = mode->vsync_end - mode->vsync_start;
  631. vfp = mode->vsync_start - mode->vdisplay;
  632. vbp = mode->vtotal - mode->vsync_end;
  633. dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
  634. dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
  635. dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
  636. dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
  637. }
  638. static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
  639. {
  640. const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
  641. struct dw_mipi_dsi_dphy_timing timing;
  642. u32 hw_version;
  643. int ret;
  644. ret = phy_ops->get_timing(dsi->plat_data->priv_data,
  645. dsi->lane_mbps, &timing);
  646. if (ret)
  647. DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");
  648. /*
  649. * TODO dw drv improvements
  650. * data & clock lane timers should be computed according to panel
  651. * blankings and to the automatic clock lane control mode...
  652. * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
  653. * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
  654. */
  655. hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
  656. if (hw_version >= HWVER_131) {
  657. dsi_write(dsi, DSI_PHY_TMR_CFG,
  658. PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
  659. PHY_LP2HS_TIME_V131(timing.data_lp2hs));
  660. dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
  661. } else {
  662. dsi_write(dsi, DSI_PHY_TMR_CFG,
  663. PHY_HS2LP_TIME(timing.data_hs2lp) |
  664. PHY_LP2HS_TIME(timing.data_lp2hs) |
  665. MAX_RD_TIME(10000));
  666. }
  667. dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
  668. PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
  669. PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
  670. }
  671. static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
  672. {
  673. /*
  674. * TODO dw drv improvements
  675. * stop wait time should be the maximum between host dsi
  676. * and panel stop wait times
  677. */
  678. dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
  679. N_LANES(dsi->lanes));
  680. }
  681. static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
  682. {
  683. /* Clear PHY state */
  684. dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
  685. | PHY_RSTZ | PHY_SHUTDOWNZ);
  686. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
  687. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
  688. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
  689. }
  690. static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
  691. {
  692. u32 val;
  693. int ret;
  694. dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
  695. PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
  696. ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
  697. val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
  698. if (ret)
  699. DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
  700. ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
  701. val, val & PHY_STOP_STATE_CLK_LANE, 1000,
  702. PHY_STATUS_TIMEOUT_US);
  703. if (ret)
  704. DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
  705. }
  706. static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
  707. {
  708. dsi_read(dsi, DSI_INT_ST0);
  709. dsi_read(dsi, DSI_INT_ST1);
  710. dsi_write(dsi, DSI_INT_MSK0, 0);
  711. dsi_write(dsi, DSI_INT_MSK1, 0);
  712. }
  713. static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
  714. {
  715. struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
  716. const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
  717. /*
  718. * Switch to command mode before panel-bridge post_disable &
  719. * panel unprepare.
  720. * Note: panel-bridge disable & panel disable has been called
  721. * before by the drm framework.
  722. */
  723. dw_mipi_dsi_set_mode(dsi, 0);
  724. /*
  725. * TODO Only way found to call panel-bridge post_disable &
  726. * panel unprepare before the dsi "final" disable...
  727. * This needs to be fixed in the drm_bridge framework and the API
  728. * needs to be updated to manage our own call chains...
  729. */
  730. if (dsi->panel_bridge->funcs->post_disable)
  731. dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
  732. if (phy_ops->power_off)
  733. phy_ops->power_off(dsi->plat_data->priv_data);
  734. if (dsi->slave) {
  735. dw_mipi_dsi_disable(dsi->slave);
  736. clk_disable_unprepare(dsi->slave->pclk);
  737. pm_runtime_put(dsi->slave->dev);
  738. }
  739. dw_mipi_dsi_disable(dsi);
  740. clk_disable_unprepare(dsi->pclk);
  741. pm_runtime_put(dsi->dev);
  742. }
  743. static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi)
  744. {
  745. /* this instance is the slave, so add the master's lanes */
  746. if (dsi->master)
  747. return dsi->master->lanes + dsi->lanes;
  748. /* this instance is the master, so add the slave's lanes */
  749. if (dsi->slave)
  750. return dsi->lanes + dsi->slave->lanes;
  751. /* single-dsi, so no other instance to consider */
  752. return dsi->lanes;
  753. }
  754. static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
  755. const struct drm_display_mode *adjusted_mode)
  756. {
  757. const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
  758. void *priv_data = dsi->plat_data->priv_data;
  759. int ret;
  760. u32 lanes = dw_mipi_dsi_get_lanes(dsi);
  761. clk_prepare_enable(dsi->pclk);
  762. ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
  763. lanes, dsi->format, &dsi->lane_mbps);
  764. if (ret)
  765. DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
  766. pm_runtime_get_sync(dsi->dev);
  767. dw_mipi_dsi_init(dsi);
  768. dw_mipi_dsi_dpi_config(dsi, adjusted_mode);
  769. dw_mipi_dsi_packet_handler_config(dsi);
  770. dw_mipi_dsi_video_mode_config(dsi);
  771. dw_mipi_dsi_video_packet_config(dsi, adjusted_mode);
  772. dw_mipi_dsi_command_mode_config(dsi);
  773. dw_mipi_dsi_line_timer_config(dsi, adjusted_mode);
  774. dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode);
  775. dw_mipi_dsi_dphy_init(dsi);
  776. dw_mipi_dsi_dphy_timing_config(dsi);
  777. dw_mipi_dsi_dphy_interface_config(dsi);
  778. dw_mipi_dsi_clear_err(dsi);
  779. ret = phy_ops->init(priv_data);
  780. if (ret)
  781. DRM_DEBUG_DRIVER("Phy init() failed\n");
  782. dw_mipi_dsi_dphy_enable(dsi);
  783. dw_mipi_dsi_wait_for_two_frames(adjusted_mode);
  784. /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
  785. dw_mipi_dsi_set_mode(dsi, 0);
  786. if (phy_ops->power_on)
  787. phy_ops->power_on(dsi->plat_data->priv_data);
  788. }
  789. static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
  790. const struct drm_display_mode *mode,
  791. const struct drm_display_mode *adjusted_mode)
  792. {
  793. struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
  794. dw_mipi_dsi_mode_set(dsi, adjusted_mode);
  795. if (dsi->slave)
  796. dw_mipi_dsi_mode_set(dsi->slave, adjusted_mode);
  797. }
  798. static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
  799. {
  800. struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
  801. /* Switch to video mode for panel-bridge enable & panel enable */
  802. dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
  803. if (dsi->slave)
  804. dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO);
  805. }
  806. static enum drm_mode_status
  807. dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
  808. const struct drm_display_info *info,
  809. const struct drm_display_mode *mode)
  810. {
  811. struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
  812. const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
  813. enum drm_mode_status mode_status = MODE_OK;
  814. if (pdata->mode_valid)
  815. mode_status = pdata->mode_valid(pdata->priv_data, mode);
  816. return mode_status;
  817. }
  818. static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge,
  819. enum drm_bridge_attach_flags flags)
  820. {
  821. struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
  822. if (!bridge->encoder) {
  823. DRM_ERROR("Parent encoder object not found\n");
  824. return -ENODEV;
  825. }
  826. /* Set the encoder type as caller does not know it */
  827. bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
  828. /* Attach the panel-bridge to the dsi bridge */
  829. return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
  830. flags);
  831. }
  832. static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
  833. .mode_set = dw_mipi_dsi_bridge_mode_set,
  834. .enable = dw_mipi_dsi_bridge_enable,
  835. .post_disable = dw_mipi_dsi_bridge_post_disable,
  836. .mode_valid = dw_mipi_dsi_bridge_mode_valid,
  837. .attach = dw_mipi_dsi_bridge_attach,
  838. };
  839. #ifdef CONFIG_DEBUG_FS
  840. static int dw_mipi_dsi_debugfs_write(void *data, u64 val)
  841. {
  842. struct debugfs_entries *vpg = data;
  843. struct dw_mipi_dsi *dsi;
  844. u32 mode_cfg;
  845. if (!vpg)
  846. return -ENODEV;
  847. dsi = vpg->dsi;
  848. *vpg->reg = (bool)val;
  849. mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG);
  850. if (*vpg->reg)
  851. mode_cfg |= vpg->mask;
  852. else
  853. mode_cfg &= ~vpg->mask;
  854. dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg);
  855. return 0;
  856. }
  857. static int dw_mipi_dsi_debugfs_show(void *data, u64 *val)
  858. {
  859. struct debugfs_entries *vpg = data;
  860. if (!vpg)
  861. return -ENODEV;
  862. *val = *vpg->reg;
  863. return 0;
  864. }
  865. DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_mipi_dsi_debugfs_show,
  866. dw_mipi_dsi_debugfs_write, "%llu\n");
  867. static void debugfs_create_files(void *data)
  868. {
  869. struct dw_mipi_dsi *dsi = data;
  870. struct debugfs_entries debugfs[] = {
  871. REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi),
  872. REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi),
  873. REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi),
  874. };
  875. int i;
  876. dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL);
  877. if (!dsi->debugfs_vpg)
  878. return;
  879. for (i = 0; i < ARRAY_SIZE(debugfs); i++)
  880. debugfs_create_file(dsi->debugfs_vpg[i].name, 0644,
  881. dsi->debugfs, &dsi->debugfs_vpg[i],
  882. &fops_x32);
  883. }
  884. static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi)
  885. {
  886. dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);
  887. if (IS_ERR(dsi->debugfs)) {
  888. dev_err(dsi->dev, "failed to create debugfs root\n");
  889. return;
  890. }
  891. debugfs_create_files(dsi);
  892. }
  893. static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi)
  894. {
  895. debugfs_remove_recursive(dsi->debugfs);
  896. kfree(dsi->debugfs_vpg);
  897. }
  898. #else
  899. static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { }
  900. static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
  901. #endif /* CONFIG_DEBUG_FS */
  902. static struct dw_mipi_dsi *
  903. __dw_mipi_dsi_probe(struct platform_device *pdev,
  904. const struct dw_mipi_dsi_plat_data *plat_data)
  905. {
  906. struct device *dev = &pdev->dev;
  907. struct reset_control *apb_rst;
  908. struct dw_mipi_dsi *dsi;
  909. int ret;
  910. dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
  911. if (!dsi)
  912. return ERR_PTR(-ENOMEM);
  913. dsi->dev = dev;
  914. dsi->plat_data = plat_data;
  915. if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps ||
  916. !plat_data->phy_ops->get_timing) {
  917. DRM_ERROR("Phy not properly configured\n");
  918. return ERR_PTR(-ENODEV);
  919. }
  920. if (!plat_data->base) {
  921. dsi->base = devm_platform_ioremap_resource(pdev, 0);
  922. if (IS_ERR(dsi->base))
  923. return ERR_PTR(-ENODEV);
  924. } else {
  925. dsi->base = plat_data->base;
  926. }
  927. dsi->pclk = devm_clk_get(dev, "pclk");
  928. if (IS_ERR(dsi->pclk)) {
  929. ret = PTR_ERR(dsi->pclk);
  930. dev_err(dev, "Unable to get pclk: %d\n", ret);
  931. return ERR_PTR(ret);
  932. }
  933. /*
  934. * Note that the reset was not defined in the initial device tree, so
  935. * we have to be prepared for it not being found.
  936. */
  937. apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
  938. if (IS_ERR(apb_rst)) {
  939. ret = PTR_ERR(apb_rst);
  940. if (ret != -EPROBE_DEFER)
  941. dev_err(dev, "Unable to get reset control: %d\n", ret);
  942. return ERR_PTR(ret);
  943. }
  944. if (apb_rst) {
  945. ret = clk_prepare_enable(dsi->pclk);
  946. if (ret) {
  947. dev_err(dev, "%s: Failed to enable pclk\n", __func__);
  948. return ERR_PTR(ret);
  949. }
  950. reset_control_assert(apb_rst);
  951. usleep_range(10, 20);
  952. reset_control_deassert(apb_rst);
  953. clk_disable_unprepare(dsi->pclk);
  954. }
  955. dw_mipi_dsi_debugfs_init(dsi);
  956. pm_runtime_enable(dev);
  957. dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
  958. dsi->dsi_host.dev = dev;
  959. ret = mipi_dsi_host_register(&dsi->dsi_host);
  960. if (ret) {
  961. dev_err(dev, "Failed to register MIPI host: %d\n", ret);
  962. pm_runtime_disable(dev);
  963. dw_mipi_dsi_debugfs_remove(dsi);
  964. return ERR_PTR(ret);
  965. }
  966. dsi->bridge.driver_private = dsi;
  967. dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
  968. #ifdef CONFIG_OF
  969. dsi->bridge.of_node = pdev->dev.of_node;
  970. #endif
  971. return dsi;
  972. }
  973. static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
  974. {
  975. mipi_dsi_host_unregister(&dsi->dsi_host);
  976. pm_runtime_disable(dsi->dev);
  977. dw_mipi_dsi_debugfs_remove(dsi);
  978. }
  979. void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave)
  980. {
  981. /* introduce controllers to each other */
  982. dsi->slave = slave;
  983. dsi->slave->master = dsi;
  984. /* migrate settings for already attached displays */
  985. dsi->slave->lanes = dsi->lanes;
  986. dsi->slave->channel = dsi->channel;
  987. dsi->slave->format = dsi->format;
  988. dsi->slave->mode_flags = dsi->mode_flags;
  989. }
  990. EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave);
  991. /*
  992. * Probe/remove API, used from platforms based on the DRM bridge API.
  993. */
  994. struct dw_mipi_dsi *
  995. dw_mipi_dsi_probe(struct platform_device *pdev,
  996. const struct dw_mipi_dsi_plat_data *plat_data)
  997. {
  998. return __dw_mipi_dsi_probe(pdev, plat_data);
  999. }
  1000. EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
  1001. void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
  1002. {
  1003. __dw_mipi_dsi_remove(dsi);
  1004. }
  1005. EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
  1006. /*
  1007. * Bind/unbind API, used from platforms based on the component framework.
  1008. */
  1009. int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
  1010. {
  1011. int ret;
  1012. ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
  1013. if (ret) {
  1014. DRM_ERROR("Failed to initialize bridge with drm\n");
  1015. return ret;
  1016. }
  1017. return ret;
  1018. }
  1019. EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
  1020. void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
  1021. {
  1022. }
  1023. EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
  1024. MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
  1025. MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
  1026. MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
  1027. MODULE_LICENSE("GPL");
  1028. MODULE_ALIAS("platform:dw-mipi-dsi");