dw-hdmi.h 49 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __DW_HDMI_H__
  6. #define __DW_HDMI_H__
  7. /* Identification Registers */
  8. #define HDMI_DESIGN_ID 0x0000
  9. #define HDMI_REVISION_ID 0x0001
  10. #define HDMI_PRODUCT_ID0 0x0002
  11. #define HDMI_PRODUCT_ID1 0x0003
  12. #define HDMI_CONFIG0_ID 0x0004
  13. #define HDMI_CONFIG1_ID 0x0005
  14. #define HDMI_CONFIG2_ID 0x0006
  15. #define HDMI_CONFIG3_ID 0x0007
  16. /* Interrupt Registers */
  17. #define HDMI_IH_FC_STAT0 0x0100
  18. #define HDMI_IH_FC_STAT1 0x0101
  19. #define HDMI_IH_FC_STAT2 0x0102
  20. #define HDMI_IH_AS_STAT0 0x0103
  21. #define HDMI_IH_PHY_STAT0 0x0104
  22. #define HDMI_IH_I2CM_STAT0 0x0105
  23. #define HDMI_IH_CEC_STAT0 0x0106
  24. #define HDMI_IH_VP_STAT0 0x0107
  25. #define HDMI_IH_I2CMPHY_STAT0 0x0108
  26. #define HDMI_IH_AHBDMAAUD_STAT0 0x0109
  27. #define HDMI_IH_MUTE_FC_STAT0 0x0180
  28. #define HDMI_IH_MUTE_FC_STAT1 0x0181
  29. #define HDMI_IH_MUTE_FC_STAT2 0x0182
  30. #define HDMI_IH_MUTE_AS_STAT0 0x0183
  31. #define HDMI_IH_MUTE_PHY_STAT0 0x0184
  32. #define HDMI_IH_MUTE_I2CM_STAT0 0x0185
  33. #define HDMI_IH_MUTE_CEC_STAT0 0x0186
  34. #define HDMI_IH_MUTE_VP_STAT0 0x0187
  35. #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
  36. #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
  37. #define HDMI_IH_MUTE 0x01FF
  38. /* Video Sample Registers */
  39. #define HDMI_TX_INVID0 0x0200
  40. #define HDMI_TX_INSTUFFING 0x0201
  41. #define HDMI_TX_GYDATA0 0x0202
  42. #define HDMI_TX_GYDATA1 0x0203
  43. #define HDMI_TX_RCRDATA0 0x0204
  44. #define HDMI_TX_RCRDATA1 0x0205
  45. #define HDMI_TX_BCBDATA0 0x0206
  46. #define HDMI_TX_BCBDATA1 0x0207
  47. /* Video Packetizer Registers */
  48. #define HDMI_VP_STATUS 0x0800
  49. #define HDMI_VP_PR_CD 0x0801
  50. #define HDMI_VP_STUFF 0x0802
  51. #define HDMI_VP_REMAP 0x0803
  52. #define HDMI_VP_CONF 0x0804
  53. #define HDMI_VP_STAT 0x0805
  54. #define HDMI_VP_INT 0x0806
  55. #define HDMI_VP_MASK 0x0807
  56. #define HDMI_VP_POL 0x0808
  57. /* Frame Composer Registers */
  58. #define HDMI_FC_INVIDCONF 0x1000
  59. #define HDMI_FC_INHACTV0 0x1001
  60. #define HDMI_FC_INHACTV1 0x1002
  61. #define HDMI_FC_INHBLANK0 0x1003
  62. #define HDMI_FC_INHBLANK1 0x1004
  63. #define HDMI_FC_INVACTV0 0x1005
  64. #define HDMI_FC_INVACTV1 0x1006
  65. #define HDMI_FC_INVBLANK 0x1007
  66. #define HDMI_FC_HSYNCINDELAY0 0x1008
  67. #define HDMI_FC_HSYNCINDELAY1 0x1009
  68. #define HDMI_FC_HSYNCINWIDTH0 0x100A
  69. #define HDMI_FC_HSYNCINWIDTH1 0x100B
  70. #define HDMI_FC_VSYNCINDELAY 0x100C
  71. #define HDMI_FC_VSYNCINWIDTH 0x100D
  72. #define HDMI_FC_INFREQ0 0x100E
  73. #define HDMI_FC_INFREQ1 0x100F
  74. #define HDMI_FC_INFREQ2 0x1010
  75. #define HDMI_FC_CTRLDUR 0x1011
  76. #define HDMI_FC_EXCTRLDUR 0x1012
  77. #define HDMI_FC_EXCTRLSPAC 0x1013
  78. #define HDMI_FC_CH0PREAM 0x1014
  79. #define HDMI_FC_CH1PREAM 0x1015
  80. #define HDMI_FC_CH2PREAM 0x1016
  81. #define HDMI_FC_AVICONF3 0x1017
  82. #define HDMI_FC_GCP 0x1018
  83. #define HDMI_FC_AVICONF0 0x1019
  84. #define HDMI_FC_AVICONF1 0x101A
  85. #define HDMI_FC_AVICONF2 0x101B
  86. #define HDMI_FC_AVIVID 0x101C
  87. #define HDMI_FC_AVIETB0 0x101D
  88. #define HDMI_FC_AVIETB1 0x101E
  89. #define HDMI_FC_AVISBB0 0x101F
  90. #define HDMI_FC_AVISBB1 0x1020
  91. #define HDMI_FC_AVIELB0 0x1021
  92. #define HDMI_FC_AVIELB1 0x1022
  93. #define HDMI_FC_AVISRB0 0x1023
  94. #define HDMI_FC_AVISRB1 0x1024
  95. #define HDMI_FC_AUDICONF0 0x1025
  96. #define HDMI_FC_AUDICONF1 0x1026
  97. #define HDMI_FC_AUDICONF2 0x1027
  98. #define HDMI_FC_AUDICONF3 0x1028
  99. #define HDMI_FC_VSDIEEEID0 0x1029
  100. #define HDMI_FC_VSDSIZE 0x102A
  101. #define HDMI_FC_VSDIEEEID1 0x1030
  102. #define HDMI_FC_VSDIEEEID2 0x1031
  103. #define HDMI_FC_VSDPAYLOAD0 0x1032
  104. #define HDMI_FC_VSDPAYLOAD1 0x1033
  105. #define HDMI_FC_VSDPAYLOAD2 0x1034
  106. #define HDMI_FC_VSDPAYLOAD3 0x1035
  107. #define HDMI_FC_VSDPAYLOAD4 0x1036
  108. #define HDMI_FC_VSDPAYLOAD5 0x1037
  109. #define HDMI_FC_VSDPAYLOAD6 0x1038
  110. #define HDMI_FC_VSDPAYLOAD7 0x1039
  111. #define HDMI_FC_VSDPAYLOAD8 0x103A
  112. #define HDMI_FC_VSDPAYLOAD9 0x103B
  113. #define HDMI_FC_VSDPAYLOAD10 0x103C
  114. #define HDMI_FC_VSDPAYLOAD11 0x103D
  115. #define HDMI_FC_VSDPAYLOAD12 0x103E
  116. #define HDMI_FC_VSDPAYLOAD13 0x103F
  117. #define HDMI_FC_VSDPAYLOAD14 0x1040
  118. #define HDMI_FC_VSDPAYLOAD15 0x1041
  119. #define HDMI_FC_VSDPAYLOAD16 0x1042
  120. #define HDMI_FC_VSDPAYLOAD17 0x1043
  121. #define HDMI_FC_VSDPAYLOAD18 0x1044
  122. #define HDMI_FC_VSDPAYLOAD19 0x1045
  123. #define HDMI_FC_VSDPAYLOAD20 0x1046
  124. #define HDMI_FC_VSDPAYLOAD21 0x1047
  125. #define HDMI_FC_VSDPAYLOAD22 0x1048
  126. #define HDMI_FC_VSDPAYLOAD23 0x1049
  127. #define HDMI_FC_SPDVENDORNAME0 0x104A
  128. #define HDMI_FC_SPDVENDORNAME1 0x104B
  129. #define HDMI_FC_SPDVENDORNAME2 0x104C
  130. #define HDMI_FC_SPDVENDORNAME3 0x104D
  131. #define HDMI_FC_SPDVENDORNAME4 0x104E
  132. #define HDMI_FC_SPDVENDORNAME5 0x104F
  133. #define HDMI_FC_SPDVENDORNAME6 0x1050
  134. #define HDMI_FC_SPDVENDORNAME7 0x1051
  135. #define HDMI_FC_SDPPRODUCTNAME0 0x1052
  136. #define HDMI_FC_SDPPRODUCTNAME1 0x1053
  137. #define HDMI_FC_SDPPRODUCTNAME2 0x1054
  138. #define HDMI_FC_SDPPRODUCTNAME3 0x1055
  139. #define HDMI_FC_SDPPRODUCTNAME4 0x1056
  140. #define HDMI_FC_SDPPRODUCTNAME5 0x1057
  141. #define HDMI_FC_SDPPRODUCTNAME6 0x1058
  142. #define HDMI_FC_SDPPRODUCTNAME7 0x1059
  143. #define HDMI_FC_SDPPRODUCTNAME8 0x105A
  144. #define HDMI_FC_SDPPRODUCTNAME9 0x105B
  145. #define HDMI_FC_SDPPRODUCTNAME10 0x105C
  146. #define HDMI_FC_SDPPRODUCTNAME11 0x105D
  147. #define HDMI_FC_SDPPRODUCTNAME12 0x105E
  148. #define HDMI_FC_SDPPRODUCTNAME13 0x105F
  149. #define HDMI_FC_SDPPRODUCTNAME14 0x1060
  150. #define HDMI_FC_SPDPRODUCTNAME15 0x1061
  151. #define HDMI_FC_SPDDEVICEINF 0x1062
  152. #define HDMI_FC_AUDSCONF 0x1063
  153. #define HDMI_FC_AUDSSTAT 0x1064
  154. #define HDMI_FC_AUDSCHNLS7 0x106e
  155. #define HDMI_FC_AUDSCHNLS8 0x106f
  156. #define HDMI_FC_DATACH0FILL 0x1070
  157. #define HDMI_FC_DATACH1FILL 0x1071
  158. #define HDMI_FC_DATACH2FILL 0x1072
  159. #define HDMI_FC_CTRLQHIGH 0x1073
  160. #define HDMI_FC_CTRLQLOW 0x1074
  161. #define HDMI_FC_ACP0 0x1075
  162. #define HDMI_FC_ACP28 0x1076
  163. #define HDMI_FC_ACP27 0x1077
  164. #define HDMI_FC_ACP26 0x1078
  165. #define HDMI_FC_ACP25 0x1079
  166. #define HDMI_FC_ACP24 0x107A
  167. #define HDMI_FC_ACP23 0x107B
  168. #define HDMI_FC_ACP22 0x107C
  169. #define HDMI_FC_ACP21 0x107D
  170. #define HDMI_FC_ACP20 0x107E
  171. #define HDMI_FC_ACP19 0x107F
  172. #define HDMI_FC_ACP18 0x1080
  173. #define HDMI_FC_ACP17 0x1081
  174. #define HDMI_FC_ACP16 0x1082
  175. #define HDMI_FC_ACP15 0x1083
  176. #define HDMI_FC_ACP14 0x1084
  177. #define HDMI_FC_ACP13 0x1085
  178. #define HDMI_FC_ACP12 0x1086
  179. #define HDMI_FC_ACP11 0x1087
  180. #define HDMI_FC_ACP10 0x1088
  181. #define HDMI_FC_ACP9 0x1089
  182. #define HDMI_FC_ACP8 0x108A
  183. #define HDMI_FC_ACP7 0x108B
  184. #define HDMI_FC_ACP6 0x108C
  185. #define HDMI_FC_ACP5 0x108D
  186. #define HDMI_FC_ACP4 0x108E
  187. #define HDMI_FC_ACP3 0x108F
  188. #define HDMI_FC_ACP2 0x1090
  189. #define HDMI_FC_ACP1 0x1091
  190. #define HDMI_FC_ISCR1_0 0x1092
  191. #define HDMI_FC_ISCR1_16 0x1093
  192. #define HDMI_FC_ISCR1_15 0x1094
  193. #define HDMI_FC_ISCR1_14 0x1095
  194. #define HDMI_FC_ISCR1_13 0x1096
  195. #define HDMI_FC_ISCR1_12 0x1097
  196. #define HDMI_FC_ISCR1_11 0x1098
  197. #define HDMI_FC_ISCR1_10 0x1099
  198. #define HDMI_FC_ISCR1_9 0x109A
  199. #define HDMI_FC_ISCR1_8 0x109B
  200. #define HDMI_FC_ISCR1_7 0x109C
  201. #define HDMI_FC_ISCR1_6 0x109D
  202. #define HDMI_FC_ISCR1_5 0x109E
  203. #define HDMI_FC_ISCR1_4 0x109F
  204. #define HDMI_FC_ISCR1_3 0x10A0
  205. #define HDMI_FC_ISCR1_2 0x10A1
  206. #define HDMI_FC_ISCR1_1 0x10A2
  207. #define HDMI_FC_ISCR2_15 0x10A3
  208. #define HDMI_FC_ISCR2_14 0x10A4
  209. #define HDMI_FC_ISCR2_13 0x10A5
  210. #define HDMI_FC_ISCR2_12 0x10A6
  211. #define HDMI_FC_ISCR2_11 0x10A7
  212. #define HDMI_FC_ISCR2_10 0x10A8
  213. #define HDMI_FC_ISCR2_9 0x10A9
  214. #define HDMI_FC_ISCR2_8 0x10AA
  215. #define HDMI_FC_ISCR2_7 0x10AB
  216. #define HDMI_FC_ISCR2_6 0x10AC
  217. #define HDMI_FC_ISCR2_5 0x10AD
  218. #define HDMI_FC_ISCR2_4 0x10AE
  219. #define HDMI_FC_ISCR2_3 0x10AF
  220. #define HDMI_FC_ISCR2_2 0x10B0
  221. #define HDMI_FC_ISCR2_1 0x10B1
  222. #define HDMI_FC_ISCR2_0 0x10B2
  223. #define HDMI_FC_DATAUTO0 0x10B3
  224. #define HDMI_FC_DATAUTO1 0x10B4
  225. #define HDMI_FC_DATAUTO2 0x10B5
  226. #define HDMI_FC_DATMAN 0x10B6
  227. #define HDMI_FC_DATAUTO3 0x10B7
  228. #define HDMI_FC_RDRB0 0x10B8
  229. #define HDMI_FC_RDRB1 0x10B9
  230. #define HDMI_FC_RDRB2 0x10BA
  231. #define HDMI_FC_RDRB3 0x10BB
  232. #define HDMI_FC_RDRB4 0x10BC
  233. #define HDMI_FC_RDRB5 0x10BD
  234. #define HDMI_FC_RDRB6 0x10BE
  235. #define HDMI_FC_RDRB7 0x10BF
  236. #define HDMI_FC_STAT0 0x10D0
  237. #define HDMI_FC_INT0 0x10D1
  238. #define HDMI_FC_MASK0 0x10D2
  239. #define HDMI_FC_POL0 0x10D3
  240. #define HDMI_FC_STAT1 0x10D4
  241. #define HDMI_FC_INT1 0x10D5
  242. #define HDMI_FC_MASK1 0x10D6
  243. #define HDMI_FC_POL1 0x10D7
  244. #define HDMI_FC_STAT2 0x10D8
  245. #define HDMI_FC_INT2 0x10D9
  246. #define HDMI_FC_MASK2 0x10DA
  247. #define HDMI_FC_POL2 0x10DB
  248. #define HDMI_FC_PRCONF 0x10E0
  249. #define HDMI_FC_SCRAMBLER_CTRL 0x10E1
  250. #define HDMI_FC_PACKET_TX_EN 0x10E3
  251. #define HDMI_FC_GMD_STAT 0x1100
  252. #define HDMI_FC_GMD_EN 0x1101
  253. #define HDMI_FC_GMD_UP 0x1102
  254. #define HDMI_FC_GMD_CONF 0x1103
  255. #define HDMI_FC_GMD_HB 0x1104
  256. #define HDMI_FC_GMD_PB0 0x1105
  257. #define HDMI_FC_GMD_PB1 0x1106
  258. #define HDMI_FC_GMD_PB2 0x1107
  259. #define HDMI_FC_GMD_PB3 0x1108
  260. #define HDMI_FC_GMD_PB4 0x1109
  261. #define HDMI_FC_GMD_PB5 0x110A
  262. #define HDMI_FC_GMD_PB6 0x110B
  263. #define HDMI_FC_GMD_PB7 0x110C
  264. #define HDMI_FC_GMD_PB8 0x110D
  265. #define HDMI_FC_GMD_PB9 0x110E
  266. #define HDMI_FC_GMD_PB10 0x110F
  267. #define HDMI_FC_GMD_PB11 0x1110
  268. #define HDMI_FC_GMD_PB12 0x1111
  269. #define HDMI_FC_GMD_PB13 0x1112
  270. #define HDMI_FC_GMD_PB14 0x1113
  271. #define HDMI_FC_GMD_PB15 0x1114
  272. #define HDMI_FC_GMD_PB16 0x1115
  273. #define HDMI_FC_GMD_PB17 0x1116
  274. #define HDMI_FC_GMD_PB18 0x1117
  275. #define HDMI_FC_GMD_PB19 0x1118
  276. #define HDMI_FC_GMD_PB20 0x1119
  277. #define HDMI_FC_GMD_PB21 0x111A
  278. #define HDMI_FC_GMD_PB22 0x111B
  279. #define HDMI_FC_GMD_PB23 0x111C
  280. #define HDMI_FC_GMD_PB24 0x111D
  281. #define HDMI_FC_GMD_PB25 0x111E
  282. #define HDMI_FC_GMD_PB26 0x111F
  283. #define HDMI_FC_GMD_PB27 0x1120
  284. #define HDMI_FC_DRM_UP 0x1167
  285. #define HDMI_FC_DRM_HB0 0x1168
  286. #define HDMI_FC_DRM_HB1 0x1169
  287. #define HDMI_FC_DRM_PB0 0x116A
  288. #define HDMI_FC_DRM_PB1 0x116B
  289. #define HDMI_FC_DRM_PB2 0x116C
  290. #define HDMI_FC_DRM_PB3 0x116D
  291. #define HDMI_FC_DRM_PB4 0x116E
  292. #define HDMI_FC_DRM_PB5 0x116F
  293. #define HDMI_FC_DRM_PB6 0x1170
  294. #define HDMI_FC_DRM_PB7 0x1171
  295. #define HDMI_FC_DRM_PB8 0x1172
  296. #define HDMI_FC_DRM_PB9 0x1173
  297. #define HDMI_FC_DRM_PB10 0x1174
  298. #define HDMI_FC_DRM_PB11 0x1175
  299. #define HDMI_FC_DRM_PB12 0x1176
  300. #define HDMI_FC_DRM_PB13 0x1177
  301. #define HDMI_FC_DRM_PB14 0x1178
  302. #define HDMI_FC_DRM_PB15 0x1179
  303. #define HDMI_FC_DRM_PB16 0x117A
  304. #define HDMI_FC_DRM_PB17 0x117B
  305. #define HDMI_FC_DRM_PB18 0x117C
  306. #define HDMI_FC_DRM_PB19 0x117D
  307. #define HDMI_FC_DRM_PB20 0x117E
  308. #define HDMI_FC_DRM_PB21 0x117F
  309. #define HDMI_FC_DRM_PB22 0x1180
  310. #define HDMI_FC_DRM_PB23 0x1181
  311. #define HDMI_FC_DRM_PB24 0x1182
  312. #define HDMI_FC_DRM_PB25 0x1183
  313. #define HDMI_FC_DRM_PB26 0x1184
  314. #define HDMI_FC_DBGFORCE 0x1200
  315. #define HDMI_FC_DBGAUD0CH0 0x1201
  316. #define HDMI_FC_DBGAUD1CH0 0x1202
  317. #define HDMI_FC_DBGAUD2CH0 0x1203
  318. #define HDMI_FC_DBGAUD0CH1 0x1204
  319. #define HDMI_FC_DBGAUD1CH1 0x1205
  320. #define HDMI_FC_DBGAUD2CH1 0x1206
  321. #define HDMI_FC_DBGAUD0CH2 0x1207
  322. #define HDMI_FC_DBGAUD1CH2 0x1208
  323. #define HDMI_FC_DBGAUD2CH2 0x1209
  324. #define HDMI_FC_DBGAUD0CH3 0x120A
  325. #define HDMI_FC_DBGAUD1CH3 0x120B
  326. #define HDMI_FC_DBGAUD2CH3 0x120C
  327. #define HDMI_FC_DBGAUD0CH4 0x120D
  328. #define HDMI_FC_DBGAUD1CH4 0x120E
  329. #define HDMI_FC_DBGAUD2CH4 0x120F
  330. #define HDMI_FC_DBGAUD0CH5 0x1210
  331. #define HDMI_FC_DBGAUD1CH5 0x1211
  332. #define HDMI_FC_DBGAUD2CH5 0x1212
  333. #define HDMI_FC_DBGAUD0CH6 0x1213
  334. #define HDMI_FC_DBGAUD1CH6 0x1214
  335. #define HDMI_FC_DBGAUD2CH6 0x1215
  336. #define HDMI_FC_DBGAUD0CH7 0x1216
  337. #define HDMI_FC_DBGAUD1CH7 0x1217
  338. #define HDMI_FC_DBGAUD2CH7 0x1218
  339. #define HDMI_FC_DBGTMDS0 0x1219
  340. #define HDMI_FC_DBGTMDS1 0x121A
  341. #define HDMI_FC_DBGTMDS2 0x121B
  342. /* HDMI Source PHY Registers */
  343. #define HDMI_PHY_CONF0 0x3000
  344. #define HDMI_PHY_TST0 0x3001
  345. #define HDMI_PHY_TST1 0x3002
  346. #define HDMI_PHY_TST2 0x3003
  347. #define HDMI_PHY_STAT0 0x3004
  348. #define HDMI_PHY_INT0 0x3005
  349. #define HDMI_PHY_MASK0 0x3006
  350. #define HDMI_PHY_POL0 0x3007
  351. /* HDMI Master PHY Registers */
  352. #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
  353. #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
  354. #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
  355. #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
  356. #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
  357. #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
  358. #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
  359. #define HDMI_PHY_I2CM_INT_ADDR 0x3027
  360. #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
  361. #define HDMI_PHY_I2CM_DIV_ADDR 0x3029
  362. #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
  363. #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
  364. #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
  365. #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
  366. #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
  367. #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
  368. #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
  369. #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
  370. #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
  371. /* Audio Sampler Registers */
  372. #define HDMI_AUD_CONF0 0x3100
  373. #define HDMI_AUD_CONF1 0x3101
  374. #define HDMI_AUD_INT 0x3102
  375. #define HDMI_AUD_CONF2 0x3103
  376. #define HDMI_AUD_N1 0x3200
  377. #define HDMI_AUD_N2 0x3201
  378. #define HDMI_AUD_N3 0x3202
  379. #define HDMI_AUD_CTS1 0x3203
  380. #define HDMI_AUD_CTS2 0x3204
  381. #define HDMI_AUD_CTS3 0x3205
  382. #define HDMI_AUD_INPUTCLKFS 0x3206
  383. #define HDMI_AUD_SPDIFINT 0x3302
  384. #define HDMI_AUD_CONF0_HBR 0x3400
  385. #define HDMI_AUD_HBR_STATUS 0x3401
  386. #define HDMI_AUD_HBR_INT 0x3402
  387. #define HDMI_AUD_HBR_POL 0x3403
  388. #define HDMI_AUD_HBR_MASK 0x3404
  389. /*
  390. * Generic Parallel Audio Interface Registers
  391. * Not used as GPAUD interface is not enabled in hw
  392. */
  393. #define HDMI_GP_CONF0 0x3500
  394. #define HDMI_GP_CONF1 0x3501
  395. #define HDMI_GP_CONF2 0x3502
  396. #define HDMI_GP_STAT 0x3503
  397. #define HDMI_GP_INT 0x3504
  398. #define HDMI_GP_MASK 0x3505
  399. #define HDMI_GP_POL 0x3506
  400. /* Audio DMA Registers */
  401. #define HDMI_AHB_DMA_CONF0 0x3600
  402. #define HDMI_AHB_DMA_START 0x3601
  403. #define HDMI_AHB_DMA_STOP 0x3602
  404. #define HDMI_AHB_DMA_THRSLD 0x3603
  405. #define HDMI_AHB_DMA_STRADDR0 0x3604
  406. #define HDMI_AHB_DMA_STRADDR1 0x3605
  407. #define HDMI_AHB_DMA_STRADDR2 0x3606
  408. #define HDMI_AHB_DMA_STRADDR3 0x3607
  409. #define HDMI_AHB_DMA_STPADDR0 0x3608
  410. #define HDMI_AHB_DMA_STPADDR1 0x3609
  411. #define HDMI_AHB_DMA_STPADDR2 0x360a
  412. #define HDMI_AHB_DMA_STPADDR3 0x360b
  413. #define HDMI_AHB_DMA_BSTADDR0 0x360c
  414. #define HDMI_AHB_DMA_BSTADDR1 0x360d
  415. #define HDMI_AHB_DMA_BSTADDR2 0x360e
  416. #define HDMI_AHB_DMA_BSTADDR3 0x360f
  417. #define HDMI_AHB_DMA_MBLENGTH0 0x3610
  418. #define HDMI_AHB_DMA_MBLENGTH1 0x3611
  419. #define HDMI_AHB_DMA_STAT 0x3612
  420. #define HDMI_AHB_DMA_INT 0x3613
  421. #define HDMI_AHB_DMA_MASK 0x3614
  422. #define HDMI_AHB_DMA_POL 0x3615
  423. #define HDMI_AHB_DMA_CONF1 0x3616
  424. #define HDMI_AHB_DMA_BUFFSTAT 0x3617
  425. #define HDMI_AHB_DMA_BUFFINT 0x3618
  426. #define HDMI_AHB_DMA_BUFFMASK 0x3619
  427. #define HDMI_AHB_DMA_BUFFPOL 0x361a
  428. /* Main Controller Registers */
  429. #define HDMI_MC_SFRDIV 0x4000
  430. #define HDMI_MC_CLKDIS 0x4001
  431. #define HDMI_MC_SWRSTZ 0x4002
  432. #define HDMI_MC_OPCTRL 0x4003
  433. #define HDMI_MC_FLOWCTRL 0x4004
  434. #define HDMI_MC_PHYRSTZ 0x4005
  435. #define HDMI_MC_LOCKONCLOCK 0x4006
  436. #define HDMI_MC_HEACPHY_RST 0x4007
  437. /* Color Space Converter Registers */
  438. #define HDMI_CSC_CFG 0x4100
  439. #define HDMI_CSC_SCALE 0x4101
  440. #define HDMI_CSC_COEF_A1_MSB 0x4102
  441. #define HDMI_CSC_COEF_A1_LSB 0x4103
  442. #define HDMI_CSC_COEF_A2_MSB 0x4104
  443. #define HDMI_CSC_COEF_A2_LSB 0x4105
  444. #define HDMI_CSC_COEF_A3_MSB 0x4106
  445. #define HDMI_CSC_COEF_A3_LSB 0x4107
  446. #define HDMI_CSC_COEF_A4_MSB 0x4108
  447. #define HDMI_CSC_COEF_A4_LSB 0x4109
  448. #define HDMI_CSC_COEF_B1_MSB 0x410A
  449. #define HDMI_CSC_COEF_B1_LSB 0x410B
  450. #define HDMI_CSC_COEF_B2_MSB 0x410C
  451. #define HDMI_CSC_COEF_B2_LSB 0x410D
  452. #define HDMI_CSC_COEF_B3_MSB 0x410E
  453. #define HDMI_CSC_COEF_B3_LSB 0x410F
  454. #define HDMI_CSC_COEF_B4_MSB 0x4110
  455. #define HDMI_CSC_COEF_B4_LSB 0x4111
  456. #define HDMI_CSC_COEF_C1_MSB 0x4112
  457. #define HDMI_CSC_COEF_C1_LSB 0x4113
  458. #define HDMI_CSC_COEF_C2_MSB 0x4114
  459. #define HDMI_CSC_COEF_C2_LSB 0x4115
  460. #define HDMI_CSC_COEF_C3_MSB 0x4116
  461. #define HDMI_CSC_COEF_C3_LSB 0x4117
  462. #define HDMI_CSC_COEF_C4_MSB 0x4118
  463. #define HDMI_CSC_COEF_C4_LSB 0x4119
  464. /* HDCP Encryption Engine Registers */
  465. #define HDMI_A_HDCPCFG0 0x5000
  466. #define HDMI_A_HDCPCFG1 0x5001
  467. #define HDMI_A_HDCPOBS0 0x5002
  468. #define HDMI_A_HDCPOBS1 0x5003
  469. #define HDMI_A_HDCPOBS2 0x5004
  470. #define HDMI_A_HDCPOBS3 0x5005
  471. #define HDMI_A_APIINTCLR 0x5006
  472. #define HDMI_A_APIINTSTAT 0x5007
  473. #define HDMI_A_APIINTMSK 0x5008
  474. #define HDMI_A_VIDPOLCFG 0x5009
  475. #define HDMI_A_OESSWCFG 0x500A
  476. #define HDMI_A_TIMER1SETUP0 0x500B
  477. #define HDMI_A_TIMER1SETUP1 0x500C
  478. #define HDMI_A_TIMER2SETUP0 0x500D
  479. #define HDMI_A_TIMER2SETUP1 0x500E
  480. #define HDMI_A_100MSCFG 0x500F
  481. #define HDMI_A_2SCFG0 0x5010
  482. #define HDMI_A_2SCFG1 0x5011
  483. #define HDMI_A_5SCFG0 0x5012
  484. #define HDMI_A_5SCFG1 0x5013
  485. #define HDMI_A_SRMVERLSB 0x5014
  486. #define HDMI_A_SRMVERMSB 0x5015
  487. #define HDMI_A_SRMCTRL 0x5016
  488. #define HDMI_A_SFRSETUP 0x5017
  489. #define HDMI_A_I2CHSETUP 0x5018
  490. #define HDMI_A_INTSETUP 0x5019
  491. #define HDMI_A_PRESETUP 0x501A
  492. #define HDMI_A_SRM_BASE 0x5020
  493. /* I2C Master Registers (E-DDC) */
  494. #define HDMI_I2CM_SLAVE 0x7E00
  495. #define HDMI_I2CM_ADDRESS 0x7E01
  496. #define HDMI_I2CM_DATAO 0x7E02
  497. #define HDMI_I2CM_DATAI 0x7E03
  498. #define HDMI_I2CM_OPERATION 0x7E04
  499. #define HDMI_I2CM_INT 0x7E05
  500. #define HDMI_I2CM_CTLINT 0x7E06
  501. #define HDMI_I2CM_DIV 0x7E07
  502. #define HDMI_I2CM_SEGADDR 0x7E08
  503. #define HDMI_I2CM_SOFTRSTZ 0x7E09
  504. #define HDMI_I2CM_SEGPTR 0x7E0A
  505. #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
  506. #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
  507. #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
  508. #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
  509. #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
  510. #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
  511. #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
  512. #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
  513. enum {
  514. /* PRODUCT_ID0 field values */
  515. HDMI_PRODUCT_ID0_HDMI_TX = 0xa0,
  516. /* PRODUCT_ID1 field values */
  517. HDMI_PRODUCT_ID1_HDCP = 0xc0,
  518. HDMI_PRODUCT_ID1_HDMI_RX = 0x02,
  519. HDMI_PRODUCT_ID1_HDMI_TX = 0x01,
  520. /* CONFIG0_ID field values */
  521. HDMI_CONFIG0_I2S = 0x10,
  522. HDMI_CONFIG0_CEC = 0x02,
  523. /* CONFIG1_ID field values */
  524. HDMI_CONFIG1_AHB = 0x01,
  525. /* CONFIG3_ID field values */
  526. HDMI_CONFIG3_AHBAUDDMA = 0x02,
  527. HDMI_CONFIG3_GPAUD = 0x01,
  528. /* IH_FC_INT2 field values */
  529. HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
  530. HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
  531. HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  532. /* IH_FC_STAT2 field values */
  533. HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
  534. HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
  535. HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  536. /* IH_PHY_STAT0 field values */
  537. HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
  538. HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
  539. HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
  540. HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
  541. HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
  542. HDMI_IH_PHY_STAT0_HPD = 0x1,
  543. /* IH_I2CM_STAT0 and IH_MUTE_I2CM_STAT0 field values */
  544. HDMI_IH_I2CM_STAT0_DONE = 0x2,
  545. HDMI_IH_I2CM_STAT0_ERROR = 0x1,
  546. /* IH_MUTE_I2CMPHY_STAT0 field values */
  547. HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
  548. HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
  549. /* IH_AHBDMAAUD_STAT0 field values */
  550. HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
  551. HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
  552. HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
  553. HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
  554. HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
  555. HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
  556. /* IH_MUTE_FC_STAT2 field values */
  557. HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
  558. HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
  559. HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  560. /* IH_MUTE_AHBDMAAUD_STAT0 field values */
  561. HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
  562. HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
  563. HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
  564. HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
  565. HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
  566. HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
  567. /* IH_MUTE field values */
  568. HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
  569. HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
  570. /* TX_INVID0 field values */
  571. HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
  572. HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
  573. HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
  574. HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
  575. HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
  576. /* TX_INSTUFFING field values */
  577. HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
  578. HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
  579. HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
  580. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
  581. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
  582. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
  583. HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
  584. HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
  585. HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
  586. /* VP_PR_CD field values */
  587. HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
  588. HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
  589. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
  590. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
  591. /* VP_STUFF field values */
  592. HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
  593. HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
  594. HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
  595. HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
  596. HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
  597. HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
  598. HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
  599. HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
  600. HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
  601. HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
  602. HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
  603. HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
  604. HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
  605. HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
  606. HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
  607. /* VP_CONF field values */
  608. HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
  609. HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
  610. HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
  611. HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
  612. HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
  613. HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
  614. HDMI_VP_CONF_PR_EN_MASK = 0x10,
  615. HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
  616. HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
  617. HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
  618. HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
  619. HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
  620. HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
  621. HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
  622. HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
  623. HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
  624. HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
  625. HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
  626. HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
  627. /* VP_REMAP field values */
  628. HDMI_VP_REMAP_MASK = 0x3,
  629. HDMI_VP_REMAP_YCC422_24bit = 0x2,
  630. HDMI_VP_REMAP_YCC422_20bit = 0x1,
  631. HDMI_VP_REMAP_YCC422_16bit = 0x0,
  632. /* FC_INVIDCONF field values */
  633. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
  634. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
  635. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
  636. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
  637. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
  638. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
  639. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
  640. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
  641. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
  642. HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
  643. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
  644. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
  645. HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
  646. HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
  647. HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
  648. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
  649. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
  650. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
  651. HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
  652. HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
  653. HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
  654. /* FC_AUDICONF0 field values */
  655. HDMI_FC_AUDICONF0_CC_OFFSET = 4,
  656. HDMI_FC_AUDICONF0_CC_MASK = 0x70,
  657. HDMI_FC_AUDICONF0_CT_OFFSET = 0,
  658. HDMI_FC_AUDICONF0_CT_MASK = 0xF,
  659. /* FC_AUDICONF1 field values */
  660. HDMI_FC_AUDICONF1_SS_OFFSET = 3,
  661. HDMI_FC_AUDICONF1_SS_MASK = 0x18,
  662. HDMI_FC_AUDICONF1_SF_OFFSET = 0,
  663. HDMI_FC_AUDICONF1_SF_MASK = 0x7,
  664. /* FC_AUDICONF3 field values */
  665. HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
  666. HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
  667. HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
  668. HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
  669. HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
  670. HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
  671. /* FC_AUDSCHNLS0 field values */
  672. HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
  673. HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
  674. HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
  675. HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
  676. /* FC_AUDSCHNLS3-6 field values */
  677. HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
  678. HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
  679. HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
  680. HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
  681. HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
  682. HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
  683. HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
  684. HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
  685. HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
  686. HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
  687. HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
  688. HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
  689. HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
  690. HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
  691. HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
  692. HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
  693. /* HDMI_FC_AUDSCHNLS7 field values */
  694. HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
  695. HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
  696. /* HDMI_FC_AUDSCHNLS8 field values */
  697. HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
  698. HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
  699. HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
  700. HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
  701. /* FC_AUDSCONF field values */
  702. HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
  703. HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
  704. HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
  705. HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
  706. HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
  707. HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
  708. /* FC_STAT2 field values */
  709. HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
  710. HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
  711. HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  712. /* FC_INT2 field values */
  713. HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
  714. HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
  715. HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  716. /* FC_MASK2 field values */
  717. HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
  718. HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
  719. HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
  720. /* FC_PRCONF field values */
  721. HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
  722. HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
  723. HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
  724. HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
  725. /* FC_PACKET_TX_EN field values */
  726. HDMI_FC_PACKET_TX_EN_DRM_MASK = 0x80,
  727. HDMI_FC_PACKET_TX_EN_DRM_ENABLE = 0x80,
  728. HDMI_FC_PACKET_TX_EN_DRM_DISABLE = 0x00,
  729. /* FC_AVICONF0-FC_AVICONF3 field values */
  730. HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
  731. HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
  732. HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
  733. HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
  734. HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
  735. HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
  736. HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
  737. HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
  738. HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
  739. HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
  740. HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
  741. HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
  742. HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
  743. HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
  744. HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
  745. HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
  746. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
  747. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
  748. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
  749. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
  750. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
  751. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
  752. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
  753. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
  754. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
  755. HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
  756. HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
  757. HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
  758. HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
  759. HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
  760. HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
  761. HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
  762. HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
  763. HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
  764. HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
  765. HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
  766. HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
  767. HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
  768. HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
  769. HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
  770. HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
  771. HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
  772. HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
  773. HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
  774. HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
  775. HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
  776. HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
  777. HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
  778. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
  779. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
  780. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
  781. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
  782. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
  783. HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
  784. HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
  785. HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
  786. /* FC_DBGFORCE field values */
  787. HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
  788. HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
  789. /* FC_DATAUTO0 field values */
  790. HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
  791. HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
  792. /* PHY_CONF0 field values */
  793. HDMI_PHY_CONF0_PDZ_MASK = 0x80,
  794. HDMI_PHY_CONF0_PDZ_OFFSET = 7,
  795. HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
  796. HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
  797. HDMI_PHY_CONF0_SVSRET_MASK = 0x20,
  798. HDMI_PHY_CONF0_SVSRET_OFFSET = 5,
  799. HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
  800. HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
  801. HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
  802. HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
  803. HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
  804. HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
  805. HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
  806. HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
  807. HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
  808. HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
  809. /* PHY_TST0 field values */
  810. HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
  811. HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
  812. HDMI_PHY_TST0_TSTEN_MASK = 0x10,
  813. HDMI_PHY_TST0_TSTEN_OFFSET = 4,
  814. HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
  815. HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
  816. /* PHY_STAT0 field values */
  817. HDMI_PHY_RX_SENSE3 = 0x80,
  818. HDMI_PHY_RX_SENSE2 = 0x40,
  819. HDMI_PHY_RX_SENSE1 = 0x20,
  820. HDMI_PHY_RX_SENSE0 = 0x10,
  821. HDMI_PHY_HPD = 0x02,
  822. HDMI_PHY_TX_PHY_LOCK = 0x01,
  823. /* PHY_I2CM_SLAVE_ADDR field values */
  824. #ifdef CONFIG_SOC_THEAD_LIGHT_EMU
  825. HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x54,
  826. #else
  827. HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
  828. #endif
  829. HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
  830. /* PHY_I2CM_OPERATION_ADDR field values */
  831. HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
  832. HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
  833. /* HDMI_PHY_I2CM_INT_ADDR */
  834. HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
  835. HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
  836. /* HDMI_PHY_I2CM_CTLINT_ADDR */
  837. HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
  838. HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
  839. HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
  840. HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
  841. /* AUD_CONF0 field values */
  842. HDMI_AUD_CONF0_SW_RESET = 0x80,
  843. HDMI_AUD_CONF0_I2S_SELECT = 0x20,
  844. HDMI_AUD_CONF0_I2S_EN3 = 0x08,
  845. HDMI_AUD_CONF0_I2S_EN2 = 0x04,
  846. HDMI_AUD_CONF0_I2S_EN1 = 0x02,
  847. HDMI_AUD_CONF0_I2S_EN0 = 0x01,
  848. /* AUD_CONF1 field values */
  849. HDMI_AUD_CONF1_MODE_I2S = 0x00,
  850. HDMI_AUD_CONF1_MODE_RIGHT_J = 0x20,
  851. HDMI_AUD_CONF1_MODE_LEFT_J = 0x40,
  852. HDMI_AUD_CONF1_MODE_BURST_1 = 0x60,
  853. HDMI_AUD_CONF1_MODE_BURST_2 = 0x80,
  854. HDMI_AUD_CONF1_WIDTH_16 = 0x10,
  855. HDMI_AUD_CONF1_WIDTH_24 = 0x18,
  856. /* AUD_CTS3 field values */
  857. HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
  858. HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
  859. HDMI_AUD_CTS3_N_SHIFT_1 = 0,
  860. HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
  861. HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
  862. HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
  863. HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
  864. HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
  865. /* note that the CTS3 MANUAL bit has been removed
  866. from our part. Can't set it, will read as 0. */
  867. HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
  868. HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
  869. /* HDMI_AUD_INPUTCLKFS field values */
  870. HDMI_AUD_INPUTCLKFS_128FS = 0,
  871. HDMI_AUD_INPUTCLKFS_256FS = 1,
  872. HDMI_AUD_INPUTCLKFS_512FS = 2,
  873. HDMI_AUD_INPUTCLKFS_64FS = 4,
  874. /* AHB_DMA_CONF0 field values */
  875. HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
  876. HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
  877. HDMI_AHB_DMA_CONF0_HBR = 0x10,
  878. HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
  879. HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
  880. HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
  881. HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
  882. HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
  883. HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
  884. HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
  885. HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
  886. /* HDMI_AHB_DMA_START field values */
  887. HDMI_AHB_DMA_START_START_OFFSET = 0,
  888. HDMI_AHB_DMA_START_START_MASK = 0x01,
  889. /* HDMI_AHB_DMA_STOP field values */
  890. HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
  891. HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
  892. /* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
  893. HDMI_AHB_DMA_DONE = 0x80,
  894. HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
  895. HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
  896. HDMI_AHB_DMA_ERROR = 0x10,
  897. HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
  898. HDMI_AHB_DMA_FIFO_FULL = 0x02,
  899. HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
  900. /* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT,AHB_DMA_BUFFMASK,AHB_DMA_BUFFPOL values */
  901. HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
  902. HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
  903. /* MC_CLKDIS field values */
  904. HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
  905. HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
  906. HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
  907. HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
  908. HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
  909. HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
  910. HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
  911. /* MC_SWRSTZ field values */
  912. HDMI_MC_SWRSTZ_I2SSWRST_REQ = 0x08,
  913. HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
  914. /* MC_FLOWCTRL field values */
  915. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
  916. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
  917. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
  918. /* MC_PHYRSTZ field values */
  919. HDMI_MC_PHYRSTZ_PHYRSTZ = 0x01,
  920. /* MC_HEACPHY_RST field values */
  921. HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
  922. HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
  923. /* CSC_CFG field values */
  924. HDMI_CSC_CFG_INTMODE_MASK = 0x30,
  925. HDMI_CSC_CFG_INTMODE_OFFSET = 4,
  926. HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
  927. HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
  928. HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
  929. HDMI_CSC_CFG_DECMODE_MASK = 0x3,
  930. HDMI_CSC_CFG_DECMODE_OFFSET = 0,
  931. HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
  932. HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
  933. HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
  934. HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
  935. /* CSC_SCALE field values */
  936. HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
  937. HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
  938. HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
  939. HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
  940. HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
  941. HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
  942. /* A_HDCPCFG0 field values */
  943. HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
  944. HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
  945. HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
  946. HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
  947. HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
  948. HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
  949. HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
  950. HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
  951. HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
  952. HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
  953. HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
  954. HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
  955. HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
  956. HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
  957. HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
  958. HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
  959. HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
  960. HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
  961. HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
  962. HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
  963. HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
  964. HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
  965. HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
  966. HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
  967. /* A_HDCPCFG1 field values */
  968. HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
  969. HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
  970. HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
  971. HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
  972. HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
  973. HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
  974. HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
  975. HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
  976. HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
  977. HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
  978. HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
  979. /* A_VIDPOLCFG field values */
  980. HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
  981. HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
  982. HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
  983. HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
  984. HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
  985. HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
  986. HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
  987. HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
  988. HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
  989. HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
  990. HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
  991. /* I2CM_OPERATION field values */
  992. HDMI_I2CM_OPERATION_WRITE = 0x10,
  993. HDMI_I2CM_OPERATION_READ_EXT = 0x2,
  994. HDMI_I2CM_OPERATION_READ = 0x1,
  995. /* I2CM_INT field values */
  996. HDMI_I2CM_INT_DONE_POL = 0x8,
  997. HDMI_I2CM_INT_DONE_MASK = 0x4,
  998. /* I2CM_CTLINT field values */
  999. HDMI_I2CM_CTLINT_NAC_POL = 0x80,
  1000. HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
  1001. HDMI_I2CM_CTLINT_ARB_POL = 0x8,
  1002. HDMI_I2CM_CTLINT_ARB_MASK = 0x4,
  1003. };
  1004. /*
  1005. * HDMI 3D TX PHY registers
  1006. */
  1007. #define HDMI_3D_TX_PHY_PWRCTRL 0x00
  1008. #define HDMI_3D_TX_PHY_SERDIVCTRL 0x01
  1009. #define HDMI_3D_TX_PHY_SERCKCTRL 0x02
  1010. #define HDMI_3D_TX_PHY_SERCKKILLCTRL 0x03
  1011. #define HDMI_3D_TX_PHY_TXRESCTRL 0x04
  1012. #define HDMI_3D_TX_PHY_CKCALCTRL 0x05
  1013. #define HDMI_3D_TX_PHY_CPCE_CTRL 0x06
  1014. #define HDMI_3D_TX_PHY_TXCLKMEASCTRL 0x07
  1015. #define HDMI_3D_TX_PHY_TXMEASCTRL 0x08
  1016. #define HDMI_3D_TX_PHY_CKSYMTXCTRL 0x09
  1017. #define HDMI_3D_TX_PHY_CMPSEQCTRL 0x0a
  1018. #define HDMI_3D_TX_PHY_CMPPWRCTRL 0x0b
  1019. #define HDMI_3D_TX_PHY_CMPMODECTRL 0x0c
  1020. #define HDMI_3D_TX_PHY_MEASCTRL 0x0d
  1021. #define HDMI_3D_TX_PHY_VLEVCTRL 0x0e
  1022. #define HDMI_3D_TX_PHY_D2ACTRL 0x0f
  1023. #define HDMI_3D_TX_PHY_CURRCTRL 0x10
  1024. #define HDMI_3D_TX_PHY_DRVANACTRL 0x11
  1025. #define HDMI_3D_TX_PHY_PLLMEASCTRL 0x12
  1026. #define HDMI_3D_TX_PHY_PLLPHBYCTRL 0x13
  1027. #define HDMI_3D_TX_PHY_GRP_CTRL 0x14
  1028. #define HDMI_3D_TX_PHY_GMPCTRL 0x15
  1029. #define HDMI_3D_TX_PHY_MPLLMEASCTRL 0x16
  1030. #define HDMI_3D_TX_PHY_MSM_CTRL 0x17
  1031. #define HDMI_3D_TX_PHY_SCRPB_STATUS 0x18
  1032. #define HDMI_3D_TX_PHY_TXTERM 0x19
  1033. #define HDMI_3D_TX_PHY_PTRPT_ENBL 0x1a
  1034. #define HDMI_3D_TX_PHY_PATTERNGEN 0x1b
  1035. #define HDMI_3D_TX_PHY_SDCAP_MODE 0x1c
  1036. #define HDMI_3D_TX_PHY_SCOPEMODE 0x1d
  1037. #define HDMI_3D_TX_PHY_DIGTXMODE 0x1e
  1038. #define HDMI_3D_TX_PHY_STR_STATUS 0x1f
  1039. #define HDMI_3D_TX_PHY_SCOPECNT0 0x20
  1040. #define HDMI_3D_TX_PHY_SCOPECNT1 0x21
  1041. #define HDMI_3D_TX_PHY_SCOPECNT2 0x22
  1042. #define HDMI_3D_TX_PHY_SCOPECNTCLK 0x23
  1043. #define HDMI_3D_TX_PHY_SCOPESAMPLE 0x24
  1044. #define HDMI_3D_TX_PHY_SCOPECNTMSB01 0x25
  1045. #define HDMI_3D_TX_PHY_SCOPECNTMSB2CK 0x26
  1046. /* HDMI_3D_TX_PHY_CKCALCTRL values */
  1047. #define HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE BIT(15)
  1048. /* HDMI_3D_TX_PHY_MSM_CTRL values */
  1049. #define HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK BIT(13)
  1050. #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_CLK_REF_MPLL (0 << 1)
  1051. #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_OFF (1 << 1)
  1052. #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_PCLK (2 << 1)
  1053. #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK (3 << 1)
  1054. #define HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL BIT(0)
  1055. /* HDMI_3D_TX_PHY_PTRPT_ENBL values */
  1056. #define HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE BIT(15)
  1057. #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2 BIT(8)
  1058. #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1 BIT(7)
  1059. #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0 BIT(6)
  1060. #define HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB BIT(5)
  1061. #define HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB BIT(4)
  1062. #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB BIT(3)
  1063. #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY BIT(2)
  1064. #define HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB BIT(1)
  1065. #define HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB BIT(0)
  1066. #endif /* __DW_HDMI_H__ */