dw-hdmi.c 99 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DesignWare High-Definition Multimedia Interface (HDMI) driver
  4. *
  5. * Copyright (C) 2013-2015 Mentor Graphics Inc.
  6. * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
  7. * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <linux/hdmi.h>
  13. #include <linux/irq.h>
  14. #include <linux/module.h>
  15. #include <linux/mutex.h>
  16. #include <linux/of_device.h>
  17. #include <linux/pinctrl/consumer.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/regmap.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/spinlock.h>
  22. #include <media/cec-notifier.h>
  23. #include <uapi/linux/media-bus-format.h>
  24. #include <uapi/linux/videodev2.h>
  25. #include <drm/bridge/dw_hdmi.h>
  26. #include <drm/drm_atomic.h>
  27. #include <drm/drm_atomic_helper.h>
  28. #include <drm/drm_bridge.h>
  29. #include <drm/drm_edid.h>
  30. #include <drm/drm_of.h>
  31. #include <drm/drm_print.h>
  32. #include <drm/drm_probe_helper.h>
  33. #include <drm/drm_scdc_helper.h>
  34. #include "dw-hdmi-audio.h"
  35. #include "dw-hdmi-cec.h"
  36. #include "dw-hdmi.h"
  37. #define DDC_CI_ADDR 0x37
  38. #define DDC_SEGMENT_ADDR 0x30
  39. #define HDMI_EDID_LEN 512
  40. /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
  41. #define SCDC_MIN_SOURCE_VERSION 0x1
  42. #define HDMI14_MAX_TMDSCLK 340000000
  43. #define HDMI_DDC_CHECK_MAX_RETRIES 100
  44. #define HDMI_DDC_CHECK_NORMAL 2
  45. #define HDMI_SCRAMBLING_RETRIES 20
  46. enum hdmi_datamap {
  47. RGB444_8B = 0x01,
  48. RGB444_10B = 0x03,
  49. RGB444_12B = 0x05,
  50. RGB444_16B = 0x07,
  51. YCbCr444_8B = 0x09,
  52. YCbCr444_10B = 0x0B,
  53. YCbCr444_12B = 0x0D,
  54. YCbCr444_16B = 0x0F,
  55. YCbCr422_8B = 0x16,
  56. YCbCr422_10B = 0x14,
  57. YCbCr422_12B = 0x12,
  58. };
  59. static const u16 csc_coeff_default[3][4] = {
  60. { 0x2000, 0x0000, 0x0000, 0x0000 },
  61. { 0x0000, 0x2000, 0x0000, 0x0000 },
  62. { 0x0000, 0x0000, 0x2000, 0x0000 }
  63. };
  64. static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  65. { 0x2000, 0x6926, 0x74fd, 0x010e },
  66. { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  67. { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  68. };
  69. static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  70. { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  71. { 0x2000, 0x3264, 0x0000, 0x7e6d },
  72. { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  73. };
  74. static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  75. { 0x2591, 0x1322, 0x074b, 0x0000 },
  76. { 0x6535, 0x2000, 0x7acc, 0x0200 },
  77. { 0x6acd, 0x7534, 0x2000, 0x0200 }
  78. };
  79. static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  80. { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  81. { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  82. { 0x6756, 0x78ab, 0x2000, 0x0200 }
  83. };
  84. static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
  85. { 0x1b7c, 0x0000, 0x0000, 0x0020 },
  86. { 0x0000, 0x1b7c, 0x0000, 0x0020 },
  87. { 0x0000, 0x0000, 0x1b7c, 0x0020 }
  88. };
  89. struct hdmi_vmode {
  90. bool mdataenablepolarity;
  91. unsigned int mpixelclock;
  92. unsigned int mpixelrepetitioninput;
  93. unsigned int mpixelrepetitionoutput;
  94. unsigned int mtmdsclock;
  95. };
  96. struct hdmi_data_info {
  97. unsigned int enc_in_bus_format;
  98. unsigned int enc_out_bus_format;
  99. unsigned int enc_in_encoding;
  100. unsigned int enc_out_encoding;
  101. unsigned int pix_repet_factor;
  102. unsigned int hdcp_enable;
  103. struct hdmi_vmode video_mode;
  104. bool rgb_limited_range;
  105. };
  106. struct dw_hdmi_i2c {
  107. struct i2c_adapter adap;
  108. struct mutex lock; /* used to serialize data transfers */
  109. struct completion cmp;
  110. u8 stat;
  111. u8 slave_reg;
  112. bool is_regaddr;
  113. bool is_segment;
  114. };
  115. struct dw_hdmi_phy_data {
  116. enum dw_hdmi_phy_type type;
  117. const char *name;
  118. unsigned int gen;
  119. bool has_svsret;
  120. int (*configure)(struct dw_hdmi *hdmi,
  121. const struct dw_hdmi_plat_data *pdata,
  122. unsigned long mpixelclock);
  123. };
  124. struct dw_hdmi {
  125. struct drm_connector connector;
  126. struct drm_bridge bridge;
  127. unsigned int version;
  128. struct platform_device *audio;
  129. struct platform_device *cec;
  130. struct device *dev;
  131. struct clk *isfr_clk;
  132. struct clk *iahb_clk;
  133. struct clk *cec_clk;
  134. struct clk *pix_clk;
  135. struct clk *i2s_clk;
  136. struct dw_hdmi_i2c *i2c;
  137. struct hdmi_data_info hdmi_data;
  138. const struct dw_hdmi_plat_data *plat_data;
  139. int vic;
  140. u8 edid[HDMI_EDID_LEN];
  141. struct {
  142. const struct dw_hdmi_phy_ops *ops;
  143. const char *name;
  144. void *data;
  145. bool enabled;
  146. } phy;
  147. struct drm_display_mode previous_mode;
  148. struct i2c_adapter *ddc;
  149. void __iomem *regs;
  150. bool sink_is_hdmi;
  151. bool sink_has_audio;
  152. struct pinctrl *pinctrl;
  153. struct pinctrl_state *default_state;
  154. struct pinctrl_state *unwedge_state;
  155. struct mutex mutex; /* for state below and previous_mode */
  156. enum drm_connector_force force; /* mutex-protected force state */
  157. struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */
  158. bool disabled; /* DRM has disabled our bridge */
  159. bool bridge_is_on; /* indicates the bridge is on */
  160. bool rxsense; /* rxsense state */
  161. u8 phy_mask; /* desired phy int mask settings */
  162. u8 mc_clkdis; /* clock disable register */
  163. spinlock_t audio_lock;
  164. struct mutex audio_mutex;
  165. unsigned int sample_rate;
  166. unsigned int audio_cts;
  167. unsigned int audio_n;
  168. bool audio_enable;
  169. unsigned int reg_shift;
  170. struct regmap *regm;
  171. void (*enable_audio)(struct dw_hdmi *hdmi);
  172. void (*disable_audio)(struct dw_hdmi *hdmi);
  173. struct mutex cec_notifier_mutex;
  174. struct cec_notifier *cec_notifier;
  175. hdmi_codec_plugged_cb plugged_cb;
  176. struct device *codec_dev;
  177. enum drm_connector_status last_connector_result;
  178. };
  179. #define HDMI_IH_PHY_STAT0_RX_SENSE \
  180. (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
  181. HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
  182. #define HDMI_PHY_RX_SENSE \
  183. (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
  184. HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
  185. static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
  186. {
  187. regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
  188. }
  189. static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
  190. {
  191. unsigned int val = 0;
  192. regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
  193. return val;
  194. }
  195. static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
  196. {
  197. if (hdmi->plugged_cb && hdmi->codec_dev)
  198. hdmi->plugged_cb(hdmi->codec_dev, plugged);
  199. }
  200. int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
  201. struct device *codec_dev)
  202. {
  203. bool plugged;
  204. mutex_lock(&hdmi->mutex);
  205. hdmi->plugged_cb = fn;
  206. hdmi->codec_dev = codec_dev;
  207. plugged = hdmi->last_connector_result == connector_status_connected;
  208. handle_plugged_change(hdmi, plugged);
  209. mutex_unlock(&hdmi->mutex);
  210. return 0;
  211. }
  212. EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);
  213. static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
  214. {
  215. regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
  216. }
  217. static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
  218. u8 shift, u8 mask)
  219. {
  220. hdmi_modb(hdmi, data << shift, mask, reg);
  221. }
  222. static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
  223. {
  224. hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
  225. HDMI_PHY_I2CM_INT_ADDR);
  226. hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
  227. HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
  228. HDMI_PHY_I2CM_CTLINT_ADDR);
  229. /* Software reset */
  230. hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
  231. /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
  232. hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
  233. /* Set done, not acknowledged and arbitration interrupt polarities */
  234. hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
  235. hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
  236. HDMI_I2CM_CTLINT);
  237. /* Clear DONE and ERROR interrupts */
  238. hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
  239. HDMI_IH_I2CM_STAT0);
  240. /* Mute DONE and ERROR interrupts */
  241. hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
  242. HDMI_IH_MUTE_I2CM_STAT0);
  243. }
  244. static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
  245. {
  246. /* If no unwedge state then give up */
  247. if (!hdmi->unwedge_state)
  248. return false;
  249. dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
  250. /*
  251. * This is a huge hack to workaround a problem where the dw_hdmi i2c
  252. * bus could sometimes get wedged. Once wedged there doesn't appear
  253. * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
  254. * other than pulsing the SDA line.
  255. *
  256. * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
  257. * by:
  258. * 1. Remux the pin as a GPIO output, driven low.
  259. * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
  260. * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
  261. *
  262. * At the moment of remuxing, the line will still be low due to its
  263. * recent stint as an output, but then it will be pulled high by the
  264. * (presumed) external pullup. dw_hdmi seems to see this as a rising
  265. * edge and that seems to get it out of its jam.
  266. *
  267. * This wedging was only ever seen on one TV, and only on one of
  268. * its HDMI ports. It happened when the TV was powered on while the
  269. * device was plugged in. A scope trace shows the TV bringing both SDA
  270. * and SCL low, then bringing them both back up at roughly the same
  271. * time. Presumably this confuses dw_hdmi because it saw activity but
  272. * no real STOP (maybe it thinks there's another master on the bus?).
  273. * Giving it a clean rising edge of SDA while SCL is already high
  274. * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
  275. * of its stupor.
  276. *
  277. * Note that after coming back alive, transfers seem to immediately
  278. * resume, so if we unwedge due to a timeout we should wait a little
  279. * longer for our transfer to finish, since it might have just started
  280. * now.
  281. */
  282. pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
  283. msleep(10);
  284. pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
  285. return true;
  286. }
  287. static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
  288. {
  289. struct dw_hdmi_i2c *i2c = hdmi->i2c;
  290. int stat;
  291. stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
  292. if (!stat) {
  293. /* If we can't unwedge, return timeout */
  294. if (!dw_hdmi_i2c_unwedge(hdmi))
  295. return -EAGAIN;
  296. /* We tried to unwedge; give it another chance */
  297. stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
  298. if (!stat)
  299. return -EAGAIN;
  300. }
  301. /* Check for error condition on the bus */
  302. if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
  303. return -EIO;
  304. return 0;
  305. }
  306. static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
  307. unsigned char *buf, unsigned int length)
  308. {
  309. struct dw_hdmi_i2c *i2c = hdmi->i2c;
  310. int ret;
  311. if (!i2c->is_regaddr) {
  312. dev_dbg(hdmi->dev, "set read register address to 0\n");
  313. i2c->slave_reg = 0x00;
  314. i2c->is_regaddr = true;
  315. }
  316. while (length--) {
  317. reinit_completion(&i2c->cmp);
  318. hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
  319. if (i2c->is_segment)
  320. hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
  321. HDMI_I2CM_OPERATION);
  322. else
  323. hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
  324. HDMI_I2CM_OPERATION);
  325. ret = dw_hdmi_i2c_wait(hdmi);
  326. if (ret)
  327. return ret;
  328. *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
  329. }
  330. i2c->is_segment = false;
  331. return 0;
  332. }
  333. static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
  334. unsigned char *buf, unsigned int length)
  335. {
  336. struct dw_hdmi_i2c *i2c = hdmi->i2c;
  337. int ret;
  338. if (!i2c->is_regaddr) {
  339. /* Use the first write byte as register address */
  340. i2c->slave_reg = buf[0];
  341. length--;
  342. buf++;
  343. i2c->is_regaddr = true;
  344. }
  345. while (length--) {
  346. reinit_completion(&i2c->cmp);
  347. hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
  348. hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
  349. hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
  350. HDMI_I2CM_OPERATION);
  351. ret = dw_hdmi_i2c_wait(hdmi);
  352. if (ret)
  353. return ret;
  354. }
  355. return 0;
  356. }
  357. static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
  358. struct i2c_msg *msgs, int num)
  359. {
  360. struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
  361. struct dw_hdmi_i2c *i2c = hdmi->i2c;
  362. u8 addr = msgs[0].addr;
  363. int i, ret = 0;
  364. if (addr == DDC_CI_ADDR)
  365. /*
  366. * The internal I2C controller does not support the multi-byte
  367. * read and write operations needed for DDC/CI.
  368. * TOFIX: Blacklist the DDC/CI address until we filter out
  369. * unsupported I2C operations.
  370. */
  371. return -EOPNOTSUPP;
  372. dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
  373. for (i = 0; i < num; i++) {
  374. if (msgs[i].len == 0) {
  375. dev_dbg(hdmi->dev,
  376. "unsupported transfer %d/%d, no data\n",
  377. i + 1, num);
  378. return -EOPNOTSUPP;
  379. }
  380. }
  381. mutex_lock(&i2c->lock);
  382. /* Unmute DONE and ERROR interrupts */
  383. hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
  384. /* Set slave device address taken from the first I2C message */
  385. hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
  386. /* Set slave device register address on transfer */
  387. i2c->is_regaddr = false;
  388. /* Set segment pointer for I2C extended read mode operation */
  389. i2c->is_segment = false;
  390. for (i = 0; i < num; i++) {
  391. dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
  392. i + 1, num, msgs[i].len, msgs[i].flags);
  393. if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
  394. i2c->is_segment = true;
  395. hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
  396. hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
  397. } else {
  398. if (msgs[i].flags & I2C_M_RD)
  399. ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
  400. msgs[i].len);
  401. else
  402. ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
  403. msgs[i].len);
  404. }
  405. if (ret < 0)
  406. break;
  407. }
  408. if (!ret)
  409. ret = num;
  410. /* Mute DONE and ERROR interrupts */
  411. hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
  412. HDMI_IH_MUTE_I2CM_STAT0);
  413. mutex_unlock(&i2c->lock);
  414. return ret;
  415. }
  416. static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
  417. {
  418. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  419. }
  420. static const struct i2c_algorithm dw_hdmi_algorithm = {
  421. .master_xfer = dw_hdmi_i2c_xfer,
  422. .functionality = dw_hdmi_i2c_func,
  423. };
  424. static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
  425. {
  426. struct i2c_adapter *adap;
  427. struct dw_hdmi_i2c *i2c;
  428. int ret;
  429. i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
  430. if (!i2c)
  431. return ERR_PTR(-ENOMEM);
  432. mutex_init(&i2c->lock);
  433. init_completion(&i2c->cmp);
  434. adap = &i2c->adap;
  435. adap->class = I2C_CLASS_DDC;
  436. adap->owner = THIS_MODULE;
  437. adap->dev.parent = hdmi->dev;
  438. adap->algo = &dw_hdmi_algorithm;
  439. strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
  440. i2c_set_adapdata(adap, hdmi);
  441. ret = i2c_add_adapter(adap);
  442. if (ret) {
  443. dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
  444. devm_kfree(hdmi->dev, i2c);
  445. return ERR_PTR(ret);
  446. }
  447. hdmi->i2c = i2c;
  448. dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
  449. return adap;
  450. }
  451. static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
  452. unsigned int n)
  453. {
  454. /* Must be set/cleared first */
  455. hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
  456. /* nshift factor = 0 */
  457. hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
  458. /* Use automatic CTS generation mode when CTS is not set */
  459. if (cts)
  460. hdmi_writeb(hdmi, ((cts >> 16) &
  461. HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
  462. HDMI_AUD_CTS3_CTS_MANUAL,
  463. HDMI_AUD_CTS3);
  464. else
  465. hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
  466. hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
  467. hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
  468. hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
  469. hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
  470. hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
  471. }
  472. static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
  473. {
  474. unsigned int n = (128 * freq) / 1000;
  475. unsigned int mult = 1;
  476. while (freq > 48000) {
  477. mult *= 2;
  478. freq /= 2;
  479. }
  480. switch (freq) {
  481. case 32000:
  482. if (pixel_clk == 25175000)
  483. n = 4576;
  484. else if (pixel_clk == 27027000)
  485. n = 4096;
  486. else if (pixel_clk == 74176000 || pixel_clk == 148352000)
  487. n = 11648;
  488. else
  489. n = 4096;
  490. n *= mult;
  491. break;
  492. case 44100:
  493. if (pixel_clk == 25175000)
  494. n = 7007;
  495. else if (pixel_clk == 74176000)
  496. n = 17836;
  497. else if (pixel_clk == 148352000)
  498. n = 8918;
  499. else
  500. n = 6272;
  501. n *= mult;
  502. break;
  503. case 48000:
  504. if (pixel_clk == 25175000)
  505. n = 6864;
  506. else if (pixel_clk == 27027000)
  507. n = 6144;
  508. else if (pixel_clk == 74176000)
  509. n = 11648;
  510. else if (pixel_clk == 148352000)
  511. n = 5824;
  512. else
  513. n = 6144;
  514. n *= mult;
  515. break;
  516. default:
  517. break;
  518. }
  519. return n;
  520. }
  521. /*
  522. * When transmitting IEC60958 linear PCM audio, these registers allow to
  523. * configure the channel status information of all the channel status
  524. * bits in the IEC60958 frame. For the moment this configuration is only
  525. * used when the I2S audio interface, General Purpose Audio (GPA),
  526. * or AHB audio DMA (AHBAUDDMA) interface is active
  527. * (for S/PDIF interface this information comes from the stream).
  528. */
  529. void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
  530. u8 *channel_status)
  531. {
  532. /*
  533. * Set channel status register for frequency and word length.
  534. * Use default values for other registers.
  535. */
  536. hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
  537. hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
  538. }
  539. EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
  540. static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
  541. unsigned long pixel_clk, unsigned int sample_rate)
  542. {
  543. unsigned long ftdms = pixel_clk;
  544. unsigned int n, cts;
  545. u8 config3;
  546. u64 tmp;
  547. n = hdmi_compute_n(sample_rate, pixel_clk);
  548. config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
  549. /* Only compute CTS when using internal AHB audio */
  550. if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
  551. /*
  552. * Compute the CTS value from the N value. Note that CTS and N
  553. * can be up to 20 bits in total, so we need 64-bit math. Also
  554. * note that our TDMS clock is not fully accurate; it is
  555. * accurate to kHz. This can introduce an unnecessary remainder
  556. * in the calculation below, so we don't try to warn about that.
  557. */
  558. tmp = (u64)ftdms * n;
  559. do_div(tmp, 128 * sample_rate);
  560. cts = tmp;
  561. dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
  562. __func__, sample_rate,
  563. ftdms / 1000000, (ftdms / 1000) % 1000,
  564. n, cts);
  565. } else {
  566. cts = 0;
  567. }
  568. hdmi->audio_enable = true;
  569. spin_lock_irq(&hdmi->audio_lock);
  570. hdmi->audio_n = n;
  571. hdmi->audio_cts = cts;
  572. hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
  573. hdmi_writeb(hdmi, 0x4, HDMI_AUD_INPUTCLKFS);
  574. spin_unlock_irq(&hdmi->audio_lock);
  575. }
  576. static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
  577. {
  578. mutex_lock(&hdmi->audio_mutex);
  579. hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
  580. mutex_unlock(&hdmi->audio_mutex);
  581. }
  582. static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
  583. {
  584. mutex_lock(&hdmi->audio_mutex);
  585. hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
  586. hdmi->sample_rate);
  587. mutex_unlock(&hdmi->audio_mutex);
  588. }
  589. void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
  590. {
  591. mutex_lock(&hdmi->audio_mutex);
  592. hdmi->sample_rate = rate;
  593. hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
  594. hdmi->sample_rate);
  595. mutex_unlock(&hdmi->audio_mutex);
  596. }
  597. EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
  598. void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
  599. {
  600. u8 layout;
  601. mutex_lock(&hdmi->audio_mutex);
  602. /*
  603. * For >2 channel PCM audio, we need to select layout 1
  604. * and set an appropriate channel map.
  605. */
  606. if (cnt > 2)
  607. layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
  608. else
  609. layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
  610. hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
  611. HDMI_FC_AUDSCONF);
  612. /* Set the audio infoframes channel count */
  613. hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
  614. HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
  615. mutex_unlock(&hdmi->audio_mutex);
  616. }
  617. EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
  618. void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
  619. {
  620. mutex_lock(&hdmi->audio_mutex);
  621. hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
  622. mutex_unlock(&hdmi->audio_mutex);
  623. }
  624. EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
  625. static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
  626. {
  627. if (enable)
  628. hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
  629. else
  630. hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
  631. hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
  632. }
  633. static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
  634. {
  635. if (!hdmi->curr_conn)
  636. return NULL;
  637. return hdmi->curr_conn->eld;
  638. }
  639. static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
  640. {
  641. hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
  642. }
  643. static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
  644. {
  645. hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
  646. }
  647. static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
  648. {
  649. hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
  650. hdmi_enable_audio_clk(hdmi, true);
  651. }
  652. static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
  653. {
  654. hdmi_enable_audio_clk(hdmi, false);
  655. }
  656. void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
  657. {
  658. unsigned long flags;
  659. spin_lock_irqsave(&hdmi->audio_lock, flags);
  660. hdmi->audio_enable = true;
  661. if (hdmi->enable_audio)
  662. hdmi->enable_audio(hdmi);
  663. spin_unlock_irqrestore(&hdmi->audio_lock, flags);
  664. }
  665. EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
  666. void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
  667. {
  668. unsigned long flags;
  669. spin_lock_irqsave(&hdmi->audio_lock, flags);
  670. hdmi->audio_enable = false;
  671. if (hdmi->disable_audio)
  672. hdmi->disable_audio(hdmi);
  673. spin_unlock_irqrestore(&hdmi->audio_lock, flags);
  674. }
  675. EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
  676. static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
  677. {
  678. switch (bus_format) {
  679. case MEDIA_BUS_FMT_RGB888_1X24:
  680. case MEDIA_BUS_FMT_RGB101010_1X30:
  681. case MEDIA_BUS_FMT_RGB121212_1X36:
  682. case MEDIA_BUS_FMT_RGB161616_1X48:
  683. return true;
  684. default:
  685. return false;
  686. }
  687. }
  688. static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
  689. {
  690. switch (bus_format) {
  691. case MEDIA_BUS_FMT_YUV8_1X24:
  692. case MEDIA_BUS_FMT_YUV10_1X30:
  693. case MEDIA_BUS_FMT_YUV12_1X36:
  694. case MEDIA_BUS_FMT_YUV16_1X48:
  695. return true;
  696. default:
  697. return false;
  698. }
  699. }
  700. static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
  701. {
  702. switch (bus_format) {
  703. case MEDIA_BUS_FMT_UYVY8_1X16:
  704. case MEDIA_BUS_FMT_UYVY10_1X20:
  705. case MEDIA_BUS_FMT_UYVY12_1X24:
  706. return true;
  707. default:
  708. return false;
  709. }
  710. }
  711. static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
  712. {
  713. switch (bus_format) {
  714. case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
  715. case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
  716. case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
  717. case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
  718. return true;
  719. default:
  720. return false;
  721. }
  722. }
  723. static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
  724. {
  725. switch (bus_format) {
  726. case MEDIA_BUS_FMT_RGB888_1X24:
  727. case MEDIA_BUS_FMT_YUV8_1X24:
  728. case MEDIA_BUS_FMT_UYVY8_1X16:
  729. case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
  730. return 8;
  731. case MEDIA_BUS_FMT_RGB101010_1X30:
  732. case MEDIA_BUS_FMT_YUV10_1X30:
  733. case MEDIA_BUS_FMT_UYVY10_1X20:
  734. case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
  735. return 10;
  736. case MEDIA_BUS_FMT_RGB121212_1X36:
  737. case MEDIA_BUS_FMT_YUV12_1X36:
  738. case MEDIA_BUS_FMT_UYVY12_1X24:
  739. case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
  740. return 12;
  741. case MEDIA_BUS_FMT_RGB161616_1X48:
  742. case MEDIA_BUS_FMT_YUV16_1X48:
  743. case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
  744. return 16;
  745. default:
  746. return 0;
  747. }
  748. }
  749. /*
  750. * this submodule is responsible for the video data synchronization.
  751. * for example, for RGB 4:4:4 input, the data map is defined as
  752. * pin{47~40} <==> R[7:0]
  753. * pin{31~24} <==> G[7:0]
  754. * pin{15~8} <==> B[7:0]
  755. */
  756. static void hdmi_video_sample(struct dw_hdmi *hdmi)
  757. {
  758. int color_format = 0;
  759. u8 val;
  760. switch (hdmi->hdmi_data.enc_in_bus_format) {
  761. case MEDIA_BUS_FMT_RGB888_1X24:
  762. color_format = 0x01;
  763. break;
  764. case MEDIA_BUS_FMT_RGB101010_1X30:
  765. color_format = 0x03;
  766. break;
  767. case MEDIA_BUS_FMT_RGB121212_1X36:
  768. color_format = 0x05;
  769. break;
  770. case MEDIA_BUS_FMT_RGB161616_1X48:
  771. color_format = 0x07;
  772. break;
  773. case MEDIA_BUS_FMT_YUV8_1X24:
  774. case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
  775. color_format = 0x09;
  776. break;
  777. case MEDIA_BUS_FMT_YUV10_1X30:
  778. case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
  779. color_format = 0x0B;
  780. break;
  781. case MEDIA_BUS_FMT_YUV12_1X36:
  782. case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
  783. color_format = 0x0D;
  784. break;
  785. case MEDIA_BUS_FMT_YUV16_1X48:
  786. case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
  787. color_format = 0x0F;
  788. break;
  789. case MEDIA_BUS_FMT_UYVY8_1X16:
  790. color_format = 0x16;
  791. break;
  792. case MEDIA_BUS_FMT_UYVY10_1X20:
  793. color_format = 0x14;
  794. break;
  795. case MEDIA_BUS_FMT_UYVY12_1X24:
  796. color_format = 0x12;
  797. break;
  798. default:
  799. return;
  800. }
  801. val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
  802. ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
  803. HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
  804. hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
  805. /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
  806. val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
  807. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
  808. HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
  809. hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
  810. hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
  811. hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
  812. hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
  813. hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
  814. hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
  815. hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
  816. }
  817. #if 0
  818. static int is_color_space_conversion(struct dw_hdmi *hdmi)
  819. {
  820. struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
  821. bool is_input_rgb, is_output_rgb;
  822. is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
  823. is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
  824. return (is_input_rgb != is_output_rgb) ||
  825. (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
  826. }
  827. #endif
  828. static int is_color_space_decimation(struct dw_hdmi *hdmi)
  829. {
  830. if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
  831. return 0;
  832. if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
  833. hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
  834. return 1;
  835. return 0;
  836. }
  837. static int is_color_space_interpolation(struct dw_hdmi *hdmi)
  838. {
  839. if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
  840. return 0;
  841. if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
  842. hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
  843. return 1;
  844. return 0;
  845. }
  846. #if 0
  847. static bool is_csc_needed(struct dw_hdmi *hdmi)
  848. {
  849. return is_color_space_conversion(hdmi) ||
  850. is_color_space_decimation(hdmi) ||
  851. is_color_space_interpolation(hdmi);
  852. }
  853. #endif
  854. static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
  855. {
  856. const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
  857. bool is_input_rgb, is_output_rgb;
  858. unsigned i;
  859. u32 csc_scale = 1;
  860. is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
  861. is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
  862. if (!is_input_rgb && is_output_rgb) {
  863. if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
  864. csc_coeff = &csc_coeff_rgb_out_eitu601;
  865. else
  866. csc_coeff = &csc_coeff_rgb_out_eitu709;
  867. } else if (is_input_rgb && !is_output_rgb) {
  868. if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
  869. csc_coeff = &csc_coeff_rgb_in_eitu601;
  870. else
  871. csc_coeff = &csc_coeff_rgb_in_eitu709;
  872. csc_scale = 0;
  873. } else if (is_input_rgb && is_output_rgb &&
  874. hdmi->hdmi_data.rgb_limited_range) {
  875. csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
  876. }
  877. /* The CSC registers are sequential, alternating MSB then LSB */
  878. for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
  879. u16 coeff_a = (*csc_coeff)[0][i];
  880. u16 coeff_b = (*csc_coeff)[1][i];
  881. u16 coeff_c = (*csc_coeff)[2][i];
  882. hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
  883. hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
  884. hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
  885. hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
  886. hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
  887. hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
  888. }
  889. hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
  890. HDMI_CSC_SCALE);
  891. }
  892. static void hdmi_video_csc(struct dw_hdmi *hdmi)
  893. {
  894. int color_depth = 0;
  895. int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
  896. int decimation = 0;
  897. /* YCC422 interpolation to 444 mode */
  898. if (is_color_space_interpolation(hdmi))
  899. interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
  900. else if (is_color_space_decimation(hdmi))
  901. decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
  902. switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
  903. case 8:
  904. color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
  905. break;
  906. case 10:
  907. color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
  908. break;
  909. case 12:
  910. color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
  911. break;
  912. case 16:
  913. color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
  914. break;
  915. default:
  916. return;
  917. }
  918. /* Configure the CSC registers */
  919. hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
  920. hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
  921. HDMI_CSC_SCALE);
  922. dw_hdmi_update_csc_coeffs(hdmi);
  923. }
  924. /*
  925. * HDMI video packetizer is used to packetize the data.
  926. * for example, if input is YCC422 mode or repeater is used,
  927. * data should be repacked this module can be bypassed.
  928. */
  929. static void hdmi_video_packetize(struct dw_hdmi *hdmi)
  930. {
  931. unsigned int color_depth = 0;
  932. unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
  933. unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
  934. struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
  935. u8 val, vp_conf;
  936. if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
  937. hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
  938. hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
  939. switch (hdmi_bus_fmt_color_depth(
  940. hdmi->hdmi_data.enc_out_bus_format)) {
  941. case 8:
  942. color_depth = 4;
  943. output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
  944. break;
  945. case 10:
  946. color_depth = 5;
  947. break;
  948. case 12:
  949. color_depth = 6;
  950. break;
  951. case 16:
  952. color_depth = 7;
  953. break;
  954. default:
  955. output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
  956. }
  957. } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
  958. switch (hdmi_bus_fmt_color_depth(
  959. hdmi->hdmi_data.enc_out_bus_format)) {
  960. case 0:
  961. case 8:
  962. remap_size = HDMI_VP_REMAP_YCC422_16bit;
  963. break;
  964. case 10:
  965. remap_size = HDMI_VP_REMAP_YCC422_20bit;
  966. break;
  967. case 12:
  968. remap_size = HDMI_VP_REMAP_YCC422_24bit;
  969. break;
  970. default:
  971. return;
  972. }
  973. output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
  974. } else {
  975. return;
  976. }
  977. /* set the packetizer registers */
  978. val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
  979. HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
  980. ((hdmi_data->pix_repet_factor <<
  981. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
  982. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
  983. hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
  984. hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
  985. HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
  986. /* Data from pixel repeater block */
  987. if (hdmi_data->pix_repet_factor > 1) {
  988. vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
  989. HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
  990. } else { /* data from packetizer block */
  991. vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
  992. HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
  993. }
  994. hdmi_modb(hdmi, vp_conf,
  995. HDMI_VP_CONF_PR_EN_MASK |
  996. HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
  997. hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
  998. HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
  999. hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
  1000. if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
  1001. vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
  1002. HDMI_VP_CONF_PP_EN_ENABLE |
  1003. HDMI_VP_CONF_YCC422_EN_DISABLE;
  1004. } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
  1005. vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
  1006. HDMI_VP_CONF_PP_EN_DISABLE |
  1007. HDMI_VP_CONF_YCC422_EN_ENABLE;
  1008. } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
  1009. vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
  1010. HDMI_VP_CONF_PP_EN_DISABLE |
  1011. HDMI_VP_CONF_YCC422_EN_DISABLE;
  1012. } else {
  1013. return;
  1014. }
  1015. hdmi_modb(hdmi, vp_conf,
  1016. HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
  1017. HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
  1018. hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
  1019. HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
  1020. HDMI_VP_STUFF_PP_STUFFING_MASK |
  1021. HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
  1022. hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
  1023. HDMI_VP_CONF);
  1024. }
  1025. /* -----------------------------------------------------------------------------
  1026. * Synopsys PHY Handling
  1027. */
  1028. static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
  1029. unsigned char bit)
  1030. {
  1031. hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
  1032. HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
  1033. }
  1034. static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
  1035. {
  1036. u32 val;
  1037. while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
  1038. if (msec-- == 0)
  1039. return false;
  1040. udelay(1000);
  1041. }
  1042. hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
  1043. return true;
  1044. }
  1045. void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
  1046. unsigned char addr)
  1047. {
  1048. hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
  1049. hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
  1050. hdmi_writeb(hdmi, (unsigned char)(data >> 8),
  1051. HDMI_PHY_I2CM_DATAO_1_ADDR);
  1052. hdmi_writeb(hdmi, (unsigned char)(data >> 0),
  1053. HDMI_PHY_I2CM_DATAO_0_ADDR);
  1054. hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
  1055. HDMI_PHY_I2CM_OPERATION_ADDR);
  1056. hdmi_phy_wait_i2c_done(hdmi, 1000);
  1057. }
  1058. EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
  1059. /* Filter out invalid setups to avoid configuring SCDC and scrambling */
  1060. static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
  1061. const struct drm_display_info *display)
  1062. {
  1063. /* Completely disable SCDC support for older controllers */
  1064. if (hdmi->version < 0x200a)
  1065. return false;
  1066. /* Disable if no DDC bus */
  1067. if (!hdmi->ddc)
  1068. return false;
  1069. /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
  1070. if (!display->hdmi.scdc.supported ||
  1071. !display->hdmi.scdc.scrambling.supported)
  1072. return false;
  1073. /*
  1074. * Disable if display only support low TMDS rates and scrambling
  1075. * for low rates is not supported either
  1076. */
  1077. if (!display->hdmi.scdc.scrambling.low_rates &&
  1078. display->max_tmds_clock <= 340000)
  1079. return false;
  1080. return true;
  1081. }
  1082. /*
  1083. * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
  1084. * - The Source shall suspend transmission of the TMDS clock and data
  1085. * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
  1086. * from a 0 to a 1 or from a 1 to a 0
  1087. * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
  1088. * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
  1089. * transmission of TMDS clock and data
  1090. *
  1091. * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
  1092. * helper should called right before enabling the TMDS Clock and Data in
  1093. * the PHY configuration callback.
  1094. */
  1095. void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
  1096. const struct drm_display_info *display)
  1097. {
  1098. unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
  1099. /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
  1100. if (dw_hdmi_support_scdc(hdmi, display)) {
  1101. if (mtmdsclock > HDMI14_MAX_TMDSCLK)
  1102. drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
  1103. else
  1104. drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
  1105. }
  1106. }
  1107. EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
  1108. static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
  1109. {
  1110. hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
  1111. HDMI_PHY_CONF0_PDZ_OFFSET,
  1112. HDMI_PHY_CONF0_PDZ_MASK);
  1113. }
  1114. static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
  1115. {
  1116. hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
  1117. HDMI_PHY_CONF0_ENTMDS_OFFSET,
  1118. HDMI_PHY_CONF0_ENTMDS_MASK);
  1119. }
  1120. static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
  1121. {
  1122. hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
  1123. HDMI_PHY_CONF0_SVSRET_OFFSET,
  1124. HDMI_PHY_CONF0_SVSRET_MASK);
  1125. }
  1126. void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
  1127. {
  1128. hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
  1129. HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
  1130. HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
  1131. }
  1132. EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
  1133. void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
  1134. {
  1135. hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
  1136. HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
  1137. HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
  1138. }
  1139. EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
  1140. static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
  1141. {
  1142. hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
  1143. HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
  1144. HDMI_PHY_CONF0_SELDATAENPOL_MASK);
  1145. }
  1146. static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
  1147. {
  1148. hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
  1149. HDMI_PHY_CONF0_SELDIPIF_OFFSET,
  1150. HDMI_PHY_CONF0_SELDIPIF_MASK);
  1151. }
  1152. void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
  1153. {
  1154. /* PHY reset. The reset signal is active high on Gen2 PHYs. */
  1155. hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
  1156. hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
  1157. }
  1158. EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
  1159. void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
  1160. {
  1161. hdmi_phy_test_clear(hdmi, 1);
  1162. hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
  1163. hdmi_phy_test_clear(hdmi, 0);
  1164. }
  1165. EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
  1166. static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
  1167. {
  1168. const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
  1169. unsigned int i;
  1170. u16 val;
  1171. if (phy->gen == 1) {
  1172. dw_hdmi_phy_enable_tmds(hdmi, 0);
  1173. dw_hdmi_phy_enable_powerdown(hdmi, true);
  1174. return;
  1175. }
  1176. dw_hdmi_phy_gen2_txpwron(hdmi, 0);
  1177. /*
  1178. * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
  1179. * to low power mode.
  1180. */
  1181. for (i = 0; i < 5; ++i) {
  1182. val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
  1183. if (!(val & HDMI_PHY_TX_PHY_LOCK))
  1184. break;
  1185. usleep_range(1000, 2000);
  1186. }
  1187. if (val & HDMI_PHY_TX_PHY_LOCK)
  1188. dev_warn(hdmi->dev, "PHY failed to power down\n");
  1189. else
  1190. dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
  1191. dw_hdmi_phy_gen2_pddq(hdmi, 1);
  1192. }
  1193. static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
  1194. {
  1195. const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
  1196. unsigned int i;
  1197. u8 val;
  1198. if (phy->gen == 1) {
  1199. dw_hdmi_phy_enable_powerdown(hdmi, false);
  1200. /* Toggle TMDS enable. */
  1201. dw_hdmi_phy_enable_tmds(hdmi, 0);
  1202. dw_hdmi_phy_enable_tmds(hdmi, 1);
  1203. return 0;
  1204. }
  1205. dw_hdmi_phy_gen2_txpwron(hdmi, 1);
  1206. dw_hdmi_phy_gen2_pddq(hdmi, 0);
  1207. /* Wait for PHY PLL lock */
  1208. for (i = 0; i < 5; ++i) {
  1209. val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
  1210. if (val)
  1211. break;
  1212. usleep_range(1000, 2000);
  1213. }
  1214. if (!val) {
  1215. dev_err(hdmi->dev, "PHY PLL failed to lock\n");
  1216. return -ETIMEDOUT;
  1217. }
  1218. dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
  1219. return 0;
  1220. }
  1221. /*
  1222. * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
  1223. * information the DWC MHL PHY has the same register layout and is thus also
  1224. * supported by this function.
  1225. */
  1226. static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
  1227. const struct dw_hdmi_plat_data *pdata,
  1228. unsigned long mpixelclock)
  1229. {
  1230. const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
  1231. const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
  1232. const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
  1233. /* TOFIX Will need 420 specific PHY configuration tables */
  1234. /* PLL/MPLL Cfg - always match on final entry */
  1235. for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
  1236. if (mpixelclock <= mpll_config->mpixelclock)
  1237. break;
  1238. for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
  1239. if (mpixelclock <= curr_ctrl->mpixelclock)
  1240. break;
  1241. for (; phy_config->mpixelclock != ~0UL; phy_config++)
  1242. if (mpixelclock <= phy_config->mpixelclock)
  1243. break;
  1244. if (mpll_config->mpixelclock == ~0UL ||
  1245. curr_ctrl->mpixelclock == ~0UL ||
  1246. phy_config->mpixelclock == ~0UL)
  1247. return -EINVAL;
  1248. dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
  1249. HDMI_3D_TX_PHY_CPCE_CTRL);
  1250. dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
  1251. HDMI_3D_TX_PHY_GMPCTRL);
  1252. dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
  1253. HDMI_3D_TX_PHY_CURRCTRL);
  1254. dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
  1255. dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
  1256. HDMI_3D_TX_PHY_MSM_CTRL);
  1257. dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
  1258. dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
  1259. HDMI_3D_TX_PHY_CKSYMTXCTRL);
  1260. dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
  1261. HDMI_3D_TX_PHY_VLEVCTRL);
  1262. /* Override and disable clock termination. */
  1263. dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
  1264. HDMI_3D_TX_PHY_CKCALCTRL);
  1265. return 0;
  1266. }
  1267. static int hdmi_phy_configure(struct dw_hdmi *hdmi,
  1268. const struct drm_display_info *display)
  1269. {
  1270. const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
  1271. const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
  1272. unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
  1273. unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
  1274. int ret;
  1275. dw_hdmi_phy_power_off(hdmi);
  1276. dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
  1277. /* Leave low power consumption mode by asserting SVSRET. */
  1278. if (phy->has_svsret)
  1279. dw_hdmi_phy_enable_svsret(hdmi, 1);
  1280. dw_hdmi_phy_reset(hdmi);
  1281. hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
  1282. dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
  1283. /* Write to the PHY as configured by the platform */
  1284. if (pdata->configure_phy)
  1285. ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
  1286. else
  1287. ret = phy->configure(hdmi, pdata, mpixelclock);
  1288. if (ret) {
  1289. dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
  1290. mpixelclock);
  1291. return ret;
  1292. }
  1293. /* Wait for resuming transmission of TMDS clock and data */
  1294. if (mtmdsclock > HDMI14_MAX_TMDSCLK)
  1295. msleep(100);
  1296. return dw_hdmi_phy_power_on(hdmi);
  1297. }
  1298. static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
  1299. const struct drm_display_info *display,
  1300. const struct drm_display_mode *mode)
  1301. {
  1302. int i, ret;
  1303. /* HDMI Phy spec says to do the phy initialization sequence twice */
  1304. for (i = 0; i < 2; i++) {
  1305. dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
  1306. dw_hdmi_phy_sel_interface_control(hdmi, 0);
  1307. ret = hdmi_phy_configure(hdmi, display);
  1308. if (ret)
  1309. return ret;
  1310. }
  1311. return 0;
  1312. }
  1313. static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
  1314. {
  1315. dw_hdmi_phy_power_off(hdmi);
  1316. }
  1317. enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
  1318. void *data)
  1319. {
  1320. return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
  1321. connector_status_connected : connector_status_disconnected;
  1322. }
  1323. EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
  1324. void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
  1325. bool force, bool disabled, bool rxsense)
  1326. {
  1327. u8 old_mask = hdmi->phy_mask;
  1328. if (force || disabled || !rxsense)
  1329. hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
  1330. else
  1331. hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
  1332. if (old_mask != hdmi->phy_mask)
  1333. hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
  1334. }
  1335. EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
  1336. void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
  1337. {
  1338. /*
  1339. * Configure the PHY RX SENSE and HPD interrupts polarities and clear
  1340. * any pending interrupt.
  1341. */
  1342. hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
  1343. hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
  1344. HDMI_IH_PHY_STAT0);
  1345. /* Enable cable hot plug irq. */
  1346. hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
  1347. /* Clear and unmute interrupts. */
  1348. hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
  1349. HDMI_IH_PHY_STAT0);
  1350. hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
  1351. HDMI_IH_MUTE_PHY_STAT0);
  1352. }
  1353. EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
  1354. static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
  1355. .init = dw_hdmi_phy_init,
  1356. .disable = dw_hdmi_phy_disable,
  1357. .read_hpd = dw_hdmi_phy_read_hpd,
  1358. .update_hpd = dw_hdmi_phy_update_hpd,
  1359. .setup_hpd = dw_hdmi_phy_setup_hpd,
  1360. };
  1361. /* -----------------------------------------------------------------------------
  1362. * HDMI TX Setup
  1363. */
  1364. static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
  1365. {
  1366. u8 de;
  1367. if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
  1368. de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
  1369. else
  1370. de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
  1371. /* disable rx detect */
  1372. hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
  1373. HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
  1374. hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
  1375. hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
  1376. HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
  1377. }
  1378. static void hdmi_config_AVI(struct dw_hdmi *hdmi,
  1379. const struct drm_connector *connector,
  1380. const struct drm_display_mode *mode)
  1381. {
  1382. struct hdmi_avi_infoframe frame;
  1383. u8 val;
  1384. /* Initialise info frame from DRM mode */
  1385. drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
  1386. if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
  1387. drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
  1388. hdmi->hdmi_data.rgb_limited_range ?
  1389. HDMI_QUANTIZATION_RANGE_LIMITED :
  1390. HDMI_QUANTIZATION_RANGE_FULL);
  1391. } else {
  1392. frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
  1393. frame.ycc_quantization_range =
  1394. HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
  1395. }
  1396. if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
  1397. frame.colorspace = HDMI_COLORSPACE_YUV444;
  1398. else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
  1399. frame.colorspace = HDMI_COLORSPACE_YUV422;
  1400. else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
  1401. frame.colorspace = HDMI_COLORSPACE_YUV420;
  1402. else
  1403. frame.colorspace = HDMI_COLORSPACE_RGB;
  1404. /* Set up colorimetry */
  1405. if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
  1406. switch (hdmi->hdmi_data.enc_out_encoding) {
  1407. case V4L2_YCBCR_ENC_601:
  1408. if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
  1409. frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
  1410. else
  1411. frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
  1412. frame.extended_colorimetry =
  1413. HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
  1414. break;
  1415. case V4L2_YCBCR_ENC_709:
  1416. if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
  1417. frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
  1418. else
  1419. frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
  1420. frame.extended_colorimetry =
  1421. HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
  1422. break;
  1423. default: /* Carries no data */
  1424. frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
  1425. frame.extended_colorimetry =
  1426. HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
  1427. break;
  1428. }
  1429. } else {
  1430. frame.colorimetry = HDMI_COLORIMETRY_NONE;
  1431. frame.extended_colorimetry =
  1432. HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
  1433. }
  1434. /*
  1435. * The Designware IP uses a different byte format from standard
  1436. * AVI info frames, though generally the bits are in the correct
  1437. * bytes.
  1438. */
  1439. /*
  1440. * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
  1441. * scan info in bits 4,5 rather than 0,1 and active aspect present in
  1442. * bit 6 rather than 4.
  1443. */
  1444. val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
  1445. if (frame.active_aspect & 15)
  1446. val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
  1447. if (frame.top_bar || frame.bottom_bar)
  1448. val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
  1449. if (frame.left_bar || frame.right_bar)
  1450. val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
  1451. hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
  1452. /* AVI data byte 2 differences: none */
  1453. val = ((frame.colorimetry & 0x3) << 6) |
  1454. ((frame.picture_aspect & 0x3) << 4) |
  1455. (frame.active_aspect & 0xf);
  1456. hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
  1457. /* AVI data byte 3 differences: none */
  1458. val = ((frame.extended_colorimetry & 0x7) << 4) |
  1459. ((frame.quantization_range & 0x3) << 2) |
  1460. (frame.nups & 0x3);
  1461. if (frame.itc)
  1462. val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
  1463. hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
  1464. /* AVI data byte 4 differences: none */
  1465. val = frame.video_code & 0x7f;
  1466. hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
  1467. /* AVI Data Byte 5- set up input and output pixel repetition */
  1468. val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
  1469. HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
  1470. HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
  1471. ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
  1472. HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
  1473. HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
  1474. hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
  1475. /*
  1476. * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
  1477. * ycc range in bits 2,3 rather than 6,7
  1478. */
  1479. val = ((frame.ycc_quantization_range & 0x3) << 2) |
  1480. (frame.content_type & 0x3);
  1481. hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
  1482. /* AVI Data Bytes 6-13 */
  1483. hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
  1484. hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
  1485. hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
  1486. hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
  1487. hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
  1488. hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
  1489. hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
  1490. hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
  1491. }
  1492. static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
  1493. const struct drm_connector *connector,
  1494. const struct drm_display_mode *mode)
  1495. {
  1496. struct hdmi_vendor_infoframe frame;
  1497. u8 buffer[10];
  1498. ssize_t err;
  1499. err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector,
  1500. mode);
  1501. if (err < 0)
  1502. /*
  1503. * Going into that statement does not means vendor infoframe
  1504. * fails. It just informed us that vendor infoframe is not
  1505. * needed for the selected mode. Only 4k or stereoscopic 3D
  1506. * mode requires vendor infoframe. So just simply return.
  1507. */
  1508. return;
  1509. err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
  1510. if (err < 0) {
  1511. dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
  1512. err);
  1513. return;
  1514. }
  1515. hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
  1516. HDMI_FC_DATAUTO0_VSD_MASK);
  1517. /* Set the length of HDMI vendor specific InfoFrame payload */
  1518. hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
  1519. /* Set 24bit IEEE Registration Identifier */
  1520. hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
  1521. hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
  1522. hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
  1523. /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
  1524. hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
  1525. hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
  1526. if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
  1527. hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
  1528. /* Packet frame interpolation */
  1529. hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
  1530. /* Auto packets per frame and line spacing */
  1531. hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
  1532. /* Configures the Frame Composer On RDRB mode */
  1533. hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
  1534. HDMI_FC_DATAUTO0_VSD_MASK);
  1535. }
  1536. static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
  1537. const struct drm_connector *connector)
  1538. {
  1539. const struct drm_connector_state *conn_state = connector->state;
  1540. struct hdmi_drm_infoframe frame;
  1541. u8 buffer[30];
  1542. ssize_t err;
  1543. int i;
  1544. if (!hdmi->plat_data->use_drm_infoframe)
  1545. return;
  1546. hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
  1547. HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
  1548. err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
  1549. if (err < 0)
  1550. return;
  1551. err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
  1552. if (err < 0) {
  1553. dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
  1554. return;
  1555. }
  1556. hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
  1557. hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
  1558. for (i = 0; i < frame.length; i++)
  1559. hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
  1560. hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
  1561. hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
  1562. HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
  1563. }
  1564. static bool dw_hdmi_ddc_debounce(struct dw_hdmi *hdmi)
  1565. {
  1566. u8 config, val, orig;
  1567. int ret, count = 0, check = 0;
  1568. drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &orig);
  1569. do {
  1570. drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &config);
  1571. if (count & 0x1)
  1572. config |= SCDC_SCRAMBLING_ENABLE;
  1573. else
  1574. config &= ~SCDC_SCRAMBLING_ENABLE;
  1575. drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, config);
  1576. drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val);
  1577. if (val != config)
  1578. check = 0;
  1579. else
  1580. check++;
  1581. if (check >= HDMI_DDC_CHECK_NORMAL) {
  1582. ret = true;
  1583. goto out;
  1584. }
  1585. if (count++ >= HDMI_DDC_CHECK_MAX_RETRIES) {
  1586. dev_err(hdmi->dev, "exceed max retries:%d\n", HDMI_DDC_CHECK_MAX_RETRIES);
  1587. ret = false;
  1588. goto out;
  1589. }
  1590. usleep_range(10000, 15000);
  1591. } while (1);
  1592. out:
  1593. drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, orig);
  1594. return ret;
  1595. }
  1596. static void hdmi_av_composer(struct dw_hdmi *hdmi,
  1597. const struct drm_display_info *display,
  1598. const struct drm_display_mode *mode)
  1599. {
  1600. u8 inv_val, bytes;
  1601. const struct drm_hdmi_info *hdmi_info = &display->hdmi;
  1602. struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
  1603. int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
  1604. unsigned int vdisplay, hdisplay;
  1605. vmode->mpixelclock = mode->clock * 1000;
  1606. dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
  1607. vmode->mtmdsclock = vmode->mpixelclock;
  1608. if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
  1609. switch (hdmi_bus_fmt_color_depth(
  1610. hdmi->hdmi_data.enc_out_bus_format)) {
  1611. case 16:
  1612. vmode->mtmdsclock = vmode->mpixelclock * 2;
  1613. break;
  1614. case 12:
  1615. vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
  1616. break;
  1617. case 10:
  1618. vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
  1619. break;
  1620. }
  1621. }
  1622. if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
  1623. vmode->mtmdsclock /= 2;
  1624. dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
  1625. /* Set up HDMI_FC_INVIDCONF */
  1626. inv_val = (hdmi->hdmi_data.hdcp_enable ||
  1627. (dw_hdmi_support_scdc(hdmi, display) &&
  1628. (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
  1629. hdmi_info->scdc.scrambling.low_rates)) ?
  1630. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
  1631. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
  1632. inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
  1633. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
  1634. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
  1635. inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
  1636. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
  1637. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
  1638. inv_val |= (vmode->mdataenablepolarity ?
  1639. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
  1640. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
  1641. if (hdmi->vic == 39)
  1642. inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
  1643. else
  1644. inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
  1645. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
  1646. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
  1647. inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
  1648. HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
  1649. HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
  1650. inv_val |= hdmi->sink_is_hdmi ?
  1651. HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
  1652. HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
  1653. hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
  1654. hdisplay = mode->hdisplay;
  1655. hblank = mode->htotal - mode->hdisplay;
  1656. h_de_hs = mode->hsync_start - mode->hdisplay;
  1657. hsync_len = mode->hsync_end - mode->hsync_start;
  1658. /*
  1659. * When we're setting a YCbCr420 mode, we need
  1660. * to adjust the horizontal timing to suit.
  1661. */
  1662. if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
  1663. hdisplay /= 2;
  1664. hblank /= 2;
  1665. h_de_hs /= 2;
  1666. hsync_len /= 2;
  1667. }
  1668. vdisplay = mode->vdisplay;
  1669. vblank = mode->vtotal - mode->vdisplay;
  1670. v_de_vs = mode->vsync_start - mode->vdisplay;
  1671. vsync_len = mode->vsync_end - mode->vsync_start;
  1672. /*
  1673. * When we're setting an interlaced mode, we need
  1674. * to adjust the vertical timing to suit.
  1675. */
  1676. if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
  1677. vdisplay /= 2;
  1678. vblank /= 2;
  1679. v_de_vs /= 2;
  1680. vsync_len /= 2;
  1681. }
  1682. /* Scrambling Control */
  1683. if (dw_hdmi_support_scdc(hdmi, display)) {
  1684. if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
  1685. hdmi_info->scdc.scrambling.low_rates) {
  1686. /*
  1687. * HDMI2.0 Specifies the following procedure:
  1688. * After the Source Device has determined that
  1689. * SCDC_Present is set (=1), the Source Device should
  1690. * write the accurate Version of the Source Device
  1691. * to the Source Version field in the SCDCS.
  1692. * Source Devices compliant shall set the
  1693. * Source Version = 1.
  1694. */
  1695. dw_hdmi_ddc_debounce(hdmi);
  1696. drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
  1697. &bytes);
  1698. drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
  1699. min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
  1700. /* Enabled Scrambling in the Sink */
  1701. drm_scdc_set_scrambling(hdmi->ddc, 1);
  1702. /*
  1703. * To activate the scrambler feature, you must ensure
  1704. * that the quasi-static configuration bit
  1705. * fc_invidconf.HDCP_keepout is set at configuration
  1706. * time, before the required mc_swrstzreq.tmdsswrst_req
  1707. * reset request is issued.
  1708. */
  1709. hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
  1710. HDMI_MC_SWRSTZ);
  1711. hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
  1712. } else {
  1713. hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
  1714. hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
  1715. HDMI_MC_SWRSTZ);
  1716. drm_scdc_set_scrambling(hdmi->ddc, 0);
  1717. }
  1718. }
  1719. /* Set up horizontal active pixel width */
  1720. hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
  1721. hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
  1722. /* Set up vertical active lines */
  1723. hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
  1724. hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
  1725. /* Set up horizontal blanking pixel region width */
  1726. hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
  1727. hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
  1728. /* Set up vertical blanking pixel region width */
  1729. hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
  1730. /* Set up HSYNC active edge delay width (in pixel clks) */
  1731. hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
  1732. hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
  1733. /* Set up VSYNC active edge delay (in lines) */
  1734. hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
  1735. /* Set up HSYNC active pulse width (in pixel clks) */
  1736. hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
  1737. hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
  1738. /* Set up VSYNC active edge delay (in lines) */
  1739. hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
  1740. }
  1741. /* HDMI Initialization Step B.4 */
  1742. static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
  1743. {
  1744. /* control period minimum duration */
  1745. hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
  1746. hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
  1747. hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
  1748. /* Set to fill TMDS data channels */
  1749. hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
  1750. hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
  1751. hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
  1752. #if 0
  1753. /* Enable pixel clock and tmds data path */
  1754. hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
  1755. HDMI_MC_CLKDIS_CSCCLK_DISABLE |
  1756. HDMI_MC_CLKDIS_AUDCLK_DISABLE |
  1757. HDMI_MC_CLKDIS_PREPCLK_DISABLE |
  1758. HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
  1759. hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
  1760. hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
  1761. hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
  1762. hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
  1763. /* Enable csc path */
  1764. if (is_csc_needed(hdmi)) {
  1765. hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
  1766. hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
  1767. hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
  1768. HDMI_MC_FLOWCTRL);
  1769. } else {
  1770. hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
  1771. hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
  1772. hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
  1773. HDMI_MC_FLOWCTRL);
  1774. }
  1775. #endif
  1776. }
  1777. /* Workaround to clear the overflow condition */
  1778. static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
  1779. {
  1780. unsigned int count;
  1781. unsigned int i;
  1782. u8 val;
  1783. /*
  1784. * Under some circumstances the Frame Composer arithmetic unit can miss
  1785. * an FC register write due to being busy processing the previous one.
  1786. * The issue can be worked around by issuing a TMDS software reset and
  1787. * then write one of the FC registers several times.
  1788. *
  1789. * The number of iterations matters and depends on the HDMI TX revision
  1790. * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
  1791. * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
  1792. * as needing the workaround, with 4 iterations for v1.30a and 1
  1793. * iteration for others.
  1794. * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
  1795. * the workaround with a single iteration.
  1796. * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
  1797. * been identified as needing the workaround with a single iteration.
  1798. */
  1799. switch (hdmi->version) {
  1800. case 0x130a:
  1801. count = 4;
  1802. break;
  1803. case 0x131a:
  1804. case 0x132a:
  1805. case 0x200a:
  1806. case 0x201a:
  1807. case 0x211a:
  1808. case 0x212a:
  1809. count = 1;
  1810. break;
  1811. default:
  1812. return;
  1813. }
  1814. /* TMDS software reset */
  1815. hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
  1816. val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
  1817. for (i = 0; i < count; i++)
  1818. hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
  1819. }
  1820. static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
  1821. {
  1822. hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
  1823. HDMI_IH_MUTE_FC_STAT2);
  1824. }
  1825. static void hdmi_check_scrambling_status(struct dw_hdmi *hdmi,
  1826. const struct drm_display_info *display)
  1827. {
  1828. int count = 0;
  1829. if (!dw_hdmi_support_scdc(hdmi, display))
  1830. return;
  1831. do {
  1832. if (drm_scdc_get_scrambling_status(hdmi->ddc))
  1833. break;
  1834. /* polling scrambling_status up to a maximum of 200ms */
  1835. if (count++ >= HDMI_SCRAMBLING_RETRIES) {
  1836. dev_err(hdmi->dev,
  1837. "TMDS link of scrambling_status is not ready\n");
  1838. break;
  1839. }
  1840. usleep_range(10000, 11000);
  1841. } while (1);
  1842. }
  1843. static int dw_hdmi_setup(struct dw_hdmi *hdmi,
  1844. const struct drm_connector *connector,
  1845. const struct drm_display_mode *mode)
  1846. {
  1847. int ret;
  1848. hdmi_disable_overflow_interrupts(hdmi);
  1849. hdmi->vic = drm_match_cea_mode(mode);
  1850. if (!hdmi->vic) {
  1851. dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
  1852. } else {
  1853. dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
  1854. }
  1855. if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
  1856. (hdmi->vic == 21) || (hdmi->vic == 22) ||
  1857. (hdmi->vic == 2) || (hdmi->vic == 3) ||
  1858. (hdmi->vic == 17) || (hdmi->vic == 18))
  1859. hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
  1860. else
  1861. hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
  1862. hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
  1863. hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
  1864. if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)
  1865. hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  1866. /* TOFIX: Get input encoding from plat data or fallback to none */
  1867. if (hdmi->plat_data->input_bus_encoding)
  1868. hdmi->hdmi_data.enc_in_encoding =
  1869. hdmi->plat_data->input_bus_encoding;
  1870. else
  1871. hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
  1872. if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)
  1873. hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  1874. hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
  1875. drm_default_rgb_quant_range(mode) ==
  1876. HDMI_QUANTIZATION_RANGE_LIMITED;
  1877. hdmi->hdmi_data.pix_repet_factor = 0;
  1878. hdmi->hdmi_data.hdcp_enable = 0;
  1879. hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
  1880. /* HDMI Initialization Step B.1 */
  1881. hdmi_av_composer(hdmi, &connector->display_info, mode);
  1882. /* HDMI Initializateion Step B.2 */
  1883. ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
  1884. &connector->display_info,
  1885. &hdmi->previous_mode);
  1886. if (ret)
  1887. return ret;
  1888. hdmi->phy.enabled = true;
  1889. /* HDMI Initialization Step B.3 */
  1890. dw_hdmi_enable_video_path(hdmi);
  1891. if (hdmi->sink_has_audio) {
  1892. dev_dbg(hdmi->dev, "sink has audio support\n");
  1893. /* HDMI Initialization Step E - Configure audio */
  1894. hdmi_clk_regenerator_update_pixel_clock(hdmi);
  1895. hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
  1896. }
  1897. /* not for DVI mode */
  1898. if (hdmi->sink_is_hdmi) {
  1899. dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
  1900. /* HDMI Initialization Step F - Configure AVI InfoFrame */
  1901. hdmi_config_AVI(hdmi, connector, mode);
  1902. hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
  1903. hdmi_config_drm_infoframe(hdmi, connector);
  1904. } else {
  1905. dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
  1906. }
  1907. hdmi_video_packetize(hdmi);
  1908. hdmi_video_csc(hdmi);
  1909. hdmi_video_sample(hdmi);
  1910. hdmi_tx_hdcp_config(hdmi);
  1911. hdmi_check_scrambling_status(hdmi, &connector->display_info);
  1912. dw_hdmi_clear_overflow(hdmi);
  1913. return 0;
  1914. }
  1915. static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
  1916. {
  1917. u8 ih_mute;
  1918. /*
  1919. * Boot up defaults are:
  1920. * HDMI_IH_MUTE = 0x03 (disabled)
  1921. * HDMI_IH_MUTE_* = 0x00 (enabled)
  1922. *
  1923. * Disable top level interrupt bits in HDMI block
  1924. */
  1925. ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
  1926. HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
  1927. HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
  1928. hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
  1929. /* by default mask all interrupts */
  1930. hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
  1931. hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
  1932. hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
  1933. hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
  1934. hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
  1935. hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
  1936. hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
  1937. hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
  1938. hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
  1939. hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
  1940. hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
  1941. hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
  1942. hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
  1943. hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
  1944. /* Disable interrupts in the IH_MUTE_* registers */
  1945. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
  1946. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
  1947. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
  1948. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
  1949. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
  1950. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
  1951. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
  1952. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
  1953. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
  1954. hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
  1955. /* Enable top level interrupt bits in HDMI block */
  1956. ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
  1957. HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
  1958. hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
  1959. }
  1960. static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
  1961. {
  1962. hdmi->bridge_is_on = true;
  1963. /*
  1964. * The curr_conn field is guaranteed to be valid here, as this function
  1965. * is only be called when !hdmi->disabled.
  1966. */
  1967. dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
  1968. }
  1969. static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
  1970. {
  1971. if (hdmi->phy.enabled) {
  1972. hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
  1973. hdmi->phy.enabled = false;
  1974. }
  1975. hdmi->bridge_is_on = false;
  1976. }
  1977. static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
  1978. {
  1979. int force = hdmi->force;
  1980. if (hdmi->disabled) {
  1981. force = DRM_FORCE_OFF;
  1982. } else if (force == DRM_FORCE_UNSPECIFIED) {
  1983. if (hdmi->rxsense)
  1984. force = DRM_FORCE_ON;
  1985. else
  1986. force = DRM_FORCE_OFF;
  1987. }
  1988. if (force == DRM_FORCE_OFF) {
  1989. if (hdmi->bridge_is_on)
  1990. dw_hdmi_poweroff(hdmi);
  1991. } else {
  1992. if (!hdmi->bridge_is_on)
  1993. dw_hdmi_poweron(hdmi);
  1994. }
  1995. }
  1996. /*
  1997. * Adjust the detection of RXSENSE according to whether we have a forced
  1998. * connection mode enabled, or whether we have been disabled. There is
  1999. * no point processing RXSENSE interrupts if we have a forced connection
  2000. * state, or DRM has us disabled.
  2001. *
  2002. * We also disable rxsense interrupts when we think we're disconnected
  2003. * to avoid floating TDMS signals giving false rxsense interrupts.
  2004. *
  2005. * Note: we still need to listen for HPD interrupts even when DRM has us
  2006. * disabled so that we can detect a connect event.
  2007. */
  2008. static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
  2009. {
  2010. if (hdmi->phy.ops->update_hpd)
  2011. hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
  2012. hdmi->force, hdmi->disabled,
  2013. hdmi->rxsense);
  2014. }
  2015. static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
  2016. {
  2017. enum drm_connector_status result;
  2018. result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
  2019. mutex_lock(&hdmi->mutex);
  2020. if (result != hdmi->last_connector_result) {
  2021. dev_dbg(hdmi->dev, "read_hpd result: %d", result);
  2022. handle_plugged_change(hdmi,
  2023. result == connector_status_connected);
  2024. hdmi->last_connector_result = result;
  2025. }
  2026. mutex_unlock(&hdmi->mutex);
  2027. return result;
  2028. }
  2029. static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi,
  2030. struct drm_connector *connector)
  2031. {
  2032. struct edid *edid;
  2033. if (!hdmi->ddc)
  2034. return NULL;
  2035. edid = drm_get_edid(connector, hdmi->ddc);
  2036. if (!edid) {
  2037. dev_dbg(hdmi->dev, "failed to get edid\n");
  2038. return NULL;
  2039. }
  2040. dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
  2041. edid->width_cm, edid->height_cm);
  2042. hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
  2043. hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
  2044. return edid;
  2045. }
  2046. /* -----------------------------------------------------------------------------
  2047. * DRM Connector Operations
  2048. */
  2049. static enum drm_connector_status
  2050. dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
  2051. {
  2052. struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
  2053. connector);
  2054. return dw_hdmi_detect(hdmi);
  2055. }
  2056. static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
  2057. {
  2058. struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
  2059. connector);
  2060. struct edid *edid;
  2061. int ret;
  2062. edid = dw_hdmi_get_edid(hdmi, connector);
  2063. if (!edid)
  2064. return 0;
  2065. drm_connector_update_edid_property(connector, edid);
  2066. cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
  2067. ret = drm_add_edid_modes(connector, edid);
  2068. kfree(edid);
  2069. return ret;
  2070. }
  2071. static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
  2072. const struct drm_connector_state *new_state)
  2073. {
  2074. struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
  2075. struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
  2076. if (!old_blob || !new_blob)
  2077. return old_blob == new_blob;
  2078. if (old_blob->length != new_blob->length)
  2079. return false;
  2080. return !memcmp(old_blob->data, new_blob->data, old_blob->length);
  2081. }
  2082. static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
  2083. struct drm_atomic_state *state)
  2084. {
  2085. struct drm_connector_state *old_state =
  2086. drm_atomic_get_old_connector_state(state, connector);
  2087. struct drm_connector_state *new_state =
  2088. drm_atomic_get_new_connector_state(state, connector);
  2089. struct drm_crtc *crtc = new_state->crtc;
  2090. struct drm_crtc_state *crtc_state;
  2091. if (!crtc)
  2092. return 0;
  2093. if (!hdr_metadata_equal(old_state, new_state)) {
  2094. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  2095. if (IS_ERR(crtc_state))
  2096. return PTR_ERR(crtc_state);
  2097. crtc_state->mode_changed = true;
  2098. }
  2099. return 0;
  2100. }
  2101. static void dw_hdmi_connector_force(struct drm_connector *connector)
  2102. {
  2103. struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
  2104. connector);
  2105. mutex_lock(&hdmi->mutex);
  2106. hdmi->force = connector->force;
  2107. dw_hdmi_update_power(hdmi);
  2108. dw_hdmi_update_phy_mask(hdmi);
  2109. mutex_unlock(&hdmi->mutex);
  2110. }
  2111. static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
  2112. .fill_modes = drm_helper_probe_single_connector_modes,
  2113. .detect = dw_hdmi_connector_detect,
  2114. .destroy = drm_connector_cleanup,
  2115. .force = dw_hdmi_connector_force,
  2116. .reset = drm_atomic_helper_connector_reset,
  2117. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  2118. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  2119. };
  2120. static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
  2121. .get_modes = dw_hdmi_connector_get_modes,
  2122. .atomic_check = dw_hdmi_connector_atomic_check,
  2123. };
  2124. static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
  2125. {
  2126. struct drm_connector *connector = &hdmi->connector;
  2127. struct cec_connector_info conn_info;
  2128. struct cec_notifier *notifier;
  2129. if (hdmi->version >= 0x200a)
  2130. connector->ycbcr_420_allowed =
  2131. hdmi->plat_data->ycbcr_420_allowed;
  2132. else
  2133. connector->ycbcr_420_allowed = false;
  2134. connector->interlace_allowed = 1;
  2135. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2136. drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
  2137. drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
  2138. &dw_hdmi_connector_funcs,
  2139. DRM_MODE_CONNECTOR_HDMIA,
  2140. hdmi->ddc);
  2141. /*
  2142. * drm_connector_attach_max_bpc_property() requires the
  2143. * connector to have a state.
  2144. */
  2145. drm_atomic_helper_connector_reset(connector);
  2146. drm_connector_attach_max_bpc_property(connector, 8, 16);
  2147. if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
  2148. drm_object_attach_property(&connector->base,
  2149. connector->dev->mode_config.hdr_output_metadata_property, 0);
  2150. drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
  2151. cec_fill_conn_info_from_drm(&conn_info, connector);
  2152. notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
  2153. if (!notifier)
  2154. return -ENOMEM;
  2155. mutex_lock(&hdmi->cec_notifier_mutex);
  2156. hdmi->cec_notifier = notifier;
  2157. mutex_unlock(&hdmi->cec_notifier_mutex);
  2158. return 0;
  2159. }
  2160. /* -----------------------------------------------------------------------------
  2161. * DRM Bridge Operations
  2162. */
  2163. /*
  2164. * Possible output formats :
  2165. * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
  2166. * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
  2167. * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
  2168. * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
  2169. * - MEDIA_BUS_FMT_YUV16_1X48,
  2170. * - MEDIA_BUS_FMT_RGB161616_1X48,
  2171. * - MEDIA_BUS_FMT_UYVY12_1X24,
  2172. * - MEDIA_BUS_FMT_YUV12_1X36,
  2173. * - MEDIA_BUS_FMT_RGB121212_1X36,
  2174. * - MEDIA_BUS_FMT_UYVY10_1X20,
  2175. * - MEDIA_BUS_FMT_YUV10_1X30,
  2176. * - MEDIA_BUS_FMT_RGB101010_1X30,
  2177. * - MEDIA_BUS_FMT_UYVY8_1X16,
  2178. * - MEDIA_BUS_FMT_YUV8_1X24,
  2179. * - MEDIA_BUS_FMT_RGB888_1X24,
  2180. */
  2181. /* Can return a maximum of 11 possible output formats for a mode/connector */
  2182. #define MAX_OUTPUT_SEL_FORMATS 11
  2183. static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
  2184. struct drm_bridge_state *bridge_state,
  2185. struct drm_crtc_state *crtc_state,
  2186. struct drm_connector_state *conn_state,
  2187. unsigned int *num_output_fmts)
  2188. {
  2189. struct drm_connector *conn = conn_state->connector;
  2190. struct drm_display_info *info = &conn->display_info;
  2191. struct drm_display_mode *mode = &crtc_state->mode;
  2192. u8 max_bpc = conn_state->max_requested_bpc;
  2193. bool is_hdmi2_sink = info->hdmi.scdc.supported ||
  2194. (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
  2195. u32 *output_fmts;
  2196. unsigned int i = 0;
  2197. *num_output_fmts = 0;
  2198. output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
  2199. GFP_KERNEL);
  2200. if (!output_fmts)
  2201. return NULL;
  2202. /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
  2203. if (list_is_singular(&bridge->encoder->bridge_chain) ||
  2204. list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
  2205. *num_output_fmts = 1;
  2206. output_fmts[0] = MEDIA_BUS_FMT_FIXED;
  2207. return output_fmts;
  2208. }
  2209. /*
  2210. * If the current mode enforces 4:2:0, force the output but format
  2211. * to 4:2:0 and do not add the YUV422/444/RGB formats
  2212. */
  2213. if (conn->ycbcr_420_allowed &&
  2214. (drm_mode_is_420_only(info, mode) ||
  2215. (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
  2216. /* Order bus formats from 16bit to 8bit if supported */
  2217. if (max_bpc >= 16 && info->bpc == 16 &&
  2218. (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
  2219. output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
  2220. if (max_bpc >= 12 && info->bpc >= 12 &&
  2221. (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
  2222. output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
  2223. if (max_bpc >= 10 && info->bpc >= 10 &&
  2224. (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
  2225. output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
  2226. /* Default 8bit fallback */
  2227. output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
  2228. *num_output_fmts = i;
  2229. return output_fmts;
  2230. }
  2231. /*
  2232. * Order bus formats from 16bit to 8bit and from YUV422 to RGB
  2233. * if supported. In any case the default RGB888 format is added
  2234. */
  2235. if (max_bpc >= 16 && info->bpc == 16) {
  2236. if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
  2237. output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
  2238. output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
  2239. }
  2240. if (max_bpc >= 12 && info->bpc >= 12) {
  2241. if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
  2242. output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
  2243. if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
  2244. output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
  2245. output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
  2246. }
  2247. if (max_bpc >= 10 && info->bpc >= 10) {
  2248. if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
  2249. output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
  2250. if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
  2251. output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
  2252. output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
  2253. }
  2254. if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
  2255. output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
  2256. if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
  2257. output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
  2258. /* Default 8bit RGB fallback */
  2259. output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
  2260. *num_output_fmts = i;
  2261. return output_fmts;
  2262. }
  2263. /*
  2264. * Possible input formats :
  2265. * - MEDIA_BUS_FMT_RGB888_1X24
  2266. * - MEDIA_BUS_FMT_YUV8_1X24
  2267. * - MEDIA_BUS_FMT_UYVY8_1X16
  2268. * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
  2269. * - MEDIA_BUS_FMT_RGB101010_1X30
  2270. * - MEDIA_BUS_FMT_YUV10_1X30
  2271. * - MEDIA_BUS_FMT_UYVY10_1X20
  2272. * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
  2273. * - MEDIA_BUS_FMT_RGB121212_1X36
  2274. * - MEDIA_BUS_FMT_YUV12_1X36
  2275. * - MEDIA_BUS_FMT_UYVY12_1X24
  2276. * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
  2277. * - MEDIA_BUS_FMT_RGB161616_1X48
  2278. * - MEDIA_BUS_FMT_YUV16_1X48
  2279. * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
  2280. */
  2281. /* Can return a maximum of 3 possible input formats for an output format */
  2282. #define MAX_INPUT_SEL_FORMATS 3
  2283. static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
  2284. struct drm_bridge_state *bridge_state,
  2285. struct drm_crtc_state *crtc_state,
  2286. struct drm_connector_state *conn_state,
  2287. u32 output_fmt,
  2288. unsigned int *num_input_fmts)
  2289. {
  2290. u32 *input_fmts;
  2291. unsigned int i = 0;
  2292. *num_input_fmts = 0;
  2293. input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
  2294. GFP_KERNEL);
  2295. if (!input_fmts)
  2296. return NULL;
  2297. switch (output_fmt) {
  2298. /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
  2299. case MEDIA_BUS_FMT_FIXED:
  2300. input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
  2301. break;
  2302. /* 8bit */
  2303. case MEDIA_BUS_FMT_RGB888_1X24:
  2304. input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
  2305. input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
  2306. input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
  2307. break;
  2308. case MEDIA_BUS_FMT_YUV8_1X24:
  2309. input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
  2310. input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
  2311. input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
  2312. break;
  2313. case MEDIA_BUS_FMT_UYVY8_1X16:
  2314. input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
  2315. input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
  2316. input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
  2317. break;
  2318. /* 10bit */
  2319. case MEDIA_BUS_FMT_RGB101010_1X30:
  2320. input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
  2321. input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
  2322. input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
  2323. break;
  2324. case MEDIA_BUS_FMT_YUV10_1X30:
  2325. input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
  2326. input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
  2327. input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
  2328. break;
  2329. case MEDIA_BUS_FMT_UYVY10_1X20:
  2330. input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
  2331. input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
  2332. input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
  2333. break;
  2334. /* 12bit */
  2335. case MEDIA_BUS_FMT_RGB121212_1X36:
  2336. input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
  2337. input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
  2338. input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
  2339. break;
  2340. case MEDIA_BUS_FMT_YUV12_1X36:
  2341. input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
  2342. input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
  2343. input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
  2344. break;
  2345. case MEDIA_BUS_FMT_UYVY12_1X24:
  2346. input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
  2347. input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
  2348. input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
  2349. break;
  2350. /* 16bit */
  2351. case MEDIA_BUS_FMT_RGB161616_1X48:
  2352. input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
  2353. input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
  2354. break;
  2355. case MEDIA_BUS_FMT_YUV16_1X48:
  2356. input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
  2357. input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
  2358. break;
  2359. /*YUV 4:2:0 */
  2360. case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
  2361. case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
  2362. case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
  2363. case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
  2364. input_fmts[i++] = output_fmt;
  2365. break;
  2366. }
  2367. *num_input_fmts = i;
  2368. if (*num_input_fmts == 0) {
  2369. kfree(input_fmts);
  2370. input_fmts = NULL;
  2371. }
  2372. return input_fmts;
  2373. }
  2374. static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
  2375. struct drm_bridge_state *bridge_state,
  2376. struct drm_crtc_state *crtc_state,
  2377. struct drm_connector_state *conn_state)
  2378. {
  2379. struct dw_hdmi *hdmi = bridge->driver_private;
  2380. hdmi->hdmi_data.enc_out_bus_format =
  2381. bridge_state->output_bus_cfg.format;
  2382. hdmi->hdmi_data.enc_in_bus_format =
  2383. bridge_state->input_bus_cfg.format;
  2384. dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
  2385. bridge_state->input_bus_cfg.format,
  2386. bridge_state->output_bus_cfg.format);
  2387. return 0;
  2388. }
  2389. static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
  2390. enum drm_bridge_attach_flags flags)
  2391. {
  2392. struct dw_hdmi *hdmi = bridge->driver_private;
  2393. if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
  2394. return 0;
  2395. return dw_hdmi_connector_create(hdmi);
  2396. }
  2397. static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
  2398. {
  2399. struct dw_hdmi *hdmi = bridge->driver_private;
  2400. mutex_lock(&hdmi->cec_notifier_mutex);
  2401. cec_notifier_conn_unregister(hdmi->cec_notifier);
  2402. hdmi->cec_notifier = NULL;
  2403. mutex_unlock(&hdmi->cec_notifier_mutex);
  2404. }
  2405. static enum drm_mode_status
  2406. dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
  2407. const struct drm_display_info *info,
  2408. const struct drm_display_mode *mode)
  2409. {
  2410. struct dw_hdmi *hdmi = bridge->driver_private;
  2411. const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
  2412. enum drm_mode_status mode_status = MODE_OK;
  2413. /* We don't support double-clocked modes */
  2414. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  2415. return MODE_BAD;
  2416. if (pdata->mode_valid)
  2417. mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
  2418. mode);
  2419. return mode_status;
  2420. }
  2421. static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
  2422. const struct drm_display_mode *orig_mode,
  2423. const struct drm_display_mode *mode)
  2424. {
  2425. struct dw_hdmi *hdmi = bridge->driver_private;
  2426. mutex_lock(&hdmi->mutex);
  2427. /* Store the display mode for plugin/DKMS poweron events */
  2428. memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
  2429. mutex_unlock(&hdmi->mutex);
  2430. }
  2431. static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
  2432. struct drm_bridge_state *old_state)
  2433. {
  2434. struct dw_hdmi *hdmi = bridge->driver_private;
  2435. mutex_lock(&hdmi->mutex);
  2436. hdmi->disabled = true;
  2437. hdmi->curr_conn = NULL;
  2438. dw_hdmi_update_power(hdmi);
  2439. dw_hdmi_update_phy_mask(hdmi);
  2440. mutex_unlock(&hdmi->mutex);
  2441. pm_runtime_put(hdmi->dev);
  2442. }
  2443. static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
  2444. struct drm_bridge_state *old_state)
  2445. {
  2446. struct dw_hdmi *hdmi = bridge->driver_private;
  2447. struct drm_atomic_state *state = old_state->base.state;
  2448. struct drm_connector *connector;
  2449. connector = drm_atomic_get_new_connector_for_encoder(state,
  2450. bridge->encoder);
  2451. pm_runtime_get_sync(hdmi->dev);
  2452. mutex_lock(&hdmi->mutex);
  2453. hdmi->disabled = false;
  2454. hdmi->curr_conn = connector;
  2455. dw_hdmi_update_power(hdmi);
  2456. dw_hdmi_update_phy_mask(hdmi);
  2457. mutex_unlock(&hdmi->mutex);
  2458. }
  2459. static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)
  2460. {
  2461. struct dw_hdmi *hdmi = bridge->driver_private;
  2462. return dw_hdmi_detect(hdmi);
  2463. }
  2464. static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge,
  2465. struct drm_connector *connector)
  2466. {
  2467. struct dw_hdmi *hdmi = bridge->driver_private;
  2468. return dw_hdmi_get_edid(hdmi, connector);
  2469. }
  2470. static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
  2471. .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
  2472. .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
  2473. .atomic_reset = drm_atomic_helper_bridge_reset,
  2474. .attach = dw_hdmi_bridge_attach,
  2475. .detach = dw_hdmi_bridge_detach,
  2476. .atomic_check = dw_hdmi_bridge_atomic_check,
  2477. .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
  2478. .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
  2479. .atomic_enable = dw_hdmi_bridge_atomic_enable,
  2480. .atomic_disable = dw_hdmi_bridge_atomic_disable,
  2481. .mode_set = dw_hdmi_bridge_mode_set,
  2482. .mode_valid = dw_hdmi_bridge_mode_valid,
  2483. .detect = dw_hdmi_bridge_detect,
  2484. .get_edid = dw_hdmi_bridge_get_edid,
  2485. };
  2486. /* -----------------------------------------------------------------------------
  2487. * IRQ Handling
  2488. */
  2489. static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
  2490. {
  2491. struct dw_hdmi_i2c *i2c = hdmi->i2c;
  2492. unsigned int stat;
  2493. stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
  2494. if (!stat)
  2495. return IRQ_NONE;
  2496. hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
  2497. i2c->stat = stat;
  2498. complete(&i2c->cmp);
  2499. return IRQ_HANDLED;
  2500. }
  2501. static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
  2502. {
  2503. struct dw_hdmi *hdmi = dev_id;
  2504. u8 intr_stat;
  2505. irqreturn_t ret = IRQ_NONE;
  2506. if (hdmi->i2c)
  2507. ret = dw_hdmi_i2c_irq(hdmi);
  2508. intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
  2509. if (intr_stat) {
  2510. hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
  2511. hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
  2512. hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
  2513. return IRQ_WAKE_THREAD;
  2514. }
  2515. return ret;
  2516. }
  2517. void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
  2518. {
  2519. mutex_lock(&hdmi->mutex);
  2520. if (!hdmi->force) {
  2521. /*
  2522. * If the RX sense status indicates we're disconnected,
  2523. * clear the software rxsense status.
  2524. */
  2525. if (!rx_sense)
  2526. hdmi->rxsense = false;
  2527. /*
  2528. * Only set the software rxsense status when both
  2529. * rxsense and hpd indicates we're connected.
  2530. * This avoids what seems to be bad behaviour in
  2531. * at least iMX6S versions of the phy.
  2532. */
  2533. if (hpd)
  2534. hdmi->rxsense = true;
  2535. dw_hdmi_update_power(hdmi);
  2536. dw_hdmi_update_phy_mask(hdmi);
  2537. }
  2538. mutex_unlock(&hdmi->mutex);
  2539. }
  2540. EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
  2541. static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
  2542. {
  2543. struct dw_hdmi *hdmi = dev_id;
  2544. u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
  2545. msleep(50);
  2546. intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
  2547. phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
  2548. phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
  2549. phy_pol_mask = 0;
  2550. if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
  2551. phy_pol_mask |= HDMI_PHY_HPD;
  2552. if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
  2553. phy_pol_mask |= HDMI_PHY_RX_SENSE0;
  2554. if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
  2555. phy_pol_mask |= HDMI_PHY_RX_SENSE1;
  2556. if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
  2557. phy_pol_mask |= HDMI_PHY_RX_SENSE2;
  2558. if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
  2559. phy_pol_mask |= HDMI_PHY_RX_SENSE3;
  2560. if (phy_pol_mask)
  2561. hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
  2562. /*
  2563. * RX sense tells us whether the TDMS transmitters are detecting
  2564. * load - in other words, there's something listening on the
  2565. * other end of the link. Use this to decide whether we should
  2566. * power on the phy as HPD may be toggled by the sink to merely
  2567. * ask the source to re-read the EDID.
  2568. */
  2569. if (intr_stat &
  2570. (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
  2571. dw_hdmi_setup_rx_sense(hdmi,
  2572. phy_stat & HDMI_PHY_HPD,
  2573. phy_stat & HDMI_PHY_RX_SENSE);
  2574. if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
  2575. mutex_lock(&hdmi->cec_notifier_mutex);
  2576. cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
  2577. mutex_unlock(&hdmi->cec_notifier_mutex);
  2578. }
  2579. }
  2580. if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
  2581. enum drm_connector_status status = phy_int_pol & HDMI_PHY_HPD
  2582. ? connector_status_connected
  2583. : connector_status_disconnected;
  2584. dev_dbg(hdmi->dev, "EVENT=%s\n",
  2585. status == connector_status_connected ?
  2586. "plugin" : "plugout");
  2587. if (hdmi->bridge.dev) {
  2588. drm_helper_hpd_irq_event(hdmi->bridge.dev);
  2589. drm_bridge_hpd_notify(&hdmi->bridge, status);
  2590. }
  2591. }
  2592. hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
  2593. hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
  2594. HDMI_IH_MUTE_PHY_STAT0);
  2595. hdmi_writeb(hdmi, (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE), HDMI_PHY_MASK0);
  2596. return IRQ_HANDLED;
  2597. }
  2598. static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
  2599. {
  2600. .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
  2601. .name = "DWC HDMI TX PHY",
  2602. .gen = 1,
  2603. }, {
  2604. .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
  2605. .name = "DWC MHL PHY + HEAC PHY",
  2606. .gen = 2,
  2607. .has_svsret = true,
  2608. .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
  2609. }, {
  2610. .type = DW_HDMI_PHY_DWC_MHL_PHY,
  2611. .name = "DWC MHL PHY",
  2612. .gen = 2,
  2613. .has_svsret = true,
  2614. .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
  2615. }, {
  2616. .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
  2617. .name = "DWC HDMI 3D TX PHY + HEAC PHY",
  2618. .gen = 2,
  2619. .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
  2620. }, {
  2621. .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
  2622. .name = "DWC HDMI 3D TX PHY",
  2623. .gen = 2,
  2624. .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
  2625. }, {
  2626. .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
  2627. .name = "DWC HDMI 2.0 TX PHY",
  2628. .gen = 2,
  2629. .has_svsret = true,
  2630. .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
  2631. }, {
  2632. .type = DW_HDMI_PHY_VENDOR_PHY,
  2633. .name = "Vendor PHY",
  2634. }
  2635. };
  2636. static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
  2637. {
  2638. unsigned int i;
  2639. u8 phy_type;
  2640. phy_type = hdmi->plat_data->phy_force_vendor ?
  2641. DW_HDMI_PHY_VENDOR_PHY :
  2642. hdmi_readb(hdmi, HDMI_CONFIG2_ID);
  2643. if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
  2644. /* Vendor PHYs require support from the glue layer. */
  2645. if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
  2646. dev_err(hdmi->dev,
  2647. "Vendor HDMI PHY not supported by glue layer\n");
  2648. return -ENODEV;
  2649. }
  2650. hdmi->phy.ops = hdmi->plat_data->phy_ops;
  2651. hdmi->phy.data = hdmi->plat_data->phy_data;
  2652. hdmi->phy.name = hdmi->plat_data->phy_name;
  2653. return 0;
  2654. }
  2655. /* Synopsys PHYs are handled internally. */
  2656. for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
  2657. if (dw_hdmi_phys[i].type == phy_type) {
  2658. hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
  2659. hdmi->phy.name = dw_hdmi_phys[i].name;
  2660. hdmi->phy.data = (void *)&dw_hdmi_phys[i];
  2661. if (!dw_hdmi_phys[i].configure &&
  2662. !hdmi->plat_data->configure_phy) {
  2663. dev_err(hdmi->dev, "%s requires platform support\n",
  2664. hdmi->phy.name);
  2665. return -ENODEV;
  2666. }
  2667. return 0;
  2668. }
  2669. }
  2670. dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
  2671. return -ENODEV;
  2672. }
  2673. static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
  2674. {
  2675. mutex_lock(&hdmi->mutex);
  2676. hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
  2677. hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
  2678. mutex_unlock(&hdmi->mutex);
  2679. }
  2680. static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
  2681. {
  2682. mutex_lock(&hdmi->mutex);
  2683. hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
  2684. hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
  2685. mutex_unlock(&hdmi->mutex);
  2686. }
  2687. static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
  2688. .write = hdmi_writeb,
  2689. .read = hdmi_readb,
  2690. .enable = dw_hdmi_cec_enable,
  2691. .disable = dw_hdmi_cec_disable,
  2692. };
  2693. static const struct regmap_config hdmi_regmap_8bit_config = {
  2694. .reg_bits = 32,
  2695. .val_bits = 8,
  2696. .reg_stride = 1,
  2697. .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
  2698. };
  2699. static const struct regmap_config hdmi_regmap_32bit_config = {
  2700. .reg_bits = 32,
  2701. .val_bits = 32,
  2702. .reg_stride = 4,
  2703. .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
  2704. };
  2705. static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
  2706. {
  2707. initialize_hdmi_ih_mutes(hdmi);
  2708. /*
  2709. * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
  2710. * Even if we are using a separate i2c adapter doing this doesn't
  2711. * hurt.
  2712. */
  2713. dw_hdmi_i2c_init(hdmi);
  2714. if (hdmi->phy.ops->setup_hpd)
  2715. hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
  2716. }
  2717. /* -----------------------------------------------------------------------------
  2718. * Probe/remove API, used from platforms based on the DRM bridge API.
  2719. */
  2720. struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
  2721. const struct dw_hdmi_plat_data *plat_data)
  2722. {
  2723. struct device *dev = &pdev->dev;
  2724. struct device_node *np = dev->of_node;
  2725. struct platform_device_info pdevinfo;
  2726. struct device_node *ddc_node;
  2727. struct dw_hdmi_cec_data cec;
  2728. struct dw_hdmi *hdmi;
  2729. struct resource *iores = NULL;
  2730. int irq;
  2731. int ret;
  2732. u32 val = 1;
  2733. u8 prod_id0;
  2734. u8 prod_id1;
  2735. u8 config0;
  2736. u8 config3;
  2737. hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
  2738. if (!hdmi)
  2739. return ERR_PTR(-ENOMEM);
  2740. hdmi->plat_data = plat_data;
  2741. hdmi->dev = dev;
  2742. hdmi->sample_rate = 48000;
  2743. hdmi->disabled = true;
  2744. hdmi->rxsense = true;
  2745. hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
  2746. hdmi->mc_clkdis = 0x0;
  2747. hdmi->last_connector_result = connector_status_disconnected;
  2748. mutex_init(&hdmi->mutex);
  2749. mutex_init(&hdmi->audio_mutex);
  2750. mutex_init(&hdmi->cec_notifier_mutex);
  2751. spin_lock_init(&hdmi->audio_lock);
  2752. ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
  2753. if (ddc_node) {
  2754. hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
  2755. of_node_put(ddc_node);
  2756. if (!hdmi->ddc) {
  2757. dev_dbg(hdmi->dev, "failed to read ddc node\n");
  2758. return ERR_PTR(-EPROBE_DEFER);
  2759. }
  2760. } else {
  2761. dev_dbg(hdmi->dev, "no ddc property found\n");
  2762. }
  2763. if (!plat_data->regm) {
  2764. const struct regmap_config *reg_config;
  2765. of_property_read_u32(np, "reg-io-width", &val);
  2766. switch (val) {
  2767. case 4:
  2768. reg_config = &hdmi_regmap_32bit_config;
  2769. hdmi->reg_shift = 2;
  2770. break;
  2771. case 1:
  2772. reg_config = &hdmi_regmap_8bit_config;
  2773. break;
  2774. default:
  2775. dev_err(dev, "reg-io-width must be 1 or 4\n");
  2776. return ERR_PTR(-EINVAL);
  2777. }
  2778. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2779. hdmi->regs = devm_ioremap_resource(dev, iores);
  2780. if (IS_ERR(hdmi->regs)) {
  2781. ret = PTR_ERR(hdmi->regs);
  2782. goto err_res;
  2783. }
  2784. hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
  2785. if (IS_ERR(hdmi->regm)) {
  2786. dev_err(dev, "Failed to configure regmap\n");
  2787. ret = PTR_ERR(hdmi->regm);
  2788. goto err_res;
  2789. }
  2790. } else {
  2791. hdmi->regm = plat_data->regm;
  2792. }
  2793. hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
  2794. if (IS_ERR(hdmi->isfr_clk)) {
  2795. ret = PTR_ERR(hdmi->isfr_clk);
  2796. dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
  2797. goto err_res;
  2798. }
  2799. hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
  2800. if (IS_ERR(hdmi->iahb_clk)) {
  2801. ret = PTR_ERR(hdmi->iahb_clk);
  2802. dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
  2803. goto err_res;
  2804. }
  2805. hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
  2806. if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
  2807. hdmi->cec_clk = NULL;
  2808. } else if (IS_ERR(hdmi->cec_clk)) {
  2809. ret = PTR_ERR(hdmi->cec_clk);
  2810. if (ret != -EPROBE_DEFER)
  2811. dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
  2812. ret);
  2813. hdmi->cec_clk = NULL;
  2814. goto err_res;
  2815. }
  2816. hdmi->pix_clk = devm_clk_get(hdmi->dev, "pixclk");
  2817. if (IS_ERR(hdmi->pix_clk)) {
  2818. ret = PTR_ERR(hdmi->pix_clk);
  2819. dev_err(hdmi->dev, "Unable to get HDMI pix clk: %d\n", ret);
  2820. goto err_res;
  2821. }
  2822. hdmi->i2s_clk = devm_clk_get_optional(hdmi->dev, "i2s");
  2823. if (IS_ERR(hdmi->i2s_clk)) {
  2824. ret = PTR_ERR(hdmi->i2s_clk);
  2825. dev_err(hdmi->dev, "Unable to get HDMI i2s clk: %d\n", ret);
  2826. goto err_res;
  2827. }
  2828. clk_prepare_enable(hdmi->iahb_clk);
  2829. clk_prepare_enable(hdmi->isfr_clk);
  2830. /* Product and revision IDs */
  2831. hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
  2832. | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
  2833. prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
  2834. prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
  2835. if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
  2836. (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
  2837. dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
  2838. hdmi->version, prod_id0, prod_id1);
  2839. ret = -ENODEV;
  2840. goto err_res;
  2841. }
  2842. ret = dw_hdmi_detect_phy(hdmi);
  2843. if (ret < 0)
  2844. goto err_res;
  2845. dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
  2846. hdmi->version >> 12, hdmi->version & 0xfff,
  2847. prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
  2848. hdmi->phy.name);
  2849. dw_hdmi_init_hw(hdmi);
  2850. irq = platform_get_irq(pdev, 0);
  2851. if (irq < 0) {
  2852. ret = irq;
  2853. goto err_res;
  2854. }
  2855. ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
  2856. dw_hdmi_irq, IRQF_SHARED,
  2857. dev_name(dev), hdmi);
  2858. if (ret)
  2859. goto err_res;
  2860. /*
  2861. * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
  2862. * N and cts values before enabling phy
  2863. */
  2864. hdmi_init_clk_regenerator(hdmi);
  2865. /* If DDC bus is not specified, try to register HDMI I2C bus */
  2866. if (!hdmi->ddc) {
  2867. /* Look for (optional) stuff related to unwedging */
  2868. hdmi->pinctrl = devm_pinctrl_get(dev);
  2869. if (!IS_ERR(hdmi->pinctrl)) {
  2870. hdmi->unwedge_state =
  2871. pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
  2872. hdmi->default_state =
  2873. pinctrl_lookup_state(hdmi->pinctrl, "default");
  2874. if (IS_ERR(hdmi->default_state) ||
  2875. IS_ERR(hdmi->unwedge_state)) {
  2876. if (!IS_ERR(hdmi->unwedge_state))
  2877. dev_warn(dev,
  2878. "Unwedge requires default pinctrl\n");
  2879. hdmi->default_state = NULL;
  2880. hdmi->unwedge_state = NULL;
  2881. }
  2882. }
  2883. hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
  2884. if (IS_ERR(hdmi->ddc))
  2885. hdmi->ddc = NULL;
  2886. }
  2887. hdmi->bridge.driver_private = hdmi;
  2888. hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
  2889. hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
  2890. | DRM_BRIDGE_OP_HPD;
  2891. #ifdef CONFIG_OF
  2892. hdmi->bridge.of_node = pdev->dev.of_node;
  2893. #endif
  2894. memset(&pdevinfo, 0, sizeof(pdevinfo));
  2895. pdevinfo.parent = dev;
  2896. pdevinfo.id = PLATFORM_DEVID_AUTO;
  2897. config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
  2898. config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
  2899. if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
  2900. struct dw_hdmi_audio_data audio;
  2901. audio.phys = iores->start;
  2902. audio.base = hdmi->regs;
  2903. audio.irq = irq;
  2904. audio.hdmi = hdmi;
  2905. audio.get_eld = hdmi_audio_get_eld;
  2906. hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
  2907. hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
  2908. pdevinfo.name = "dw-hdmi-ahb-audio";
  2909. pdevinfo.data = &audio;
  2910. pdevinfo.size_data = sizeof(audio);
  2911. pdevinfo.dma_mask = DMA_BIT_MASK(32);
  2912. hdmi->audio = platform_device_register_full(&pdevinfo);
  2913. } else if (config0 & HDMI_CONFIG0_I2S) {
  2914. struct dw_hdmi_i2s_audio_data audio;
  2915. audio.hdmi = hdmi;
  2916. audio.get_eld = hdmi_audio_get_eld;
  2917. audio.write = hdmi_writeb;
  2918. audio.read = hdmi_readb;
  2919. hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
  2920. hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
  2921. pdevinfo.name = "dw-hdmi-i2s-audio";
  2922. pdevinfo.data = &audio;
  2923. pdevinfo.size_data = sizeof(audio);
  2924. pdevinfo.dma_mask = DMA_BIT_MASK(32);
  2925. hdmi->audio = platform_device_register_full(&pdevinfo);
  2926. }
  2927. if (config0 & HDMI_CONFIG0_CEC) {
  2928. cec.hdmi = hdmi;
  2929. cec.ops = &dw_hdmi_cec_ops;
  2930. cec.irq = irq;
  2931. pdevinfo.name = "dw-hdmi-cec";
  2932. pdevinfo.data = &cec;
  2933. pdevinfo.size_data = sizeof(cec);
  2934. pdevinfo.dma_mask = 0;
  2935. hdmi->cec = platform_device_register_full(&pdevinfo);
  2936. }
  2937. drm_bridge_add(&hdmi->bridge);
  2938. return hdmi;
  2939. err_res:
  2940. i2c_put_adapter(hdmi->ddc);
  2941. return ERR_PTR(ret);
  2942. }
  2943. EXPORT_SYMBOL_GPL(dw_hdmi_probe);
  2944. void dw_hdmi_remove(struct dw_hdmi *hdmi)
  2945. {
  2946. drm_bridge_remove(&hdmi->bridge);
  2947. if (hdmi->audio && !IS_ERR(hdmi->audio))
  2948. platform_device_unregister(hdmi->audio);
  2949. if (!IS_ERR(hdmi->cec))
  2950. platform_device_unregister(hdmi->cec);
  2951. /* Disable all interrupts */
  2952. hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
  2953. clk_disable_unprepare(hdmi->iahb_clk);
  2954. clk_disable_unprepare(hdmi->isfr_clk);
  2955. if (hdmi->i2c)
  2956. i2c_del_adapter(&hdmi->i2c->adap);
  2957. else
  2958. i2c_put_adapter(hdmi->ddc);
  2959. }
  2960. EXPORT_SYMBOL_GPL(dw_hdmi_remove);
  2961. /* -----------------------------------------------------------------------------
  2962. * Bind/unbind API, used from platforms based on the component framework.
  2963. */
  2964. struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
  2965. struct drm_encoder *encoder,
  2966. const struct dw_hdmi_plat_data *plat_data)
  2967. {
  2968. struct dw_hdmi *hdmi;
  2969. int ret;
  2970. hdmi = dw_hdmi_probe(pdev, plat_data);
  2971. if (IS_ERR(hdmi))
  2972. return hdmi;
  2973. ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
  2974. if (ret) {
  2975. dw_hdmi_remove(hdmi);
  2976. DRM_ERROR("Failed to initialize bridge with drm\n");
  2977. return ERR_PTR(ret);
  2978. }
  2979. return hdmi;
  2980. }
  2981. EXPORT_SYMBOL_GPL(dw_hdmi_bind);
  2982. void dw_hdmi_unbind(struct dw_hdmi *hdmi)
  2983. {
  2984. dw_hdmi_remove(hdmi);
  2985. }
  2986. EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
  2987. void dw_hdmi_resume(struct dw_hdmi *hdmi)
  2988. {
  2989. dw_hdmi_init_hw(hdmi);
  2990. }
  2991. EXPORT_SYMBOL_GPL(dw_hdmi_resume);
  2992. #ifdef CONFIG_PM
  2993. int dw_hdmi_runtime_suspend(struct dw_hdmi *hdmi)
  2994. {
  2995. clk_disable_unprepare(hdmi->i2s_clk);
  2996. clk_disable_unprepare(hdmi->pix_clk);
  2997. clk_disable_unprepare(hdmi->cec_clk);
  2998. return 0;
  2999. }
  3000. EXPORT_SYMBOL_GPL(dw_hdmi_runtime_suspend);
  3001. int dw_hdmi_runtime_resume(struct dw_hdmi *hdmi)
  3002. {
  3003. clk_prepare_enable(hdmi->cec_clk);
  3004. clk_prepare_enable(hdmi->pix_clk);
  3005. clk_prepare_enable(hdmi->i2s_clk);
  3006. return 0;
  3007. }
  3008. EXPORT_SYMBOL_GPL(dw_hdmi_runtime_resume);
  3009. #endif
  3010. MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
  3011. MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
  3012. MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
  3013. MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
  3014. MODULE_DESCRIPTION("DW HDMI transmitter driver");
  3015. MODULE_LICENSE("GPL");
  3016. MODULE_ALIAS("platform:dw-hdmi");