dw-hdmi-ahb-audio.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * DesignWare HDMI audio driver
  4. *
  5. * Written and tested against the Designware HDMI Tx found in iMX6.
  6. */
  7. #include <linux/io.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <drm/bridge/dw_hdmi.h>
  12. #include <drm/drm_edid.h>
  13. #include <sound/asoundef.h>
  14. #include <sound/core.h>
  15. #include <sound/initval.h>
  16. #include <sound/pcm.h>
  17. #include <sound/pcm_drm_eld.h>
  18. #include <sound/pcm_iec958.h>
  19. #include "dw-hdmi-audio.h"
  20. #define DRIVER_NAME "dw-hdmi-ahb-audio"
  21. /* Provide some bits rather than bit offsets */
  22. enum {
  23. HDMI_AHB_DMA_CONF0_SW_FIFO_RST = BIT(7),
  24. HDMI_AHB_DMA_CONF0_EN_HLOCK = BIT(3),
  25. HDMI_AHB_DMA_START_START = BIT(0),
  26. HDMI_AHB_DMA_STOP_STOP = BIT(0),
  27. HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = BIT(5),
  28. HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = BIT(4),
  29. HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = BIT(3),
  30. HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = BIT(2),
  31. HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = BIT(1),
  32. HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0),
  33. HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL =
  34. HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR |
  35. HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST |
  36. HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY |
  37. HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE |
  38. HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL |
  39. HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY,
  40. HDMI_IH_AHBDMAAUD_STAT0_ERROR = BIT(5),
  41. HDMI_IH_AHBDMAAUD_STAT0_LOST = BIT(4),
  42. HDMI_IH_AHBDMAAUD_STAT0_RETRY = BIT(3),
  43. HDMI_IH_AHBDMAAUD_STAT0_DONE = BIT(2),
  44. HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = BIT(1),
  45. HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0),
  46. HDMI_IH_AHBDMAAUD_STAT0_ALL =
  47. HDMI_IH_AHBDMAAUD_STAT0_ERROR |
  48. HDMI_IH_AHBDMAAUD_STAT0_LOST |
  49. HDMI_IH_AHBDMAAUD_STAT0_RETRY |
  50. HDMI_IH_AHBDMAAUD_STAT0_DONE |
  51. HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL |
  52. HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY,
  53. HDMI_AHB_DMA_CONF0_INCR16 = 2 << 1,
  54. HDMI_AHB_DMA_CONF0_INCR8 = 1 << 1,
  55. HDMI_AHB_DMA_CONF0_INCR4 = 0,
  56. HDMI_AHB_DMA_CONF0_BURST_MODE = BIT(0),
  57. HDMI_AHB_DMA_MASK_DONE = BIT(7),
  58. HDMI_REVISION_ID = 0x0001,
  59. HDMI_IH_AHBDMAAUD_STAT0 = 0x0109,
  60. HDMI_IH_MUTE_AHBDMAAUD_STAT0 = 0x0189,
  61. HDMI_AHB_DMA_CONF0 = 0x3600,
  62. HDMI_AHB_DMA_START = 0x3601,
  63. HDMI_AHB_DMA_STOP = 0x3602,
  64. HDMI_AHB_DMA_THRSLD = 0x3603,
  65. HDMI_AHB_DMA_STRADDR0 = 0x3604,
  66. HDMI_AHB_DMA_STPADDR0 = 0x3608,
  67. HDMI_AHB_DMA_MASK = 0x3614,
  68. HDMI_AHB_DMA_POL = 0x3615,
  69. HDMI_AHB_DMA_CONF1 = 0x3616,
  70. HDMI_AHB_DMA_BUFFPOL = 0x361a,
  71. };
  72. struct dw_hdmi_channel_conf {
  73. u8 conf1;
  74. u8 ca;
  75. };
  76. /*
  77. * The default mapping of ALSA channels to HDMI channels and speaker
  78. * allocation bits. Note that we can't do channel remapping here -
  79. * channels must be in the same order.
  80. *
  81. * Mappings for alsa-lib pcm/surround*.conf files:
  82. *
  83. * Front Sur4.0 Sur4.1 Sur5.0 Sur5.1 Sur7.1
  84. * Channels 2 4 6 6 6 8
  85. *
  86. * Our mapping from ALSA channel to CEA686D speaker name and HDMI channel:
  87. *
  88. * Number of ALSA channels
  89. * ALSA Channel 2 3 4 5 6 7 8
  90. * 0 FL:0 = = = = = =
  91. * 1 FR:1 = = = = = =
  92. * 2 FC:3 RL:4 LFE:2 = = =
  93. * 3 RR:5 RL:4 FC:3 = =
  94. * 4 RR:5 RL:4 = =
  95. * 5 RR:5 = =
  96. * 6 RC:6 =
  97. * 7 RLC/FRC RLC/FRC
  98. */
  99. static struct dw_hdmi_channel_conf default_hdmi_channel_config[7] = {
  100. { 0x03, 0x00 }, /* FL,FR */
  101. { 0x0b, 0x02 }, /* FL,FR,FC */
  102. { 0x33, 0x08 }, /* FL,FR,RL,RR */
  103. { 0x37, 0x09 }, /* FL,FR,LFE,RL,RR */
  104. { 0x3f, 0x0b }, /* FL,FR,LFE,FC,RL,RR */
  105. { 0x7f, 0x0f }, /* FL,FR,LFE,FC,RL,RR,RC */
  106. { 0xff, 0x13 }, /* FL,FR,LFE,FC,RL,RR,[FR]RC,[FR]LC */
  107. };
  108. struct snd_dw_hdmi {
  109. struct snd_card *card;
  110. struct snd_pcm *pcm;
  111. spinlock_t lock;
  112. struct dw_hdmi_audio_data data;
  113. struct snd_pcm_substream *substream;
  114. void (*reformat)(struct snd_dw_hdmi *, size_t, size_t);
  115. void *buf_src;
  116. void *buf_dst;
  117. dma_addr_t buf_addr;
  118. unsigned buf_offset;
  119. unsigned buf_period;
  120. unsigned buf_size;
  121. unsigned channels;
  122. u8 revision;
  123. u8 iec_offset;
  124. u8 cs[192][8];
  125. };
  126. static void dw_hdmi_writel(u32 val, void __iomem *ptr)
  127. {
  128. writeb_relaxed(val, ptr);
  129. writeb_relaxed(val >> 8, ptr + 1);
  130. writeb_relaxed(val >> 16, ptr + 2);
  131. writeb_relaxed(val >> 24, ptr + 3);
  132. }
  133. /*
  134. * Convert to hardware format: The userspace buffer contains IEC958 samples,
  135. * with the PCUV bits in bits 31..28 and audio samples in bits 27..4. We
  136. * need these to be in bits 27..24, with the IEC B bit in bit 28, and audio
  137. * samples in 23..0.
  138. *
  139. * Default preamble in bits 3..0: 8 = block start, 4 = even 2 = odd
  140. *
  141. * Ideally, we could do with having the data properly formatted in userspace.
  142. */
  143. static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw,
  144. size_t offset, size_t bytes)
  145. {
  146. u32 *src = dw->buf_src + offset;
  147. u32 *dst = dw->buf_dst + offset;
  148. u32 *end = dw->buf_src + offset + bytes;
  149. do {
  150. u32 b, sample = *src++;
  151. b = (sample & 8) << (28 - 3);
  152. sample >>= 4;
  153. *dst++ = sample | b;
  154. } while (src < end);
  155. }
  156. static u32 parity(u32 sample)
  157. {
  158. sample ^= sample >> 16;
  159. sample ^= sample >> 8;
  160. sample ^= sample >> 4;
  161. sample ^= sample >> 2;
  162. sample ^= sample >> 1;
  163. return (sample & 1) << 27;
  164. }
  165. static void dw_hdmi_reformat_s24(struct snd_dw_hdmi *dw,
  166. size_t offset, size_t bytes)
  167. {
  168. u32 *src = dw->buf_src + offset;
  169. u32 *dst = dw->buf_dst + offset;
  170. u32 *end = dw->buf_src + offset + bytes;
  171. do {
  172. unsigned i;
  173. u8 *cs;
  174. cs = dw->cs[dw->iec_offset++];
  175. if (dw->iec_offset >= 192)
  176. dw->iec_offset = 0;
  177. i = dw->channels;
  178. do {
  179. u32 sample = *src++;
  180. sample &= ~0xff000000;
  181. sample |= *cs++ << 24;
  182. sample |= parity(sample & ~0xf8000000);
  183. *dst++ = sample;
  184. } while (--i);
  185. } while (src < end);
  186. }
  187. static void dw_hdmi_create_cs(struct snd_dw_hdmi *dw,
  188. struct snd_pcm_runtime *runtime)
  189. {
  190. u8 cs[4];
  191. unsigned ch, i, j;
  192. snd_pcm_create_iec958_consumer(runtime, cs, sizeof(cs));
  193. memset(dw->cs, 0, sizeof(dw->cs));
  194. for (ch = 0; ch < 8; ch++) {
  195. cs[2] &= ~IEC958_AES2_CON_CHANNEL;
  196. cs[2] |= (ch + 1) << 4;
  197. for (i = 0; i < ARRAY_SIZE(cs); i++) {
  198. unsigned c = cs[i];
  199. for (j = 0; j < 8; j++, c >>= 1)
  200. dw->cs[i * 8 + j][ch] = (c & 1) << 2;
  201. }
  202. }
  203. dw->cs[0][0] |= BIT(4);
  204. }
  205. static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw)
  206. {
  207. void __iomem *base = dw->data.base;
  208. unsigned offset = dw->buf_offset;
  209. unsigned period = dw->buf_period;
  210. u32 start, stop;
  211. dw->reformat(dw, offset, period);
  212. /* Clear all irqs before enabling irqs and starting DMA */
  213. writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL,
  214. base + HDMI_IH_AHBDMAAUD_STAT0);
  215. start = dw->buf_addr + offset;
  216. stop = start + period - 1;
  217. /* Setup the hardware start/stop addresses */
  218. dw_hdmi_writel(start, base + HDMI_AHB_DMA_STRADDR0);
  219. dw_hdmi_writel(stop, base + HDMI_AHB_DMA_STPADDR0);
  220. writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK);
  221. writeb(HDMI_AHB_DMA_START_START, base + HDMI_AHB_DMA_START);
  222. offset += period;
  223. if (offset >= dw->buf_size)
  224. offset = 0;
  225. dw->buf_offset = offset;
  226. }
  227. static void dw_hdmi_stop_dma(struct snd_dw_hdmi *dw)
  228. {
  229. /* Disable interrupts before disabling DMA */
  230. writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK);
  231. writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP);
  232. }
  233. static irqreturn_t snd_dw_hdmi_irq(int irq, void *data)
  234. {
  235. struct snd_dw_hdmi *dw = data;
  236. struct snd_pcm_substream *substream;
  237. unsigned stat;
  238. stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);
  239. if (!stat)
  240. return IRQ_NONE;
  241. writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);
  242. substream = dw->substream;
  243. if (stat & HDMI_IH_AHBDMAAUD_STAT0_DONE && substream) {
  244. snd_pcm_period_elapsed(substream);
  245. spin_lock(&dw->lock);
  246. if (dw->substream)
  247. dw_hdmi_start_dma(dw);
  248. spin_unlock(&dw->lock);
  249. }
  250. return IRQ_HANDLED;
  251. }
  252. static const struct snd_pcm_hardware dw_hdmi_hw = {
  253. .info = SNDRV_PCM_INFO_INTERLEAVED |
  254. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  255. SNDRV_PCM_INFO_MMAP |
  256. SNDRV_PCM_INFO_MMAP_VALID,
  257. .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE |
  258. SNDRV_PCM_FMTBIT_S24_LE,
  259. .rates = SNDRV_PCM_RATE_32000 |
  260. SNDRV_PCM_RATE_44100 |
  261. SNDRV_PCM_RATE_48000 |
  262. SNDRV_PCM_RATE_88200 |
  263. SNDRV_PCM_RATE_96000 |
  264. SNDRV_PCM_RATE_176400 |
  265. SNDRV_PCM_RATE_192000,
  266. .channels_min = 2,
  267. .channels_max = 8,
  268. .buffer_bytes_max = 1024 * 1024,
  269. .period_bytes_min = 256,
  270. .period_bytes_max = 8192, /* ERR004323: must limit to 8k */
  271. .periods_min = 2,
  272. .periods_max = 16,
  273. .fifo_size = 0,
  274. };
  275. static int dw_hdmi_open(struct snd_pcm_substream *substream)
  276. {
  277. struct snd_pcm_runtime *runtime = substream->runtime;
  278. struct snd_dw_hdmi *dw = substream->private_data;
  279. void __iomem *base = dw->data.base;
  280. u8 *eld;
  281. int ret;
  282. runtime->hw = dw_hdmi_hw;
  283. eld = dw->data.get_eld(dw->data.hdmi);
  284. if (eld) {
  285. ret = snd_pcm_hw_constraint_eld(runtime, eld);
  286. if (ret < 0)
  287. return ret;
  288. }
  289. ret = snd_pcm_limit_hw_rates(runtime);
  290. if (ret < 0)
  291. return ret;
  292. ret = snd_pcm_hw_constraint_integer(runtime,
  293. SNDRV_PCM_HW_PARAM_PERIODS);
  294. if (ret < 0)
  295. return ret;
  296. /* Limit the buffer size to the size of the preallocated buffer */
  297. ret = snd_pcm_hw_constraint_minmax(runtime,
  298. SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
  299. 0, substream->dma_buffer.bytes);
  300. if (ret < 0)
  301. return ret;
  302. /* Clear FIFO */
  303. writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST,
  304. base + HDMI_AHB_DMA_CONF0);
  305. /* Configure interrupt polarities */
  306. writeb_relaxed(~0, base + HDMI_AHB_DMA_POL);
  307. writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL);
  308. /* Keep interrupts masked, and clear any pending */
  309. writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK);
  310. writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0);
  311. ret = request_irq(dw->data.irq, snd_dw_hdmi_irq, IRQF_SHARED,
  312. "dw-hdmi-audio", dw);
  313. if (ret)
  314. return ret;
  315. /* Un-mute done interrupt */
  316. writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL &
  317. ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE,
  318. base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
  319. return 0;
  320. }
  321. static int dw_hdmi_close(struct snd_pcm_substream *substream)
  322. {
  323. struct snd_dw_hdmi *dw = substream->private_data;
  324. /* Mute all interrupts */
  325. writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,
  326. dw->data.base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
  327. free_irq(dw->data.irq, dw);
  328. return 0;
  329. }
  330. static int dw_hdmi_hw_free(struct snd_pcm_substream *substream)
  331. {
  332. return snd_pcm_lib_free_vmalloc_buffer(substream);
  333. }
  334. static int dw_hdmi_hw_params(struct snd_pcm_substream *substream,
  335. struct snd_pcm_hw_params *params)
  336. {
  337. /* Allocate the PCM runtime buffer, which is exposed to userspace. */
  338. return snd_pcm_lib_alloc_vmalloc_buffer(substream,
  339. params_buffer_bytes(params));
  340. }
  341. static int dw_hdmi_prepare(struct snd_pcm_substream *substream)
  342. {
  343. struct snd_pcm_runtime *runtime = substream->runtime;
  344. struct snd_dw_hdmi *dw = substream->private_data;
  345. u8 threshold, conf0, conf1, ca;
  346. /* Setup as per 3.0.5 FSL 4.1.0 BSP */
  347. switch (dw->revision) {
  348. case 0x0a:
  349. conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
  350. HDMI_AHB_DMA_CONF0_INCR4;
  351. if (runtime->channels == 2)
  352. threshold = 126;
  353. else
  354. threshold = 124;
  355. break;
  356. case 0x1a:
  357. conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
  358. HDMI_AHB_DMA_CONF0_INCR8;
  359. threshold = 128;
  360. break;
  361. default:
  362. /* NOTREACHED */
  363. return -EINVAL;
  364. }
  365. dw_hdmi_set_sample_rate(dw->data.hdmi, runtime->rate);
  366. /* Minimum number of bytes in the fifo. */
  367. runtime->hw.fifo_size = threshold * 32;
  368. conf0 |= HDMI_AHB_DMA_CONF0_EN_HLOCK;
  369. conf1 = default_hdmi_channel_config[runtime->channels - 2].conf1;
  370. ca = default_hdmi_channel_config[runtime->channels - 2].ca;
  371. writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD);
  372. writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0);
  373. writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1);
  374. dw_hdmi_set_channel_count(dw->data.hdmi, runtime->channels);
  375. dw_hdmi_set_channel_allocation(dw->data.hdmi, ca);
  376. switch (runtime->format) {
  377. case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
  378. dw->reformat = dw_hdmi_reformat_iec958;
  379. break;
  380. case SNDRV_PCM_FORMAT_S24_LE:
  381. dw_hdmi_create_cs(dw, runtime);
  382. dw->reformat = dw_hdmi_reformat_s24;
  383. break;
  384. }
  385. dw->iec_offset = 0;
  386. dw->channels = runtime->channels;
  387. dw->buf_src = runtime->dma_area;
  388. dw->buf_dst = substream->dma_buffer.area;
  389. dw->buf_addr = substream->dma_buffer.addr;
  390. dw->buf_period = snd_pcm_lib_period_bytes(substream);
  391. dw->buf_size = snd_pcm_lib_buffer_bytes(substream);
  392. return 0;
  393. }
  394. static int dw_hdmi_trigger(struct snd_pcm_substream *substream, int cmd)
  395. {
  396. struct snd_dw_hdmi *dw = substream->private_data;
  397. unsigned long flags;
  398. int ret = 0;
  399. switch (cmd) {
  400. case SNDRV_PCM_TRIGGER_START:
  401. spin_lock_irqsave(&dw->lock, flags);
  402. dw->buf_offset = 0;
  403. dw->substream = substream;
  404. dw_hdmi_start_dma(dw);
  405. dw_hdmi_audio_enable(dw->data.hdmi);
  406. spin_unlock_irqrestore(&dw->lock, flags);
  407. substream->runtime->delay = substream->runtime->period_size;
  408. break;
  409. case SNDRV_PCM_TRIGGER_STOP:
  410. spin_lock_irqsave(&dw->lock, flags);
  411. dw->substream = NULL;
  412. dw_hdmi_stop_dma(dw);
  413. dw_hdmi_audio_disable(dw->data.hdmi);
  414. spin_unlock_irqrestore(&dw->lock, flags);
  415. break;
  416. default:
  417. ret = -EINVAL;
  418. break;
  419. }
  420. return ret;
  421. }
  422. static snd_pcm_uframes_t dw_hdmi_pointer(struct snd_pcm_substream *substream)
  423. {
  424. struct snd_pcm_runtime *runtime = substream->runtime;
  425. struct snd_dw_hdmi *dw = substream->private_data;
  426. /*
  427. * We are unable to report the exact hardware position as
  428. * reading the 32-bit DMA position using 8-bit reads is racy.
  429. */
  430. return bytes_to_frames(runtime, dw->buf_offset);
  431. }
  432. static const struct snd_pcm_ops snd_dw_hdmi_ops = {
  433. .open = dw_hdmi_open,
  434. .close = dw_hdmi_close,
  435. .ioctl = snd_pcm_lib_ioctl,
  436. .hw_params = dw_hdmi_hw_params,
  437. .hw_free = dw_hdmi_hw_free,
  438. .prepare = dw_hdmi_prepare,
  439. .trigger = dw_hdmi_trigger,
  440. .pointer = dw_hdmi_pointer,
  441. .page = snd_pcm_lib_get_vmalloc_page,
  442. };
  443. static int snd_dw_hdmi_probe(struct platform_device *pdev)
  444. {
  445. const struct dw_hdmi_audio_data *data = pdev->dev.platform_data;
  446. struct device *dev = pdev->dev.parent;
  447. struct snd_dw_hdmi *dw;
  448. struct snd_card *card;
  449. struct snd_pcm *pcm;
  450. unsigned revision;
  451. int ret;
  452. writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,
  453. data->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
  454. revision = readb_relaxed(data->base + HDMI_REVISION_ID);
  455. if (revision != 0x0a && revision != 0x1a) {
  456. dev_err(dev, "dw-hdmi-audio: unknown revision 0x%02x\n",
  457. revision);
  458. return -ENXIO;
  459. }
  460. ret = snd_card_new(dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  461. THIS_MODULE, sizeof(struct snd_dw_hdmi), &card);
  462. if (ret < 0)
  463. return ret;
  464. strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
  465. strlcpy(card->shortname, "DW-HDMI", sizeof(card->shortname));
  466. snprintf(card->longname, sizeof(card->longname),
  467. "%s rev 0x%02x, irq %d", card->shortname, revision,
  468. data->irq);
  469. dw = card->private_data;
  470. dw->card = card;
  471. dw->data = *data;
  472. dw->revision = revision;
  473. spin_lock_init(&dw->lock);
  474. ret = snd_pcm_new(card, "DW HDMI", 0, 1, 0, &pcm);
  475. if (ret < 0)
  476. goto err;
  477. dw->pcm = pcm;
  478. pcm->private_data = dw;
  479. strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
  480. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dw_hdmi_ops);
  481. /*
  482. * To support 8-channel 96kHz audio reliably, we need 512k
  483. * to satisfy alsa with our restricted period (ERR004323).
  484. */
  485. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  486. dev, 128 * 1024, 1024 * 1024);
  487. ret = snd_card_register(card);
  488. if (ret < 0)
  489. goto err;
  490. platform_set_drvdata(pdev, dw);
  491. return 0;
  492. err:
  493. snd_card_free(card);
  494. return ret;
  495. }
  496. static int snd_dw_hdmi_remove(struct platform_device *pdev)
  497. {
  498. struct snd_dw_hdmi *dw = platform_get_drvdata(pdev);
  499. snd_card_free(dw->card);
  500. return 0;
  501. }
  502. #if defined(CONFIG_PM_SLEEP) && defined(IS_NOT_BROKEN)
  503. /*
  504. * This code is fine, but requires implementation in the dw_hdmi_trigger()
  505. * method which is currently missing as I have no way to test this.
  506. */
  507. static int snd_dw_hdmi_suspend(struct device *dev)
  508. {
  509. struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
  510. snd_power_change_state(dw->card, SNDRV_CTL_POWER_D3cold);
  511. return 0;
  512. }
  513. static int snd_dw_hdmi_resume(struct device *dev)
  514. {
  515. struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
  516. snd_power_change_state(dw->card, SNDRV_CTL_POWER_D0);
  517. return 0;
  518. }
  519. static SIMPLE_DEV_PM_OPS(snd_dw_hdmi_pm, snd_dw_hdmi_suspend,
  520. snd_dw_hdmi_resume);
  521. #define PM_OPS &snd_dw_hdmi_pm
  522. #else
  523. #define PM_OPS NULL
  524. #endif
  525. static struct platform_driver snd_dw_hdmi_driver = {
  526. .probe = snd_dw_hdmi_probe,
  527. .remove = snd_dw_hdmi_remove,
  528. .driver = {
  529. .name = DRIVER_NAME,
  530. .pm = PM_OPS,
  531. },
  532. };
  533. module_platform_driver(snd_dw_hdmi_driver);
  534. MODULE_AUTHOR("Russell King <rmk+kernel@armlinux.org.uk>");
  535. MODULE_DESCRIPTION("Synopsis Designware HDMI AHB ALSA interface");
  536. MODULE_LICENSE("GPL v2");
  537. MODULE_ALIAS("platform:" DRIVER_NAME);