sil-sii8620.h 51 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Registers of Silicon Image SiI8620 Mobile HD Transmitter
  4. *
  5. * Copyright (C) 2015, Samsung Electronics Co., Ltd.
  6. * Andrzej Hajda <a.hajda@samsung.com>
  7. *
  8. * Based on MHL driver for Android devices.
  9. * Copyright (C) 2013-2014 Silicon Image, Inc.
  10. */
  11. #ifndef __SIL_SII8620_H__
  12. #define __SIL_SII8620_H__
  13. /* Vendor ID Low byte, default value: 0x01 */
  14. #define REG_VND_IDL 0x0000
  15. /* Vendor ID High byte, default value: 0x00 */
  16. #define REG_VND_IDH 0x0001
  17. /* Device ID Low byte, default value: 0x60 */
  18. #define REG_DEV_IDL 0x0002
  19. /* Device ID High byte, default value: 0x86 */
  20. #define REG_DEV_IDH 0x0003
  21. /* Device Revision, default value: 0x10 */
  22. #define REG_DEV_REV 0x0004
  23. /* OTP DBYTE510, default value: 0x00 */
  24. #define REG_OTP_DBYTE510 0x0006
  25. /* System Control #1, default value: 0x00 */
  26. #define REG_SYS_CTRL1 0x0008
  27. #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
  28. #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
  29. #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
  30. #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
  31. #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
  32. #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
  33. #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
  34. #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
  35. /* System Control DPD, default value: 0x90 */
  36. #define REG_DPD 0x000b
  37. #define BIT_DPD_PWRON_PLL BIT(7)
  38. #define BIT_DPD_PDNTX12 BIT(6)
  39. #define BIT_DPD_PDNRX12 BIT(5)
  40. #define BIT_DPD_OSC_EN BIT(4)
  41. #define BIT_DPD_PWRON_HSIC BIT(3)
  42. #define BIT_DPD_PDIDCK_N BIT(2)
  43. #define BIT_DPD_PD_MHL_CLK_N BIT(1)
  44. /* Dual link Control, default value: 0x00 */
  45. #define REG_DCTL 0x000d
  46. #define BIT_DCTL_TDM_LCLK_PHASE BIT(7)
  47. #define BIT_DCTL_HSIC_CLK_PHASE BIT(6)
  48. #define BIT_DCTL_CTS_TCK_PHASE BIT(5)
  49. #define BIT_DCTL_EXT_DDC_SEL BIT(4)
  50. #define BIT_DCTL_TRANSCODE BIT(3)
  51. #define BIT_DCTL_HSIC_RX_STROBE_PHASE BIT(2)
  52. #define BIT_DCTL_HSIC_TX_BIST_START_SEL BIT(1)
  53. #define BIT_DCTL_TCLKNX_PHASE BIT(0)
  54. /* PWD Software Reset, default value: 0x20 */
  55. #define REG_PWD_SRST 0x000e
  56. #define BIT_PWD_SRST_COC_DOC_RST BIT(7)
  57. #define BIT_PWD_SRST_CBUS_RST_SW BIT(6)
  58. #define BIT_PWD_SRST_CBUS_RST_SW_EN BIT(5)
  59. #define BIT_PWD_SRST_MHLFIFO_RST BIT(4)
  60. #define BIT_PWD_SRST_CBUS_RST BIT(3)
  61. #define BIT_PWD_SRST_SW_RST_AUTO BIT(2)
  62. #define BIT_PWD_SRST_HDCP2X_SW_RST BIT(1)
  63. #define BIT_PWD_SRST_SW_RST BIT(0)
  64. /* AKSV_1, default value: 0x00 */
  65. #define REG_AKSV_1 0x001d
  66. /* Video H Resolution #1, default value: 0x00 */
  67. #define REG_H_RESL 0x003a
  68. /* Video Mode, default value: 0x00 */
  69. #define REG_VID_MODE 0x004a
  70. #define BIT_VID_MODE_M1080P BIT(6)
  71. /* Video Input Mode, default value: 0xc0 */
  72. #define REG_VID_OVRRD 0x0051
  73. #define BIT_VID_OVRRD_PP_AUTO_DISABLE BIT(7)
  74. #define BIT_VID_OVRRD_M1080P_OVRRD BIT(6)
  75. #define BIT_VID_OVRRD_MINIVSYNC_ON BIT(5)
  76. #define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK BIT(4)
  77. #define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN BIT(3)
  78. #define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD BIT(2)
  79. #define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD BIT(0)
  80. /* I2C Address reassignment, default value: 0x00 */
  81. #define REG_PAGE_MHLSPEC_ADDR 0x0057
  82. #define REG_PAGE7_ADDR 0x0058
  83. #define REG_PAGE8_ADDR 0x005c
  84. /* Fast Interrupt Status, default value: 0x00 */
  85. #define REG_FAST_INTR_STAT 0x005f
  86. #define LEN_FAST_INTR_STAT 7
  87. #define BIT_FAST_INTR_STAT_TIMR 8
  88. #define BIT_FAST_INTR_STAT_INT2 9
  89. #define BIT_FAST_INTR_STAT_DDC 10
  90. #define BIT_FAST_INTR_STAT_SCDT 11
  91. #define BIT_FAST_INTR_STAT_INFR 13
  92. #define BIT_FAST_INTR_STAT_EDID 14
  93. #define BIT_FAST_INTR_STAT_HDCP 15
  94. #define BIT_FAST_INTR_STAT_MSC 16
  95. #define BIT_FAST_INTR_STAT_MERR 17
  96. #define BIT_FAST_INTR_STAT_G2WB 18
  97. #define BIT_FAST_INTR_STAT_G2WB_ERR 19
  98. #define BIT_FAST_INTR_STAT_DISC 28
  99. #define BIT_FAST_INTR_STAT_BLOCK 30
  100. #define BIT_FAST_INTR_STAT_LTRN 31
  101. #define BIT_FAST_INTR_STAT_HDCP2 32
  102. #define BIT_FAST_INTR_STAT_TDM 42
  103. #define BIT_FAST_INTR_STAT_COC 51
  104. /* GPIO Control, default value: 0x15 */
  105. #define REG_GPIO_CTRL1 0x006e
  106. #define BIT_CTRL1_GPIO_I_8 BIT(5)
  107. #define BIT_CTRL1_GPIO_OEN_8 BIT(4)
  108. #define BIT_CTRL1_GPIO_I_7 BIT(3)
  109. #define BIT_CTRL1_GPIO_OEN_7 BIT(2)
  110. #define BIT_CTRL1_GPIO_I_6 BIT(1)
  111. #define BIT_CTRL1_GPIO_OEN_6 BIT(0)
  112. /* Interrupt Control, default value: 0x06 */
  113. #define REG_INT_CTRL 0x006f
  114. #define BIT_INT_CTRL_SOFTWARE_WP BIT(7)
  115. #define BIT_INT_CTRL_INTR_OD BIT(2)
  116. #define BIT_INT_CTRL_INTR_POLARITY BIT(1)
  117. /* Interrupt State, default value: 0x00 */
  118. #define REG_INTR_STATE 0x0070
  119. #define BIT_INTR_STATE_INTR_STATE BIT(0)
  120. /* Interrupt Source #1, default value: 0x00 */
  121. #define REG_INTR1 0x0071
  122. /* Interrupt Source #2, default value: 0x00 */
  123. #define REG_INTR2 0x0072
  124. /* Interrupt Source #3, default value: 0x01 */
  125. #define REG_INTR3 0x0073
  126. #define BIT_DDC_CMD_DONE BIT(3)
  127. /* Interrupt Source #5, default value: 0x00 */
  128. #define REG_INTR5 0x0074
  129. /* Interrupt #1 Mask, default value: 0x00 */
  130. #define REG_INTR1_MASK 0x0075
  131. /* Interrupt #2 Mask, default value: 0x00 */
  132. #define REG_INTR2_MASK 0x0076
  133. /* Interrupt #3 Mask, default value: 0x00 */
  134. #define REG_INTR3_MASK 0x0077
  135. /* Interrupt #5 Mask, default value: 0x00 */
  136. #define REG_INTR5_MASK 0x0078
  137. #define BIT_INTR_SCDT_CHANGE BIT(0)
  138. /* Hot Plug Connection Control, default value: 0x45 */
  139. #define REG_HPD_CTRL 0x0079
  140. #define BIT_HPD_CTRL_HPD_DS_SIGNAL BIT(7)
  141. #define BIT_HPD_CTRL_HPD_OUT_OD_EN BIT(6)
  142. #define BIT_HPD_CTRL_HPD_HIGH BIT(5)
  143. #define BIT_HPD_CTRL_HPD_OUT_OVR_EN BIT(4)
  144. #define BIT_HPD_CTRL_GPIO_I_1 BIT(3)
  145. #define BIT_HPD_CTRL_GPIO_OEN_1 BIT(2)
  146. #define BIT_HPD_CTRL_GPIO_I_0 BIT(1)
  147. #define BIT_HPD_CTRL_GPIO_OEN_0 BIT(0)
  148. /* GPIO Control, default value: 0x55 */
  149. #define REG_GPIO_CTRL 0x007a
  150. #define BIT_CTRL_GPIO_I_5 BIT(7)
  151. #define BIT_CTRL_GPIO_OEN_5 BIT(6)
  152. #define BIT_CTRL_GPIO_I_4 BIT(5)
  153. #define BIT_CTRL_GPIO_OEN_4 BIT(4)
  154. #define BIT_CTRL_GPIO_I_3 BIT(3)
  155. #define BIT_CTRL_GPIO_OEN_3 BIT(2)
  156. #define BIT_CTRL_GPIO_I_2 BIT(1)
  157. #define BIT_CTRL_GPIO_OEN_2 BIT(0)
  158. /* Interrupt Source 7, default value: 0x00 */
  159. #define REG_INTR7 0x007b
  160. /* Interrupt Source 8, default value: 0x00 */
  161. #define REG_INTR8 0x007c
  162. /* Interrupt #7 Mask, default value: 0x00 */
  163. #define REG_INTR7_MASK 0x007d
  164. /* Interrupt #8 Mask, default value: 0x00 */
  165. #define REG_INTR8_MASK 0x007e
  166. #define BIT_CEA_NEW_VSI BIT(2)
  167. #define BIT_CEA_NEW_AVI BIT(1)
  168. /* IEEE, default value: 0x10 */
  169. #define REG_TMDS_CCTRL 0x0080
  170. #define BIT_TMDS_CCTRL_TMDS_OE BIT(4)
  171. /* TMDS Control #4, default value: 0x02 */
  172. #define REG_TMDS_CTRL4 0x0085
  173. #define BIT_TMDS_CTRL4_SCDT_CKDT_SEL BIT(1)
  174. #define BIT_TMDS_CTRL4_TX_EN_BY_SCDT BIT(0)
  175. /* BIST CNTL, default value: 0x00 */
  176. #define REG_BIST_CTRL 0x00bb
  177. #define BIT_RXBIST_VGB_EN BIT(7)
  178. #define BIT_TXBIST_VGB_EN BIT(6)
  179. #define BIT_BIST_START_SEL BIT(5)
  180. #define BIT_BIST_START_BIT BIT(4)
  181. #define BIT_BIST_ALWAYS_ON BIT(3)
  182. #define BIT_BIST_TRANS BIT(2)
  183. #define BIT_BIST_RESET BIT(1)
  184. #define BIT_BIST_EN BIT(0)
  185. /* BIST DURATION0, default value: 0x00 */
  186. #define REG_BIST_TEST_SEL 0x00bd
  187. #define MSK_BIST_TEST_SEL_BIST_PATT_SEL 0x0f
  188. /* BIST VIDEO_MODE, default value: 0x00 */
  189. #define REG_BIST_VIDEO_MODE 0x00be
  190. #define MSK_BIST_VIDEO_MODE_BIST_VIDEO_MODE_3_0 0x0f
  191. /* BIST DURATION0, default value: 0x00 */
  192. #define REG_BIST_DURATION_0 0x00bf
  193. /* BIST DURATION1, default value: 0x00 */
  194. #define REG_BIST_DURATION_1 0x00c0
  195. /* BIST DURATION2, default value: 0x00 */
  196. #define REG_BIST_DURATION_2 0x00c1
  197. /* BIST 8BIT_PATTERN, default value: 0x00 */
  198. #define REG_BIST_8BIT_PATTERN 0x00c2
  199. /* LM DDC, default value: 0x80 */
  200. #define REG_LM_DDC 0x00c7
  201. #define BIT_LM_DDC_SW_TPI_EN_DISABLED BIT(7)
  202. #define BIT_LM_DDC_VIDEO_MUTE_EN BIT(5)
  203. #define BIT_LM_DDC_DDC_TPI_SW BIT(2)
  204. #define BIT_LM_DDC_DDC_GRANT BIT(1)
  205. #define BIT_LM_DDC_DDC_GPU_REQUEST BIT(0)
  206. /* DDC I2C Manual, default value: 0x03 */
  207. #define REG_DDC_MANUAL 0x00ec
  208. #define BIT_DDC_MANUAL_MAN_DDC BIT(7)
  209. #define BIT_DDC_MANUAL_VP_SEL BIT(6)
  210. #define BIT_DDC_MANUAL_DSDA BIT(5)
  211. #define BIT_DDC_MANUAL_DSCL BIT(4)
  212. #define BIT_DDC_MANUAL_GCP_HW_CTL_EN BIT(3)
  213. #define BIT_DDC_MANUAL_DDCM_ABORT_WP BIT(2)
  214. #define BIT_DDC_MANUAL_IO_DSDA BIT(1)
  215. #define BIT_DDC_MANUAL_IO_DSCL BIT(0)
  216. /* DDC I2C Target Slave Address, default value: 0x00 */
  217. #define REG_DDC_ADDR 0x00ed
  218. #define MSK_DDC_ADDR_DDC_ADDR 0xfe
  219. /* DDC I2C Target Segment Address, default value: 0x00 */
  220. #define REG_DDC_SEGM 0x00ee
  221. /* DDC I2C Target Offset Address, default value: 0x00 */
  222. #define REG_DDC_OFFSET 0x00ef
  223. /* DDC I2C Data In count #1, default value: 0x00 */
  224. #define REG_DDC_DIN_CNT1 0x00f0
  225. /* DDC I2C Data In count #2, default value: 0x00 */
  226. #define REG_DDC_DIN_CNT2 0x00f1
  227. #define MSK_DDC_DIN_CNT2_DDC_DIN_CNT_9_8 0x03
  228. /* DDC I2C Status, default value: 0x04 */
  229. #define REG_DDC_STATUS 0x00f2
  230. #define BIT_DDC_STATUS_DDC_BUS_LOW BIT(6)
  231. #define BIT_DDC_STATUS_DDC_NO_ACK BIT(5)
  232. #define BIT_DDC_STATUS_DDC_I2C_IN_PROG BIT(4)
  233. #define BIT_DDC_STATUS_DDC_FIFO_FULL BIT(3)
  234. #define BIT_DDC_STATUS_DDC_FIFO_EMPTY BIT(2)
  235. #define BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE BIT(1)
  236. #define BIT_DDC_STATUS_DDC_FIFO_WRITE_IN_USE BIT(0)
  237. /* DDC I2C Command, default value: 0x70 */
  238. #define REG_DDC_CMD 0x00f3
  239. #define BIT_DDC_CMD_HDCP_DDC_EN BIT(6)
  240. #define BIT_DDC_CMD_SDA_DEL_EN BIT(5)
  241. #define BIT_DDC_CMD_DDC_FLT_EN BIT(4)
  242. #define MSK_DDC_CMD_DDC_CMD 0x0f
  243. #define VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 0x04
  244. #define VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO 0x09
  245. #define VAL_DDC_CMD_DDC_CMD_ABORT 0x0f
  246. /* DDC I2C FIFO Data In/Out, default value: 0x00 */
  247. #define REG_DDC_DATA 0x00f4
  248. /* DDC I2C Data Out Counter, default value: 0x00 */
  249. #define REG_DDC_DOUT_CNT 0x00f5
  250. #define BIT_DDC_DOUT_CNT_DDC_DELAY_CNT_8 BIT(7)
  251. #define MSK_DDC_DOUT_CNT_DDC_DATA_OUT_CNT 0x1f
  252. /* DDC I2C Delay Count, default value: 0x14 */
  253. #define REG_DDC_DELAY_CNT 0x00f6
  254. /* Test Control, default value: 0x80 */
  255. #define REG_TEST_TXCTRL 0x00f7
  256. #define BIT_TEST_TXCTRL_RCLK_REF_SEL BIT(7)
  257. #define BIT_TEST_TXCTRL_PCLK_REF_SEL BIT(6)
  258. #define MSK_TEST_TXCTRL_BYPASS_PLL_CLK 0x3c
  259. #define BIT_TEST_TXCTRL_HDMI_MODE BIT(1)
  260. #define BIT_TEST_TXCTRL_TST_PLLCK BIT(0)
  261. /* CBUS Address, default value: 0x00 */
  262. #define REG_PAGE_CBUS_ADDR 0x00f8
  263. /* I2C Device Address re-assignment */
  264. #define REG_PAGE1_ADDR 0x00fc
  265. #define REG_PAGE2_ADDR 0x00fd
  266. #define REG_PAGE3_ADDR 0x00fe
  267. #define REG_HW_TPI_ADDR 0x00ff
  268. /* USBT CTRL0, default value: 0x00 */
  269. #define REG_UTSRST 0x0100
  270. #define BIT_UTSRST_FC_SRST BIT(5)
  271. #define BIT_UTSRST_KEEPER_SRST BIT(4)
  272. #define BIT_UTSRST_HTX_SRST BIT(3)
  273. #define BIT_UTSRST_TRX_SRST BIT(2)
  274. #define BIT_UTSRST_TTX_SRST BIT(1)
  275. #define BIT_UTSRST_HRX_SRST BIT(0)
  276. /* HSIC RX Control3, default value: 0x07 */
  277. #define REG_HRXCTRL3 0x0104
  278. #define MSK_HRXCTRL3_HRX_AFFCTRL 0xf0
  279. #define BIT_HRXCTRL3_HRX_OUT_EN BIT(2)
  280. #define BIT_HRXCTRL3_STATUS_EN BIT(1)
  281. #define BIT_HRXCTRL3_HRX_STAY_RESET BIT(0)
  282. /* HSIC RX INT Registers */
  283. #define REG_HRXINTL 0x0111
  284. #define REG_HRXINTH 0x0112
  285. /* TDM TX NUMBITS, default value: 0x0c */
  286. #define REG_TTXNUMB 0x0116
  287. #define MSK_TTXNUMB_TTX_AFFCTRL_3_0 0xf0
  288. #define BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT BIT(3)
  289. #define MSK_TTXNUMB_TTX_NUMBPS 0x07
  290. /* TDM TX NUMSPISYM, default value: 0x04 */
  291. #define REG_TTXSPINUMS 0x0117
  292. /* TDM TX NUMHSICSYM, default value: 0x14 */
  293. #define REG_TTXHSICNUMS 0x0118
  294. /* TDM TX NUMTOTSYM, default value: 0x18 */
  295. #define REG_TTXTOTNUMS 0x0119
  296. /* TDM TX INT Low, default value: 0x00 */
  297. #define REG_TTXINTL 0x0136
  298. #define BIT_TTXINTL_TTX_INTR7 BIT(7)
  299. #define BIT_TTXINTL_TTX_INTR6 BIT(6)
  300. #define BIT_TTXINTL_TTX_INTR5 BIT(5)
  301. #define BIT_TTXINTL_TTX_INTR4 BIT(4)
  302. #define BIT_TTXINTL_TTX_INTR3 BIT(3)
  303. #define BIT_TTXINTL_TTX_INTR2 BIT(2)
  304. #define BIT_TTXINTL_TTX_INTR1 BIT(1)
  305. #define BIT_TTXINTL_TTX_INTR0 BIT(0)
  306. /* TDM TX INT High, default value: 0x00 */
  307. #define REG_TTXINTH 0x0137
  308. #define BIT_TTXINTH_TTX_INTR15 BIT(7)
  309. #define BIT_TTXINTH_TTX_INTR14 BIT(6)
  310. #define BIT_TTXINTH_TTX_INTR13 BIT(5)
  311. #define BIT_TTXINTH_TTX_INTR12 BIT(4)
  312. #define BIT_TTXINTH_TTX_INTR11 BIT(3)
  313. #define BIT_TTXINTH_TTX_INTR10 BIT(2)
  314. #define BIT_TTXINTH_TTX_INTR9 BIT(1)
  315. #define BIT_TTXINTH_TTX_INTR8 BIT(0)
  316. /* TDM RX Control, default value: 0x1c */
  317. #define REG_TRXCTRL 0x013b
  318. #define BIT_TRXCTRL_TRX_CLR_WVALLOW BIT(4)
  319. #define BIT_TRXCTRL_TRX_FROM_SE_COC BIT(3)
  320. #define MSK_TRXCTRL_TRX_NUMBPS_2_0 0x07
  321. /* TDM RX NUMSPISYM, default value: 0x04 */
  322. #define REG_TRXSPINUMS 0x013c
  323. /* TDM RX NUMHSICSYM, default value: 0x14 */
  324. #define REG_TRXHSICNUMS 0x013d
  325. /* TDM RX NUMTOTSYM, default value: 0x18 */
  326. #define REG_TRXTOTNUMS 0x013e
  327. /* TDM RX Status 2nd, default value: 0x00 */
  328. #define REG_TRXSTA2 0x015c
  329. #define MSK_TDM_SYNCHRONIZED 0xc0
  330. #define VAL_TDM_SYNCHRONIZED 0x80
  331. /* TDM RX INT Low, default value: 0x00 */
  332. #define REG_TRXINTL 0x0163
  333. /* TDM RX INT High, default value: 0x00 */
  334. #define REG_TRXINTH 0x0164
  335. #define BIT_TDM_INTR_SYNC_DATA BIT(0)
  336. #define BIT_TDM_INTR_SYNC_WAIT BIT(1)
  337. /* TDM RX INTMASK High, default value: 0x00 */
  338. #define REG_TRXINTMH 0x0166
  339. /* HSIC TX CRTL, default value: 0x00 */
  340. #define REG_HTXCTRL 0x0169
  341. #define BIT_HTXCTRL_HTX_ALLSBE_SOP BIT(4)
  342. #define BIT_HTXCTRL_HTX_RGDINV_USB BIT(3)
  343. #define BIT_HTXCTRL_HTX_RSPTDM_BUSY BIT(2)
  344. #define BIT_HTXCTRL_HTX_DRVCONN1 BIT(1)
  345. #define BIT_HTXCTRL_HTX_DRVRST1 BIT(0)
  346. /* HSIC TX INT Low, default value: 0x00 */
  347. #define REG_HTXINTL 0x017d
  348. /* HSIC TX INT High, default value: 0x00 */
  349. #define REG_HTXINTH 0x017e
  350. /* HSIC Keeper, default value: 0x00 */
  351. #define REG_KEEPER 0x0181
  352. #define MSK_KEEPER_MODE 0x03
  353. #define VAL_KEEPER_MODE_HOST 0
  354. #define VAL_KEEPER_MODE_DEVICE 2
  355. /* HSIC Flow Control General, default value: 0x02 */
  356. #define REG_FCGC 0x0183
  357. #define BIT_FCGC_HSIC_HOSTMODE BIT(1)
  358. #define BIT_FCGC_HSIC_ENABLE BIT(0)
  359. /* HSIC Flow Control CTR13, default value: 0xfc */
  360. #define REG_FCCTR13 0x0191
  361. /* HSIC Flow Control CTR14, default value: 0xff */
  362. #define REG_FCCTR14 0x0192
  363. /* HSIC Flow Control CTR15, default value: 0xff */
  364. #define REG_FCCTR15 0x0193
  365. /* HSIC Flow Control CTR50, default value: 0x03 */
  366. #define REG_FCCTR50 0x01b6
  367. /* HSIC Flow Control INTR0, default value: 0x00 */
  368. #define REG_FCINTR0 0x01ec
  369. #define REG_FCINTR1 0x01ed
  370. #define REG_FCINTR2 0x01ee
  371. #define REG_FCINTR3 0x01ef
  372. #define REG_FCINTR4 0x01f0
  373. #define REG_FCINTR5 0x01f1
  374. #define REG_FCINTR6 0x01f2
  375. #define REG_FCINTR7 0x01f3
  376. /* TDM Low Latency, default value: 0x20 */
  377. #define REG_TDMLLCTL 0x01fc
  378. #define MSK_TDMLLCTL_TRX_LL_SEL_MANUAL 0xc0
  379. #define MSK_TDMLLCTL_TRX_LL_SEL_MODE 0x30
  380. #define MSK_TDMLLCTL_TTX_LL_SEL_MANUAL 0x0c
  381. #define BIT_TDMLLCTL_TTX_LL_TIE_LOW BIT(1)
  382. #define BIT_TDMLLCTL_TTX_LL_SEL_MODE BIT(0)
  383. /* TMDS 0 Clock Control, default value: 0x10 */
  384. #define REG_TMDS0_CCTRL1 0x0210
  385. #define MSK_TMDS0_CCTRL1_TEST_SEL 0xc0
  386. #define MSK_TMDS0_CCTRL1_CLK1X_CTL 0x30
  387. /* TMDS Clock Enable, default value: 0x00 */
  388. #define REG_TMDS_CLK_EN 0x0211
  389. #define BIT_TMDS_CLK_EN_CLK_EN BIT(0)
  390. /* TMDS Channel Enable, default value: 0x00 */
  391. #define REG_TMDS_CH_EN 0x0212
  392. #define BIT_TMDS_CH_EN_CH0_EN BIT(4)
  393. #define BIT_TMDS_CH_EN_CH12_EN BIT(0)
  394. /* BGR_BIAS, default value: 0x07 */
  395. #define REG_BGR_BIAS 0x0215
  396. #define BIT_BGR_BIAS_BGR_EN BIT(7)
  397. #define MSK_BGR_BIAS_BIAS_BGR_D 0x0f
  398. /* TMDS 0 Digital I2C BW, default value: 0x0a */
  399. #define REG_ALICE0_BW_I2C 0x0231
  400. /* TMDS 0 Digital Zone Control, default value: 0xe0 */
  401. #define REG_ALICE0_ZONE_CTRL 0x024c
  402. #define BIT_ALICE0_ZONE_CTRL_ICRST_N BIT(7)
  403. #define BIT_ALICE0_ZONE_CTRL_USE_INT_DIV20 BIT(6)
  404. #define MSK_ALICE0_ZONE_CTRL_SZONE_I2C 0x30
  405. #define MSK_ALICE0_ZONE_CTRL_ZONE_CTRL 0x0f
  406. /* TMDS 0 Digital PLL Mode Control, default value: 0x00 */
  407. #define REG_ALICE0_MODE_CTRL 0x024d
  408. #define MSK_ALICE0_MODE_CTRL_PLL_MODE_I2C 0x0c
  409. #define MSK_ALICE0_MODE_CTRL_DIV20_CTRL 0x03
  410. /* MHL Tx Control 6th, default value: 0xa0 */
  411. #define REG_MHLTX_CTL6 0x0285
  412. #define MSK_MHLTX_CTL6_EMI_SEL 0xe0
  413. #define MSK_MHLTX_CTL6_TX_CLK_SHAPE_9_8 0x03
  414. /* Packet Filter0, default value: 0x00 */
  415. #define REG_PKT_FILTER_0 0x0290
  416. #define BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT BIT(7)
  417. #define BIT_PKT_FILTER_0_DROP_CEA_CP_PKT BIT(6)
  418. #define BIT_PKT_FILTER_0_DROP_MPEG_PKT BIT(5)
  419. #define BIT_PKT_FILTER_0_DROP_SPIF_PKT BIT(4)
  420. #define BIT_PKT_FILTER_0_DROP_AIF_PKT BIT(3)
  421. #define BIT_PKT_FILTER_0_DROP_AVI_PKT BIT(2)
  422. #define BIT_PKT_FILTER_0_DROP_CTS_PKT BIT(1)
  423. #define BIT_PKT_FILTER_0_DROP_GCP_PKT BIT(0)
  424. /* Packet Filter1, default value: 0x00 */
  425. #define REG_PKT_FILTER_1 0x0291
  426. #define BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS BIT(7)
  427. #define BIT_PKT_FILTER_1_AVI_OVERRIDE_DIS BIT(6)
  428. #define BIT_PKT_FILTER_1_DROP_AUDIO_PKT BIT(3)
  429. #define BIT_PKT_FILTER_1_DROP_GEN2_PKT BIT(2)
  430. #define BIT_PKT_FILTER_1_DROP_GEN_PKT BIT(1)
  431. #define BIT_PKT_FILTER_1_DROP_VSIF_PKT BIT(0)
  432. /* TMDS Clock Status, default value: 0x10 */
  433. #define REG_TMDS_CSTAT_P3 0x02a0
  434. #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_CLR_MUTE BIT(7)
  435. #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_SET_MUTE BIT(6)
  436. #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP BIT(5)
  437. #define BIT_TMDS_CSTAT_P3_CLR_AVI BIT(3)
  438. #define BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS BIT(2)
  439. #define BIT_TMDS_CSTAT_P3_SCDT BIT(1)
  440. #define BIT_TMDS_CSTAT_P3_CKDT BIT(0)
  441. /* RX_HDMI Control, default value: 0x10 */
  442. #define REG_RX_HDMI_CTRL0 0x02a1
  443. #define BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC BIT(5)
  444. #define BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR BIT(4)
  445. #define BIT_RX_HDMI_CTRL0_HDMI_MODE_SW_VALUE BIT(3)
  446. #define BIT_RX_HDMI_CTRL0_HDMI_MODE_OVERWRITE BIT(2)
  447. #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN BIT(1)
  448. #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE BIT(0)
  449. /* RX_HDMI Control, default value: 0x38 */
  450. #define REG_RX_HDMI_CTRL2 0x02a3
  451. #define MSK_RX_HDMI_CTRL2_IDLE_CNT 0xf0
  452. #define VAL_RX_HDMI_CTRL2_IDLE_CNT(n) ((n) << 4)
  453. #define BIT_RX_HDMI_CTRL2_USE_AV_MUTE BIT(3)
  454. #define BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI BIT(0)
  455. /* RX_HDMI Control, default value: 0x0f */
  456. #define REG_RX_HDMI_CTRL3 0x02a4
  457. #define MSK_RX_HDMI_CTRL3_PP_MODE_CLK_EN 0x0f
  458. /* rx_hdmi Clear Buffer, default value: 0x00 */
  459. #define REG_RX_HDMI_CLR_BUFFER 0x02ac
  460. #define MSK_RX_HDMI_CLR_BUFFER_AIF4VSI_CMP 0xc0
  461. #define BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI BIT(5)
  462. #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI BIT(4)
  463. #define BIT_RX_HDMI_CLR_BUFFER_VSI_IEEE_ID_CHK_EN BIT(3)
  464. #define BIT_RX_HDMI_CLR_BUFFER_SWAP_VSI_IEEE_ID BIT(2)
  465. #define BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN BIT(1)
  466. #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN BIT(0)
  467. /* RX_HDMI VSI Header1, default value: 0x00 */
  468. #define REG_RX_HDMI_MON_PKT_HEADER1 0x02b8
  469. /* RX_HDMI VSI MHL Monitor, default value: 0x3c */
  470. #define REG_RX_HDMI_VSIF_MHL_MON 0x02d7
  471. #define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_3D_FORMAT 0x3c
  472. #define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_VID_FORMAT 0x03
  473. /* Interrupt Source 9, default value: 0x00 */
  474. #define REG_INTR9 0x02e0
  475. #define BIT_INTR9_EDID_ERROR BIT(6)
  476. #define BIT_INTR9_EDID_DONE BIT(5)
  477. #define BIT_INTR9_DEVCAP_DONE BIT(4)
  478. /* Interrupt 9 Mask, default value: 0x00 */
  479. #define REG_INTR9_MASK 0x02e1
  480. /* TPI CBUS Start, default value: 0x00 */
  481. #define REG_TPI_CBUS_START 0x02e2
  482. #define BIT_TPI_CBUS_START_RCP_REQ_START BIT(7)
  483. #define BIT_TPI_CBUS_START_RCPK_REPLY_START BIT(6)
  484. #define BIT_TPI_CBUS_START_RCPE_REPLY_START BIT(5)
  485. #define BIT_TPI_CBUS_START_PUT_LINK_MODE_START BIT(4)
  486. #define BIT_TPI_CBUS_START_PUT_DCAPCHG_START BIT(3)
  487. #define BIT_TPI_CBUS_START_PUT_DCAPRDY_START BIT(2)
  488. #define BIT_TPI_CBUS_START_GET_EDID_START_0 BIT(1)
  489. #define BIT_TPI_CBUS_START_GET_DEVCAP_START BIT(0)
  490. /* EDID Control, default value: 0x10 */
  491. #define REG_EDID_CTRL 0x02e3
  492. #define BIT_EDID_CTRL_EDID_PRIME_VALID BIT(7)
  493. #define BIT_EDID_CTRL_XDEVCAP_EN BIT(6)
  494. #define BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP BIT(5)
  495. #define BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO BIT(4)
  496. #define BIT_EDID_CTRL_EDID_FIFO_ACCESS_ALWAYS_EN BIT(3)
  497. #define BIT_EDID_CTRL_EDID_FIFO_BLOCK_SEL BIT(2)
  498. #define BIT_EDID_CTRL_INVALID_BKSV BIT(1)
  499. #define BIT_EDID_CTRL_EDID_MODE_EN BIT(0)
  500. /* EDID FIFO Addr, default value: 0x00 */
  501. #define REG_EDID_FIFO_ADDR 0x02e9
  502. /* EDID FIFO Write Data, default value: 0x00 */
  503. #define REG_EDID_FIFO_WR_DATA 0x02ea
  504. /* EDID/DEVCAP FIFO Internal Addr, default value: 0x00 */
  505. #define REG_EDID_FIFO_ADDR_MON 0x02eb
  506. /* EDID FIFO Read Data, default value: 0x00 */
  507. #define REG_EDID_FIFO_RD_DATA 0x02ec
  508. /* EDID DDC Segment Pointer, default value: 0x00 */
  509. #define REG_EDID_START_EXT 0x02ed
  510. /* TX IP BIST CNTL and Status, default value: 0x00 */
  511. #define REG_TX_IP_BIST_CNTLSTA 0x02f2
  512. #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_QUARTER_CLK_SEL BIT(6)
  513. #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE BIT(5)
  514. #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON BIT(4)
  515. #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_RUN BIT(3)
  516. #define BIT_TX_IP_BIST_CNTLSTA_TXCLK_HALF_SEL BIT(2)
  517. #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN BIT(1)
  518. #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_SEL BIT(0)
  519. /* TX IP BIST INST LOW, default value: 0x00 */
  520. #define REG_TX_IP_BIST_INST_LOW 0x02f3
  521. #define REG_TX_IP_BIST_INST_HIGH 0x02f4
  522. /* TX IP BIST PATTERN LOW, default value: 0x00 */
  523. #define REG_TX_IP_BIST_PAT_LOW 0x02f5
  524. #define REG_TX_IP_BIST_PAT_HIGH 0x02f6
  525. /* TX IP BIST CONFIGURE LOW, default value: 0x00 */
  526. #define REG_TX_IP_BIST_CONF_LOW 0x02f7
  527. #define REG_TX_IP_BIST_CONF_HIGH 0x02f8
  528. /* E-MSC General Control, default value: 0x80 */
  529. #define REG_GENCTL 0x0300
  530. #define BIT_GENCTL_SPEC_TRANS_DIS BIT(7)
  531. #define BIT_GENCTL_DIS_XMIT_ERR_STATE BIT(6)
  532. #define BIT_GENCTL_SPI_MISO_EDGE BIT(5)
  533. #define BIT_GENCTL_SPI_MOSI_EDGE BIT(4)
  534. #define BIT_GENCTL_CLR_EMSC_RFIFO BIT(3)
  535. #define BIT_GENCTL_CLR_EMSC_XFIFO BIT(2)
  536. #define BIT_GENCTL_START_TRAIN_SEQ BIT(1)
  537. #define BIT_GENCTL_EMSC_EN BIT(0)
  538. /* E-MSC Comma ErrorCNT, default value: 0x03 */
  539. #define REG_COMMECNT 0x0305
  540. #define BIT_COMMECNT_I2C_TO_EMSC_EN BIT(7)
  541. #define MSK_COMMECNT_COMMA_CHAR_ERR_CNT 0x0f
  542. /* E-MSC RFIFO ByteCnt, default value: 0x00 */
  543. #define REG_EMSCRFIFOBCNTL 0x031a
  544. #define REG_EMSCRFIFOBCNTH 0x031b
  545. /* SPI Burst Cnt Status, default value: 0x00 */
  546. #define REG_SPIBURSTCNT 0x031e
  547. /* SPI Burst Status and SWRST, default value: 0x00 */
  548. #define REG_SPIBURSTSTAT 0x0322
  549. #define BIT_SPIBURSTSTAT_SPI_HDCPRST BIT(7)
  550. #define BIT_SPIBURSTSTAT_SPI_CBUSRST BIT(6)
  551. #define BIT_SPIBURSTSTAT_SPI_SRST BIT(5)
  552. #define BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE BIT(0)
  553. /* E-MSC 1st Interrupt, default value: 0x00 */
  554. #define REG_EMSCINTR 0x0323
  555. #define BIT_EMSCINTR_EMSC_XFIFO_EMPTY BIT(7)
  556. #define BIT_EMSCINTR_EMSC_XMIT_ACK_TOUT BIT(6)
  557. #define BIT_EMSCINTR_EMSC_RFIFO_READ_ERR BIT(5)
  558. #define BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR BIT(4)
  559. #define BIT_EMSCINTR_EMSC_COMMA_CHAR_ERR BIT(3)
  560. #define BIT_EMSCINTR_EMSC_XMIT_DONE BIT(2)
  561. #define BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT BIT(1)
  562. #define BIT_EMSCINTR_SPI_DVLD BIT(0)
  563. /* E-MSC Interrupt Mask, default value: 0x00 */
  564. #define REG_EMSCINTRMASK 0x0324
  565. /* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
  566. #define REG_EMSC_XMIT_WRITE_PORT 0x032a
  567. /* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
  568. #define REG_EMSC_RCV_READ_PORT 0x032b
  569. /* E-MSC 2nd Interrupt, default value: 0x00 */
  570. #define REG_EMSCINTR1 0x032c
  571. #define BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR BIT(0)
  572. /* E-MSC Interrupt Mask, default value: 0x00 */
  573. #define REG_EMSCINTRMASK1 0x032d
  574. #define BIT_EMSCINTRMASK1_EMSC_INTRMASK1_0 BIT(0)
  575. /* MHL Top Ctl, default value: 0x00 */
  576. #define REG_MHL_TOP_CTL 0x0330
  577. #define BIT_MHL_TOP_CTL_MHL3_DOC_SEL BIT(7)
  578. #define BIT_MHL_TOP_CTL_MHL_PP_SEL BIT(6)
  579. #define MSK_MHL_TOP_CTL_IF_TIMING_CTL 0x03
  580. /* MHL DataPath 1st Ctl, default value: 0xbc */
  581. #define REG_MHL_DP_CTL0 0x0331
  582. #define BIT_MHL_DP_CTL0_DP_OE BIT(7)
  583. #define BIT_MHL_DP_CTL0_TX_OE_OVR BIT(6)
  584. #define MSK_MHL_DP_CTL0_TX_OE 0x3f
  585. /* MHL DataPath 2nd Ctl, default value: 0xbb */
  586. #define REG_MHL_DP_CTL1 0x0332
  587. #define MSK_MHL_DP_CTL1_CK_SWING_CTL 0xf0
  588. #define MSK_MHL_DP_CTL1_DT_SWING_CTL 0x0f
  589. /* MHL DataPath 3rd Ctl, default value: 0x2f */
  590. #define REG_MHL_DP_CTL2 0x0333
  591. #define BIT_MHL_DP_CTL2_CLK_BYPASS_EN BIT(7)
  592. #define MSK_MHL_DP_CTL2_DAMP_TERM_SEL 0x30
  593. #define MSK_MHL_DP_CTL2_CK_TERM_SEL 0x0c
  594. #define MSK_MHL_DP_CTL2_DT_TERM_SEL 0x03
  595. /* MHL DataPath 4th Ctl, default value: 0x48 */
  596. #define REG_MHL_DP_CTL3 0x0334
  597. #define MSK_MHL_DP_CTL3_DT_DRV_VNBC_CTL 0xf0
  598. #define MSK_MHL_DP_CTL3_DT_DRV_VNB_CTL 0x0f
  599. /* MHL DataPath 5th Ctl, default value: 0x48 */
  600. #define REG_MHL_DP_CTL4 0x0335
  601. #define MSK_MHL_DP_CTL4_CK_DRV_VNBC_CTL 0xf0
  602. #define MSK_MHL_DP_CTL4_CK_DRV_VNB_CTL 0x0f
  603. /* MHL DataPath 6th Ctl, default value: 0x3f */
  604. #define REG_MHL_DP_CTL5 0x0336
  605. #define BIT_MHL_DP_CTL5_RSEN_EN_OVR BIT(7)
  606. #define BIT_MHL_DP_CTL5_RSEN_EN BIT(6)
  607. #define MSK_MHL_DP_CTL5_DAMP_TERM_VGS_CTL 0x30
  608. #define MSK_MHL_DP_CTL5_CK_TERM_VGS_CTL 0x0c
  609. #define MSK_MHL_DP_CTL5_DT_TERM_VGS_CTL 0x03
  610. /* MHL PLL 1st Ctl, default value: 0x05 */
  611. #define REG_MHL_PLL_CTL0 0x0337
  612. #define BIT_MHL_PLL_CTL0_AUD_CLK_EN BIT(7)
  613. #define MSK_MHL_PLL_CTL0_AUD_CLK_RATIO 0x70
  614. #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_10 0x70
  615. #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_6 0x60
  616. #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_4 0x50
  617. #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2 0x40
  618. #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 0x30
  619. #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_3 0x20
  620. #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2_PRIME 0x10
  621. #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_1 0x00
  622. #define MSK_MHL_PLL_CTL0_HDMI_CLK_RATIO 0x0c
  623. #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_4X 0x0c
  624. #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_2X 0x08
  625. #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 0x04
  626. #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_HALF_X 0x00
  627. #define BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL BIT(1)
  628. #define BIT_MHL_PLL_CTL0_ZONE_MASK_OE BIT(0)
  629. /* MHL PLL 3rd Ctl, default value: 0x80 */
  630. #define REG_MHL_PLL_CTL2 0x0339
  631. #define BIT_MHL_PLL_CTL2_CLKDETECT_EN BIT(7)
  632. #define BIT_MHL_PLL_CTL2_MEAS_FVCO BIT(3)
  633. #define BIT_MHL_PLL_CTL2_PLL_FAST_LOCK BIT(2)
  634. #define MSK_MHL_PLL_CTL2_PLL_LF_SEL 0x03
  635. /* MHL CBUS 1st Ctl, default value: 0x12 */
  636. #define REG_MHL_CBUS_CTL0 0x0340
  637. #define BIT_MHL_CBUS_CTL0_CBUS_RGND_TEST_MODE BIT(7)
  638. #define MSK_MHL_CBUS_CTL0_CBUS_RGND_VTH_CTL 0x30
  639. #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734 0x00
  640. #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_747 0x10
  641. #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_740 0x20
  642. #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_754 0x30
  643. #define MSK_MHL_CBUS_CTL0_CBUS_RES_TEST_SEL 0x0c
  644. #define MSK_MHL_CBUS_CTL0_CBUS_DRV_SEL 0x03
  645. #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAKEST 0x00
  646. #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAK 0x01
  647. #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 0x02
  648. #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONGEST 0x03
  649. /* MHL CBUS 2nd Ctl, default value: 0x03 */
  650. #define REG_MHL_CBUS_CTL1 0x0341
  651. #define MSK_MHL_CBUS_CTL1_CBUS_RGND_RES_CTL 0x07
  652. #define VAL_MHL_CBUS_CTL1_0888_OHM 0x00
  653. #define VAL_MHL_CBUS_CTL1_1115_OHM 0x04
  654. #define VAL_MHL_CBUS_CTL1_1378_OHM 0x07
  655. /* MHL CoC 1st Ctl, default value: 0xc3 */
  656. #define REG_MHL_COC_CTL0 0x0342
  657. #define BIT_MHL_COC_CTL0_COC_BIAS_EN BIT(7)
  658. #define MSK_MHL_COC_CTL0_COC_BIAS_CTL 0x70
  659. #define MSK_MHL_COC_CTL0_COC_TERM_CTL 0x07
  660. /* MHL CoC 2nd Ctl, default value: 0x87 */
  661. #define REG_MHL_COC_CTL1 0x0343
  662. #define BIT_MHL_COC_CTL1_COC_EN BIT(7)
  663. #define MSK_MHL_COC_CTL1_COC_DRV_CTL 0x3f
  664. /* MHL CoC 4th Ctl, default value: 0x00 */
  665. #define REG_MHL_COC_CTL3 0x0345
  666. #define BIT_MHL_COC_CTL3_COC_AECHO_EN BIT(0)
  667. /* MHL CoC 5th Ctl, default value: 0x28 */
  668. #define REG_MHL_COC_CTL4 0x0346
  669. #define MSK_MHL_COC_CTL4_COC_IF_CTL 0xf0
  670. #define MSK_MHL_COC_CTL4_COC_SLEW_CTL 0x0f
  671. /* MHL CoC 6th Ctl, default value: 0x0d */
  672. #define REG_MHL_COC_CTL5 0x0347
  673. /* MHL DoC 1st Ctl, default value: 0x18 */
  674. #define REG_MHL_DOC_CTL0 0x0349
  675. #define BIT_MHL_DOC_CTL0_DOC_RXDATA_EN BIT(7)
  676. #define MSK_MHL_DOC_CTL0_DOC_DM_TERM 0x38
  677. #define MSK_MHL_DOC_CTL0_DOC_OPMODE 0x06
  678. #define BIT_MHL_DOC_CTL0_DOC_RXBIAS_EN BIT(0)
  679. /* MHL DataPath 7th Ctl, default value: 0x2a */
  680. #define REG_MHL_DP_CTL6 0x0350
  681. #define BIT_MHL_DP_CTL6_DP_TAP2_SGN BIT(5)
  682. #define BIT_MHL_DP_CTL6_DP_TAP2_EN BIT(4)
  683. #define BIT_MHL_DP_CTL6_DP_TAP1_SGN BIT(3)
  684. #define BIT_MHL_DP_CTL6_DP_TAP1_EN BIT(2)
  685. #define BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN BIT(1)
  686. #define BIT_MHL_DP_CTL6_DP_PRE_POST_SEL BIT(0)
  687. /* MHL DataPath 8th Ctl, default value: 0x06 */
  688. #define REG_MHL_DP_CTL7 0x0351
  689. #define MSK_MHL_DP_CTL7_DT_DRV_VBIAS_CASCTL 0xf0
  690. #define MSK_MHL_DP_CTL7_DT_DRV_IREF_CTL 0x0f
  691. #define REG_MHL_DP_CTL8 0x0352
  692. /* Tx Zone Ctl1, default value: 0x00 */
  693. #define REG_TX_ZONE_CTL1 0x0361
  694. #define VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE 0x08
  695. /* MHL3 Tx Zone Ctl, default value: 0x00 */
  696. #define REG_MHL3_TX_ZONE_CTL 0x0364
  697. #define BIT_MHL3_TX_ZONE_CTL_MHL2_INTPLT_ZONE_MANU_EN BIT(7)
  698. #define MSK_MHL3_TX_ZONE_CTL_MHL3_TX_ZONE 0x03
  699. #define MSK_TX_ZONE_CTL3_TX_ZONE 0x03
  700. #define VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS 0x00
  701. #define VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS 0x01
  702. #define VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS 0x02
  703. /* HDCP Polling Control and Status, default value: 0x70 */
  704. #define REG_HDCP2X_POLL_CS 0x0391
  705. #define BIT_HDCP2X_POLL_CS_HDCP2X_MSG_SZ_CLR_OPTION BIT(6)
  706. #define BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION BIT(5)
  707. #define BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION BIT(4)
  708. #define MSK_HDCP2X_POLL_CS_ 0x0c
  709. #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT BIT(1)
  710. #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_EN BIT(0)
  711. /* HDCP Interrupt 0, default value: 0x00 */
  712. #define REG_HDCP2X_INTR0 0x0398
  713. /* HDCP Interrupt 0 Mask, default value: 0x00 */
  714. #define REG_HDCP2X_INTR0_MASK 0x0399
  715. /* HDCP General Control 0, default value: 0x02 */
  716. #define REG_HDCP2X_CTRL_0 0x03a0
  717. #define BIT_HDCP2X_CTRL_0_HDCP2X_ENCRYPT_EN BIT(7)
  718. #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_SEL BIT(6)
  719. #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR BIT(5)
  720. #define BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE BIT(4)
  721. #define BIT_HDCP2X_CTRL_0_HDCP2X_HDMIMODE BIT(3)
  722. #define BIT_HDCP2X_CTRL_0_HDCP2X_REPEATER BIT(2)
  723. #define BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX BIT(1)
  724. #define BIT_HDCP2X_CTRL_0_HDCP2X_EN BIT(0)
  725. /* HDCP General Control 1, default value: 0x08 */
  726. #define REG_HDCP2X_CTRL_1 0x03a1
  727. #define MSK_HDCP2X_CTRL_1_HDCP2X_REAUTH_MSK_3_0 0xf0
  728. #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_SW BIT(3)
  729. #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_OVR BIT(2)
  730. #define BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK BIT(1)
  731. #define BIT_HDCP2X_CTRL_1_HDCP2X_REAUTH_SW BIT(0)
  732. /* HDCP Misc Control, default value: 0x00 */
  733. #define REG_HDCP2X_MISC_CTRL 0x03a5
  734. #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START BIT(4)
  735. #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR_START BIT(3)
  736. #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR BIT(2)
  737. #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START BIT(1)
  738. #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD BIT(0)
  739. /* HDCP RPT SMNG K, default value: 0x00 */
  740. #define REG_HDCP2X_RPT_SMNG_K 0x03a6
  741. /* HDCP RPT SMNG In, default value: 0x00 */
  742. #define REG_HDCP2X_RPT_SMNG_IN 0x03a7
  743. /* HDCP Auth Status, default value: 0x00 */
  744. #define REG_HDCP2X_AUTH_STAT 0x03aa
  745. /* HDCP RPT RCVID Out, default value: 0x00 */
  746. #define REG_HDCP2X_RPT_RCVID_OUT 0x03ac
  747. /* HDCP TP1, default value: 0x62 */
  748. #define REG_HDCP2X_TP1 0x03b4
  749. /* HDCP GP Out 0, default value: 0x00 */
  750. #define REG_HDCP2X_GP_OUT0 0x03c7
  751. /* HDCP Repeater RCVR ID 0, default value: 0x00 */
  752. #define REG_HDCP2X_RPT_RCVR_ID0 0x03d1
  753. /* HDCP DDCM Status, default value: 0x00 */
  754. #define REG_HDCP2X_DDCM_STS 0x03d8
  755. #define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_ERR_STS_3_0 0xf0
  756. #define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_CTL_CS_3_0 0x0f
  757. /* HDMI2MHL3 Control, default value: 0x0a */
  758. #define REG_M3_CTRL 0x03e0
  759. #define BIT_M3_CTRL_H2M_SWRST BIT(4)
  760. #define BIT_M3_CTRL_SW_MHL3_SEL BIT(3)
  761. #define BIT_M3_CTRL_M3AV_EN BIT(2)
  762. #define BIT_M3_CTRL_ENC_TMDS BIT(1)
  763. #define BIT_M3_CTRL_MHL3_MASTER_EN BIT(0)
  764. #define VAL_M3_CTRL_MHL1_2_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \
  765. | BIT_M3_CTRL_ENC_TMDS)
  766. #define VAL_M3_CTRL_MHL3_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \
  767. | BIT_M3_CTRL_M3AV_EN \
  768. | BIT_M3_CTRL_ENC_TMDS \
  769. | BIT_M3_CTRL_MHL3_MASTER_EN)
  770. /* HDMI2MHL3 Port0 Control, default value: 0x04 */
  771. #define REG_M3_P0CTRL 0x03e1
  772. #define BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN BIT(4)
  773. #define BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN BIT(3)
  774. #define BIT_M3_P0CTRL_MHL3_P0_HDCP_EN BIT(2)
  775. #define BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED BIT(1)
  776. #define BIT_M3_P0CTRL_MHL3_P0_PORT_EN BIT(0)
  777. #define REG_M3_POSTM 0x03e2
  778. #define MSK_M3_POSTM_RRP_DECODE 0xf8
  779. #define MSK_M3_POSTM_MHL3_P0_STM_ID 0x07
  780. /* HDMI2MHL3 Scramble Control, default value: 0x41 */
  781. #define REG_M3_SCTRL 0x03e6
  782. #define MSK_M3_SCTRL_MHL3_SR_LENGTH 0xf0
  783. #define BIT_M3_SCTRL_MHL3_SCRAMBLER_EN BIT(0)
  784. /* HSIC Div Ctl, default value: 0x05 */
  785. #define REG_DIV_CTL_MAIN 0x03f2
  786. #define MSK_DIV_CTL_MAIN_PRE_DIV_CTL_MAIN 0x1c
  787. #define MSK_DIV_CTL_MAIN_FB_DIV_CTL_MAIN 0x03
  788. /* MHL Capability 1st Byte, default value: 0x00 */
  789. #define REG_MHL_DEVCAP_0 0x0400
  790. /* MHL Interrupt 1st Byte, default value: 0x00 */
  791. #define REG_MHL_INT_0 0x0420
  792. /* Device Status 1st byte, default value: 0x00 */
  793. #define REG_MHL_STAT_0 0x0430
  794. /* CBUS Scratch Pad 1st Byte, default value: 0x00 */
  795. #define REG_MHL_SCRPAD_0 0x0440
  796. /* MHL Extended Capability 1st Byte, default value: 0x00 */
  797. #define REG_MHL_EXTDEVCAP_0 0x0480
  798. /* Device Extended Status 1st byte, default value: 0x00 */
  799. #define REG_MHL_EXTSTAT_0 0x0490
  800. /* TPI DTD Byte2, default value: 0x00 */
  801. #define REG_TPI_DTD_B2 0x0602
  802. #define VAL_TPI_QUAN_RANGE_LIMITED 0x01
  803. #define VAL_TPI_QUAN_RANGE_FULL 0x02
  804. #define VAL_TPI_FORMAT_RGB 0x00
  805. #define VAL_TPI_FORMAT_YCBCR444 0x01
  806. #define VAL_TPI_FORMAT_YCBCR422 0x02
  807. #define VAL_TPI_FORMAT_INTERNAL_RGB 0x03
  808. #define VAL_TPI_FORMAT(_fmt, _qr) \
  809. (VAL_TPI_FORMAT_##_fmt | (VAL_TPI_QUAN_RANGE_##_qr << 2))
  810. /* Input Format, default value: 0x00 */
  811. #define REG_TPI_INPUT 0x0609
  812. #define BIT_TPI_INPUT_EXTENDEDBITMODE BIT(7)
  813. #define BIT_TPI_INPUT_ENDITHER BIT(6)
  814. #define MSK_TPI_INPUT_INPUT_QUAN_RANGE 0x0c
  815. #define MSK_TPI_INPUT_INPUT_FORMAT 0x03
  816. /* Output Format, default value: 0x00 */
  817. #define REG_TPI_OUTPUT 0x060a
  818. #define BIT_TPI_OUTPUT_CSCMODE709 BIT(4)
  819. #define MSK_TPI_OUTPUT_OUTPUT_QUAN_RANGE 0x0c
  820. #define MSK_TPI_OUTPUT_OUTPUT_FORMAT 0x03
  821. /* TPI AVI Check Sum, default value: 0x00 */
  822. #define REG_TPI_AVI_CHSUM 0x060c
  823. /* TPI System Control, default value: 0x00 */
  824. #define REG_TPI_SC 0x061a
  825. #define BIT_TPI_SC_TPI_UPDATE_FLG BIT(7)
  826. #define BIT_TPI_SC_TPI_REAUTH_CTL BIT(6)
  827. #define BIT_TPI_SC_TPI_OUTPUT_MODE_1 BIT(5)
  828. #define BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN BIT(4)
  829. #define BIT_TPI_SC_TPI_AV_MUTE BIT(3)
  830. #define BIT_TPI_SC_DDC_GPU_REQUEST BIT(2)
  831. #define BIT_TPI_SC_DDC_TPI_SW BIT(1)
  832. #define BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI BIT(0)
  833. /* TPI COPP Query Data, default value: 0x00 */
  834. #define REG_TPI_COPP_DATA1 0x0629
  835. #define BIT_TPI_COPP_DATA1_COPP_GPROT BIT(7)
  836. #define BIT_TPI_COPP_DATA1_COPP_LPROT BIT(6)
  837. #define MSK_TPI_COPP_DATA1_COPP_LINK_STATUS 0x30
  838. #define VAL_TPI_COPP_LINK_STATUS_NORMAL 0x00
  839. #define VAL_TPI_COPP_LINK_STATUS_LINK_LOST 0x10
  840. #define VAL_TPI_COPP_LINK_STATUS_RENEGOTIATION_REQ 0x20
  841. #define VAL_TPI_COPP_LINK_STATUS_LINK_SUSPENDED 0x30
  842. #define BIT_TPI_COPP_DATA1_COPP_HDCP_REP BIT(3)
  843. #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_0 BIT(2)
  844. #define BIT_TPI_COPP_DATA1_COPP_PROTYPE BIT(1)
  845. #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_1 BIT(0)
  846. /* TPI COPP Control Data, default value: 0x00 */
  847. #define REG_TPI_COPP_DATA2 0x062a
  848. #define BIT_TPI_COPP_DATA2_INTR_ENCRYPTION BIT(5)
  849. #define BIT_TPI_COPP_DATA2_KSV_FORWARD BIT(4)
  850. #define BIT_TPI_COPP_DATA2_INTERM_RI_CHECK_EN BIT(3)
  851. #define BIT_TPI_COPP_DATA2_DOUBLE_RI_CHECK BIT(2)
  852. #define BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD BIT(1)
  853. #define BIT_TPI_COPP_DATA2_COPP_PROTLEVEL BIT(0)
  854. /* TPI Interrupt Enable, default value: 0x00 */
  855. #define REG_TPI_INTR_EN 0x063c
  856. /* TPI Interrupt Status Low Byte, default value: 0x00 */
  857. #define REG_TPI_INTR_ST0 0x063d
  858. #define BIT_TPI_INTR_ST0_TPI_AUTH_CHNGE_STAT BIT(7)
  859. #define BIT_TPI_INTR_ST0_TPI_V_RDY_STAT BIT(6)
  860. #define BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT BIT(5)
  861. #define BIT_TPI_INTR_ST0_KSV_FIFO_FIRST_STAT BIT(3)
  862. #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_DONE_STAT BIT(2)
  863. #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT BIT(1)
  864. #define BIT_TPI_INTR_ST0_READ_BKSV_ERR_STAT BIT(0)
  865. /* TPI DS BCAPS Status, default value: 0x00 */
  866. #define REG_TPI_DS_BCAPS 0x0644
  867. /* TPI BStatus1, default value: 0x00 */
  868. #define REG_TPI_BSTATUS1 0x0645
  869. #define BIT_TPI_BSTATUS1_DS_DEV_EXCEED BIT(7)
  870. #define MSK_TPI_BSTATUS1_DS_DEV_CNT 0x7f
  871. /* TPI BStatus2, default value: 0x10 */
  872. #define REG_TPI_BSTATUS2 0x0646
  873. #define MSK_TPI_BSTATUS2_DS_BSTATUS 0xe0
  874. #define BIT_TPI_BSTATUS2_DS_HDMI_MODE BIT(4)
  875. #define BIT_TPI_BSTATUS2_DS_CASC_EXCEED BIT(3)
  876. #define MSK_TPI_BSTATUS2_DS_DEPTH 0x07
  877. /* TPI HW Optimization Control #3, default value: 0x00 */
  878. #define REG_TPI_HW_OPT3 0x06bb
  879. #define BIT_TPI_HW_OPT3_DDC_DEBUG BIT(7)
  880. #define BIT_TPI_HW_OPT3_RI_CHECK_SKIP BIT(3)
  881. #define BIT_TPI_HW_OPT3_TPI_DDC_BURST_MODE BIT(2)
  882. #define MSK_TPI_HW_OPT3_TPI_DDC_REQ_LEVEL 0x03
  883. /* TPI Info Frame Select, default value: 0x00 */
  884. #define REG_TPI_INFO_FSEL 0x06bf
  885. #define BIT_TPI_INFO_FSEL_EN BIT(7)
  886. #define BIT_TPI_INFO_FSEL_RPT BIT(6)
  887. #define BIT_TPI_INFO_FSEL_READ_FLAG BIT(5)
  888. #define MSK_TPI_INFO_FSEL_PKT 0x07
  889. #define VAL_TPI_INFO_FSEL_AVI 0x00
  890. #define VAL_TPI_INFO_FSEL_SPD 0x01
  891. #define VAL_TPI_INFO_FSEL_AUD 0x02
  892. #define VAL_TPI_INFO_FSEL_MPG 0x03
  893. #define VAL_TPI_INFO_FSEL_GEN 0x04
  894. #define VAL_TPI_INFO_FSEL_GEN2 0x05
  895. #define VAL_TPI_INFO_FSEL_VSI 0x06
  896. /* TPI Info Byte #0, default value: 0x00 */
  897. #define REG_TPI_INFO_B0 0x06c0
  898. /* CoC Status, default value: 0x00 */
  899. #define REG_COC_STAT_0 0x0700
  900. #define BIT_COC_STAT_0_PLL_LOCKED BIT(7)
  901. #define MSK_COC_STAT_0_FSM_STATE 0x0f
  902. #define REG_COC_STAT_1 0x0701
  903. #define REG_COC_STAT_2 0x0702
  904. #define REG_COC_STAT_3 0x0703
  905. #define REG_COC_STAT_4 0x0704
  906. #define REG_COC_STAT_5 0x0705
  907. /* CoC 1st Ctl, default value: 0x40 */
  908. #define REG_COC_CTL0 0x0710
  909. /* CoC 2nd Ctl, default value: 0x0a */
  910. #define REG_COC_CTL1 0x0711
  911. #define MSK_COC_CTL1_COC_CTRL1_7_6 0xc0
  912. #define MSK_COC_CTL1_COC_CTRL1_5_0 0x3f
  913. /* CoC 3rd Ctl, default value: 0x14 */
  914. #define REG_COC_CTL2 0x0712
  915. #define MSK_COC_CTL2_COC_CTRL2_7_6 0xc0
  916. #define MSK_COC_CTL2_COC_CTRL2_5_0 0x3f
  917. /* CoC 4th Ctl, default value: 0x40 */
  918. #define REG_COC_CTL3 0x0713
  919. #define BIT_COC_CTL3_COC_CTRL3_7 BIT(7)
  920. #define MSK_COC_CTL3_COC_CTRL3_6_0 0x7f
  921. /* CoC 7th Ctl, default value: 0x00 */
  922. #define REG_COC_CTL6 0x0716
  923. #define BIT_COC_CTL6_COC_CTRL6_7 BIT(7)
  924. #define BIT_COC_CTL6_COC_CTRL6_6 BIT(6)
  925. #define MSK_COC_CTL6_COC_CTRL6_5_0 0x3f
  926. /* CoC 8th Ctl, default value: 0x06 */
  927. #define REG_COC_CTL7 0x0717
  928. #define BIT_COC_CTL7_COC_CTRL7_7 BIT(7)
  929. #define BIT_COC_CTL7_COC_CTRL7_6 BIT(6)
  930. #define BIT_COC_CTL7_COC_CTRL7_5 BIT(5)
  931. #define MSK_COC_CTL7_COC_CTRL7_4_3 0x18
  932. #define MSK_COC_CTL7_COC_CTRL7_2_0 0x07
  933. /* CoC 10th Ctl, default value: 0x00 */
  934. #define REG_COC_CTL9 0x0719
  935. /* CoC 11th Ctl, default value: 0x00 */
  936. #define REG_COC_CTLA 0x071a
  937. /* CoC 12th Ctl, default value: 0x00 */
  938. #define REG_COC_CTLB 0x071b
  939. /* CoC 13th Ctl, default value: 0x0f */
  940. #define REG_COC_CTLC 0x071c
  941. /* CoC 14th Ctl, default value: 0x0a */
  942. #define REG_COC_CTLD 0x071d
  943. #define BIT_COC_CTLD_COC_CTRLD_7 BIT(7)
  944. #define MSK_COC_CTLD_COC_CTRLD_6_0 0x7f
  945. /* CoC 15th Ctl, default value: 0x0a */
  946. #define REG_COC_CTLE 0x071e
  947. #define BIT_COC_CTLE_COC_CTRLE_7 BIT(7)
  948. #define MSK_COC_CTLE_COC_CTRLE_6_0 0x7f
  949. /* CoC 16th Ctl, default value: 0x00 */
  950. #define REG_COC_CTLF 0x071f
  951. #define MSK_COC_CTLF_COC_CTRLF_7_3 0xf8
  952. #define MSK_COC_CTLF_COC_CTRLF_2_0 0x07
  953. /* CoC 18th Ctl, default value: 0x32 */
  954. #define REG_COC_CTL11 0x0721
  955. #define MSK_COC_CTL11_COC_CTRL11_7_4 0xf0
  956. #define MSK_COC_CTL11_COC_CTRL11_3_0 0x0f
  957. /* CoC 21st Ctl, default value: 0x00 */
  958. #define REG_COC_CTL14 0x0724
  959. #define MSK_COC_CTL14_COC_CTRL14_7_4 0xf0
  960. #define MSK_COC_CTL14_COC_CTRL14_3_0 0x0f
  961. /* CoC 22nd Ctl, default value: 0x00 */
  962. #define REG_COC_CTL15 0x0725
  963. #define BIT_COC_CTL15_COC_CTRL15_7 BIT(7)
  964. #define MSK_COC_CTL15_COC_CTRL15_6_4 0x70
  965. #define MSK_COC_CTL15_COC_CTRL15_3_0 0x0f
  966. /* CoC Interrupt, default value: 0x00 */
  967. #define REG_COC_INTR 0x0726
  968. /* CoC Interrupt Mask, default value: 0x00 */
  969. #define REG_COC_INTR_MASK 0x0727
  970. #define BIT_COC_PLL_LOCK_STATUS_CHANGE BIT(0)
  971. #define BIT_COC_CALIBRATION_DONE BIT(1)
  972. /* CoC Misc Ctl, default value: 0x00 */
  973. #define REG_COC_MISC_CTL0 0x0728
  974. #define BIT_COC_MISC_CTL0_FSM_MON BIT(7)
  975. /* CoC 24th Ctl, default value: 0x00 */
  976. #define REG_COC_CTL17 0x072a
  977. #define MSK_COC_CTL17_COC_CTRL17_7_4 0xf0
  978. #define MSK_COC_CTL17_COC_CTRL17_3_0 0x0f
  979. /* CoC 25th Ctl, default value: 0x00 */
  980. #define REG_COC_CTL18 0x072b
  981. #define MSK_COC_CTL18_COC_CTRL18_7_4 0xf0
  982. #define MSK_COC_CTL18_COC_CTRL18_3_0 0x0f
  983. /* CoC 26th Ctl, default value: 0x00 */
  984. #define REG_COC_CTL19 0x072c
  985. #define MSK_COC_CTL19_COC_CTRL19_7_4 0xf0
  986. #define MSK_COC_CTL19_COC_CTRL19_3_0 0x0f
  987. /* CoC 27th Ctl, default value: 0x00 */
  988. #define REG_COC_CTL1A 0x072d
  989. #define MSK_COC_CTL1A_COC_CTRL1A_7_2 0xfc
  990. #define MSK_COC_CTL1A_COC_CTRL1A_1_0 0x03
  991. /* DoC 9th Status, default value: 0x00 */
  992. #define REG_DOC_STAT_8 0x0740
  993. /* DoC 10th Status, default value: 0x00 */
  994. #define REG_DOC_STAT_9 0x0741
  995. /* DoC 5th CFG, default value: 0x00 */
  996. #define REG_DOC_CFG4 0x074e
  997. #define MSK_DOC_CFG4_DBG_STATE_DOC_FSM 0x0f
  998. /* DoC 1st Ctl, default value: 0x40 */
  999. #define REG_DOC_CTL0 0x0751
  1000. /* DoC 7th Ctl, default value: 0x00 */
  1001. #define REG_DOC_CTL6 0x0757
  1002. #define BIT_DOC_CTL6_DOC_CTRL6_7 BIT(7)
  1003. #define BIT_DOC_CTL6_DOC_CTRL6_6 BIT(6)
  1004. #define MSK_DOC_CTL6_DOC_CTRL6_5_4 0x30
  1005. #define MSK_DOC_CTL6_DOC_CTRL6_3_0 0x0f
  1006. /* DoC 8th Ctl, default value: 0x00 */
  1007. #define REG_DOC_CTL7 0x0758
  1008. #define BIT_DOC_CTL7_DOC_CTRL7_7 BIT(7)
  1009. #define BIT_DOC_CTL7_DOC_CTRL7_6 BIT(6)
  1010. #define BIT_DOC_CTL7_DOC_CTRL7_5 BIT(5)
  1011. #define MSK_DOC_CTL7_DOC_CTRL7_4_3 0x18
  1012. #define MSK_DOC_CTL7_DOC_CTRL7_2_0 0x07
  1013. /* DoC 9th Ctl, default value: 0x00 */
  1014. #define REG_DOC_CTL8 0x076c
  1015. #define BIT_DOC_CTL8_DOC_CTRL8_7 BIT(7)
  1016. #define MSK_DOC_CTL8_DOC_CTRL8_6_4 0x70
  1017. #define MSK_DOC_CTL8_DOC_CTRL8_3_2 0x0c
  1018. #define MSK_DOC_CTL8_DOC_CTRL8_1_0 0x03
  1019. /* DoC 10th Ctl, default value: 0x00 */
  1020. #define REG_DOC_CTL9 0x076d
  1021. /* DoC 11th Ctl, default value: 0x00 */
  1022. #define REG_DOC_CTLA 0x076e
  1023. /* DoC 15th Ctl, default value: 0x00 */
  1024. #define REG_DOC_CTLE 0x0772
  1025. #define BIT_DOC_CTLE_DOC_CTRLE_7 BIT(7)
  1026. #define BIT_DOC_CTLE_DOC_CTRLE_6 BIT(6)
  1027. #define MSK_DOC_CTLE_DOC_CTRLE_5_4 0x30
  1028. #define MSK_DOC_CTLE_DOC_CTRLE_3_0 0x0f
  1029. /* Interrupt Mask 1st, default value: 0x00 */
  1030. #define REG_MHL_INT_0_MASK 0x0580
  1031. /* Interrupt Mask 2nd, default value: 0x00 */
  1032. #define REG_MHL_INT_1_MASK 0x0581
  1033. /* Interrupt Mask 3rd, default value: 0x00 */
  1034. #define REG_MHL_INT_2_MASK 0x0582
  1035. /* Interrupt Mask 4th, default value: 0x00 */
  1036. #define REG_MHL_INT_3_MASK 0x0583
  1037. /* MDT Receive Time Out, default value: 0x00 */
  1038. #define REG_MDT_RCV_TIMEOUT 0x0584
  1039. /* MDT Transmit Time Out, default value: 0x00 */
  1040. #define REG_MDT_XMIT_TIMEOUT 0x0585
  1041. /* MDT Receive Control, default value: 0x00 */
  1042. #define REG_MDT_RCV_CTRL 0x0586
  1043. #define BIT_MDT_RCV_CTRL_MDT_RCV_EN BIT(7)
  1044. #define BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN BIT(6)
  1045. #define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN BIT(4)
  1046. #define BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN BIT(3)
  1047. #define BIT_MDT_RCV_CTRL_MDT_DISABLE BIT(2)
  1048. #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL BIT(1)
  1049. #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR BIT(0)
  1050. /* MDT Receive Read Port, default value: 0x00 */
  1051. #define REG_MDT_RCV_READ_PORT 0x0587
  1052. /* MDT Transmit Control, default value: 0x70 */
  1053. #define REG_MDT_XMIT_CTRL 0x0588
  1054. #define BIT_MDT_XMIT_CTRL_EN BIT(7)
  1055. #define BIT_MDT_XMIT_CTRL_CMD_MERGE_EN BIT(6)
  1056. #define BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN BIT(5)
  1057. #define BIT_MDT_XMIT_CTRL_FIXED_AID BIT(4)
  1058. #define BIT_MDT_XMIT_CTRL_SINGLE_RUN_EN BIT(3)
  1059. #define BIT_MDT_XMIT_CTRL_CLR_ABORT_WAIT BIT(2)
  1060. #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL BIT(1)
  1061. #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_CUR BIT(0)
  1062. /* MDT Receive WRITE Port, default value: 0x00 */
  1063. #define REG_MDT_XMIT_WRITE_PORT 0x0589
  1064. /* MDT RFIFO Status, default value: 0x00 */
  1065. #define REG_MDT_RFIFO_STAT 0x058a
  1066. #define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CNT 0xe0
  1067. #define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CUR_BYTE_CNT 0x1f
  1068. /* MDT XFIFO Status, default value: 0x80 */
  1069. #define REG_MDT_XFIFO_STAT 0x058b
  1070. #define MSK_MDT_XFIFO_STAT_MDT_XFIFO_LEVEL_AVAIL 0xe0
  1071. #define BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN BIT(4)
  1072. #define MSK_MDT_XFIFO_STAT_MDT_WRITE_BURST_LEN 0x0f
  1073. /* MDT Interrupt 0, default value: 0x0c */
  1074. #define REG_MDT_INT_0 0x058c
  1075. #define BIT_MDT_RFIFO_DATA_RDY BIT(0)
  1076. #define BIT_MDT_IDLE_AFTER_HAWB_DISABLE BIT(2)
  1077. #define BIT_MDT_XFIFO_EMPTY BIT(3)
  1078. /* MDT Interrupt 0 Mask, default value: 0x00 */
  1079. #define REG_MDT_INT_0_MASK 0x058d
  1080. /* MDT Interrupt 1, default value: 0x00 */
  1081. #define REG_MDT_INT_1 0x058e
  1082. #define BIT_MDT_RCV_TIMEOUT BIT(0)
  1083. #define BIT_MDT_RCV_SM_ABORT_PKT_RCVD BIT(1)
  1084. #define BIT_MDT_RCV_SM_ERROR BIT(2)
  1085. #define BIT_MDT_XMIT_TIMEOUT BIT(5)
  1086. #define BIT_MDT_XMIT_SM_ABORT_PKT_RCVD BIT(6)
  1087. #define BIT_MDT_XMIT_SM_ERROR BIT(7)
  1088. /* MDT Interrupt 1 Mask, default value: 0x00 */
  1089. #define REG_MDT_INT_1_MASK 0x058f
  1090. /* CBUS Vendor ID, default value: 0x01 */
  1091. #define REG_CBUS_VENDOR_ID 0x0590
  1092. /* CBUS Connection Status, default value: 0x00 */
  1093. #define REG_CBUS_STATUS 0x0591
  1094. #define BIT_CBUS_STATUS_MHL_CABLE_PRESENT BIT(4)
  1095. #define BIT_CBUS_STATUS_MSC_HB_SUCCESS BIT(3)
  1096. #define BIT_CBUS_STATUS_CBUS_HPD BIT(2)
  1097. #define BIT_CBUS_STATUS_MHL_MODE BIT(1)
  1098. #define BIT_CBUS_STATUS_CBUS_CONNECTED BIT(0)
  1099. /* CBUS Interrupt 1st, default value: 0x00 */
  1100. #define REG_CBUS_INT_0 0x0592
  1101. #define BIT_CBUS_MSC_MT_DONE_NACK BIT(7)
  1102. #define BIT_CBUS_MSC_MR_SET_INT BIT(6)
  1103. #define BIT_CBUS_MSC_MR_WRITE_BURST BIT(5)
  1104. #define BIT_CBUS_MSC_MR_MSC_MSG BIT(4)
  1105. #define BIT_CBUS_MSC_MR_WRITE_STAT BIT(3)
  1106. #define BIT_CBUS_HPD_CHG BIT(2)
  1107. #define BIT_CBUS_MSC_MT_DONE BIT(1)
  1108. #define BIT_CBUS_CNX_CHG BIT(0)
  1109. /* CBUS Interrupt Mask 1st, default value: 0x00 */
  1110. #define REG_CBUS_INT_0_MASK 0x0593
  1111. /* CBUS Interrupt 2nd, default value: 0x00 */
  1112. #define REG_CBUS_INT_1 0x0594
  1113. #define BIT_CBUS_CMD_ABORT BIT(6)
  1114. #define BIT_CBUS_MSC_ABORT_RCVD BIT(3)
  1115. #define BIT_CBUS_DDC_ABORT BIT(2)
  1116. #define BIT_CBUS_CEC_ABORT BIT(1)
  1117. /* CBUS Interrupt Mask 2nd, default value: 0x00 */
  1118. #define REG_CBUS_INT_1_MASK 0x0595
  1119. /* CBUS DDC Abort Interrupt, default value: 0x00 */
  1120. #define REG_DDC_ABORT_INT 0x0598
  1121. /* CBUS DDC Abort Interrupt Mask, default value: 0x00 */
  1122. #define REG_DDC_ABORT_INT_MASK 0x0599
  1123. /* CBUS MSC Requester Abort Interrupt, default value: 0x00 */
  1124. #define REG_MSC_MT_ABORT_INT 0x059a
  1125. /* CBUS MSC Requester Abort Interrupt Mask, default value: 0x00 */
  1126. #define REG_MSC_MT_ABORT_INT_MASK 0x059b
  1127. /* CBUS MSC Responder Abort Interrupt, default value: 0x00 */
  1128. #define REG_MSC_MR_ABORT_INT 0x059c
  1129. /* CBUS MSC Responder Abort Interrupt Mask, default value: 0x00 */
  1130. #define REG_MSC_MR_ABORT_INT_MASK 0x059d
  1131. /* CBUS RX DISCOVERY interrupt, default value: 0x00 */
  1132. #define REG_CBUS_RX_DISC_INT0 0x059e
  1133. /* CBUS RX DISCOVERY Interrupt Mask, default value: 0x00 */
  1134. #define REG_CBUS_RX_DISC_INT0_MASK 0x059f
  1135. /* CBUS_Link_Layer Control #8, default value: 0x00 */
  1136. #define REG_CBUS_LINK_CTRL_8 0x05a7
  1137. /* MDT State Machine Status, default value: 0x00 */
  1138. #define REG_MDT_SM_STAT 0x05b5
  1139. #define MSK_MDT_SM_STAT_MDT_RCV_STATE 0xf0
  1140. #define MSK_MDT_SM_STAT_MDT_XMIT_STATE 0x0f
  1141. /* CBUS MSC command trigger, default value: 0x00 */
  1142. #define REG_MSC_COMMAND_START 0x05b8
  1143. #define BIT_MSC_COMMAND_START_DEBUG BIT(5)
  1144. #define BIT_MSC_COMMAND_START_WRITE_BURST BIT(4)
  1145. #define BIT_MSC_COMMAND_START_WRITE_STAT BIT(3)
  1146. #define BIT_MSC_COMMAND_START_READ_DEVCAP BIT(2)
  1147. #define BIT_MSC_COMMAND_START_MSC_MSG BIT(1)
  1148. #define BIT_MSC_COMMAND_START_PEER BIT(0)
  1149. /* CBUS MSC Command/Offset, default value: 0x00 */
  1150. #define REG_MSC_CMD_OR_OFFSET 0x05b9
  1151. /* CBUS MSC Transmit Data */
  1152. #define REG_MSC_1ST_TRANSMIT_DATA 0x05ba
  1153. #define REG_MSC_2ND_TRANSMIT_DATA 0x05bb
  1154. /* CBUS MSC Requester Received Data */
  1155. #define REG_MSC_MT_RCVD_DATA0 0x05bc
  1156. #define REG_MSC_MT_RCVD_DATA1 0x05bd
  1157. /* CBUS MSC Responder MSC_MSG Received Data */
  1158. #define REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA 0x05bf
  1159. #define REG_MSC_MR_MSC_MSG_RCVD_2ND_DATA 0x05c0
  1160. /* CBUS MSC Heartbeat Control, default value: 0x27 */
  1161. #define REG_MSC_HEARTBEAT_CTRL 0x05c4
  1162. #define BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN BIT(7)
  1163. #define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_FAIL_LIMIT 0x70
  1164. #define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_PERIOD_MSB 0x0f
  1165. /* CBUS MSC Compatibility Control, default value: 0x02 */
  1166. #define REG_CBUS_MSC_COMPAT_CTRL 0x05c7
  1167. #define BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN BIT(7)
  1168. #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS BIT(6)
  1169. #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS BIT(5)
  1170. #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE BIT(3)
  1171. #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE BIT(2)
  1172. /* CBUS3 Converter Control, default value: 0x24 */
  1173. #define REG_CBUS3_CNVT 0x05dc
  1174. #define MSK_CBUS3_CNVT_CBUS3_RETRYLMT 0xf0
  1175. #define MSK_CBUS3_CNVT_CBUS3_PEERTOUT_SEL 0x0c
  1176. #define BIT_CBUS3_CNVT_TEARCBUS_EN BIT(1)
  1177. #define BIT_CBUS3_CNVT_CBUS3CNVT_EN BIT(0)
  1178. /* Discovery Control1, default value: 0x24 */
  1179. #define REG_DISC_CTRL1 0x05e0
  1180. #define BIT_DISC_CTRL1_CBUS_INTR_EN BIT(7)
  1181. #define BIT_DISC_CTRL1_HB_ONLY BIT(6)
  1182. #define MSK_DISC_CTRL1_DISC_ATT 0x30
  1183. #define MSK_DISC_CTRL1_DISC_CYC 0x0c
  1184. #define BIT_DISC_CTRL1_DISC_EN BIT(0)
  1185. #define VAL_PUP_OFF 0
  1186. #define VAL_PUP_20K 1
  1187. #define VAL_PUP_5K 2
  1188. /* Discovery Control4, default value: 0x80 */
  1189. #define REG_DISC_CTRL4 0x05e3
  1190. #define MSK_DISC_CTRL4_CBUSDISC_PUP_SEL 0xc0
  1191. #define MSK_DISC_CTRL4_CBUSIDLE_PUP_SEL 0x30
  1192. #define VAL_DISC_CTRL4(pup_disc, pup_idle) (((pup_disc) << 6) | (pup_idle << 4))
  1193. /* Discovery Control5, default value: 0x03 */
  1194. #define REG_DISC_CTRL5 0x05e4
  1195. #define BIT_DISC_CTRL5_DSM_OVRIDE BIT(3)
  1196. #define MSK_DISC_CTRL5_CBUSMHL_PUP_SEL 0x03
  1197. /* Discovery Control8, default value: 0x81 */
  1198. #define REG_DISC_CTRL8 0x05e7
  1199. #define BIT_DISC_CTRL8_NOMHLINT_CLR_BYPASS BIT(7)
  1200. #define BIT_DISC_CTRL8_DELAY_CBUS_INTR_EN BIT(0)
  1201. /* Discovery Control9, default value: 0x54 */
  1202. #define REG_DISC_CTRL9 0x05e8
  1203. #define BIT_DISC_CTRL9_MHL3_RSEN_BYP BIT(7)
  1204. #define BIT_DISC_CTRL9_MHL3DISC_EN BIT(6)
  1205. #define BIT_DISC_CTRL9_WAKE_DRVFLT BIT(4)
  1206. #define BIT_DISC_CTRL9_NOMHL_EST BIT(3)
  1207. #define BIT_DISC_CTRL9_DISC_PULSE_PROCEED BIT(2)
  1208. #define BIT_DISC_CTRL9_WAKE_PULSE_BYPASS BIT(1)
  1209. #define BIT_DISC_CTRL9_VBUS_OUTPUT_CAPABILITY_SRC BIT(0)
  1210. /* Discovery Status1, default value: 0x00 */
  1211. #define REG_DISC_STAT1 0x05eb
  1212. #define BIT_DISC_STAT1_PSM_OVRIDE BIT(5)
  1213. #define MSK_DISC_STAT1_DISC_SM 0x0f
  1214. /* Discovery Status2, default value: 0x00 */
  1215. #define REG_DISC_STAT2 0x05ec
  1216. #define BIT_DISC_STAT2_CBUS_OE_POL BIT(6)
  1217. #define BIT_DISC_STAT2_CBUS_SATUS BIT(5)
  1218. #define BIT_DISC_STAT2_RSEN BIT(4)
  1219. #define MSK_DISC_STAT2_MHL_VRSN 0x0c
  1220. #define VAL_DISC_STAT2_DEFAULT 0x00
  1221. #define VAL_DISC_STAT2_MHL1_2 0x04
  1222. #define VAL_DISC_STAT2_MHL3 0x08
  1223. #define VAL_DISC_STAT2_RESERVED 0x0c
  1224. #define MSK_DISC_STAT2_RGND 0x03
  1225. #define VAL_RGND_OPEN 0x00
  1226. #define VAL_RGND_2K 0x01
  1227. #define VAL_RGND_1K 0x02
  1228. #define VAL_RGND_SHORT 0x03
  1229. /* Interrupt CBUS_reg1 INTR0, default value: 0x00 */
  1230. #define REG_CBUS_DISC_INTR0 0x05ed
  1231. #define BIT_RGND_READY_INT BIT(6)
  1232. #define BIT_CBUS_MHL12_DISCON_INT BIT(5)
  1233. #define BIT_CBUS_MHL3_DISCON_INT BIT(4)
  1234. #define BIT_NOT_MHL_EST_INT BIT(3)
  1235. #define BIT_MHL_EST_INT BIT(2)
  1236. #define BIT_MHL3_EST_INT BIT(1)
  1237. #define VAL_CBUS_MHL_DISCON (BIT_CBUS_MHL12_DISCON_INT \
  1238. | BIT_CBUS_MHL3_DISCON_INT \
  1239. | BIT_NOT_MHL_EST_INT)
  1240. /* Interrupt CBUS_reg1 INTR0 Mask, default value: 0x00 */
  1241. #define REG_CBUS_DISC_INTR0_MASK 0x05ee
  1242. #endif /* __SIL_SII8620_H__ */