nwl-dsi.h 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * NWL MIPI DSI host driver
  4. *
  5. * Copyright (C) 2017 NXP
  6. * Copyright (C) 2019 Purism SPC
  7. */
  8. #ifndef __NWL_DSI_H__
  9. #define __NWL_DSI_H__
  10. /* DSI HOST registers */
  11. #define NWL_DSI_CFG_NUM_LANES 0x0
  12. #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
  13. #define NWL_DSI_CFG_T_PRE 0x8
  14. #define NWL_DSI_CFG_T_POST 0xc
  15. #define NWL_DSI_CFG_TX_GAP 0x10
  16. #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
  17. #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
  18. #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
  19. #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
  20. #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
  21. #define NWL_DSI_CFG_TWAKEUP 0x28
  22. #define NWL_DSI_CFG_STATUS_OUT 0x2c
  23. #define NWL_DSI_RX_ERROR_STATUS 0x30
  24. /* DSI DPI registers */
  25. #define NWL_DSI_PIXEL_PAYLOAD_SIZE 0x200
  26. #define NWL_DSI_PIXEL_FIFO_SEND_LEVEL 0x204
  27. #define NWL_DSI_INTERFACE_COLOR_CODING 0x208
  28. #define NWL_DSI_PIXEL_FORMAT 0x20c
  29. #define NWL_DSI_VSYNC_POLARITY 0x210
  30. #define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW 0
  31. #define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(1)
  32. #define NWL_DSI_HSYNC_POLARITY 0x214
  33. #define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW 0
  34. #define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(1)
  35. #define NWL_DSI_VIDEO_MODE 0x218
  36. #define NWL_DSI_HFP 0x21c
  37. #define NWL_DSI_HBP 0x220
  38. #define NWL_DSI_HSA 0x224
  39. #define NWL_DSI_ENABLE_MULT_PKTS 0x228
  40. #define NWL_DSI_VBP 0x22c
  41. #define NWL_DSI_VFP 0x230
  42. #define NWL_DSI_BLLP_MODE 0x234
  43. #define NWL_DSI_USE_NULL_PKT_BLLP 0x238
  44. #define NWL_DSI_VACTIVE 0x23c
  45. #define NWL_DSI_VC 0x240
  46. /* DSI APB PKT control */
  47. #define NWL_DSI_TX_PAYLOAD 0x280
  48. #define NWL_DSI_PKT_CONTROL 0x284
  49. #define NWL_DSI_SEND_PACKET 0x288
  50. #define NWL_DSI_PKT_STATUS 0x28c
  51. #define NWL_DSI_PKT_FIFO_WR_LEVEL 0x290
  52. #define NWL_DSI_PKT_FIFO_RD_LEVEL 0x294
  53. #define NWL_DSI_RX_PAYLOAD 0x298
  54. #define NWL_DSI_RX_PKT_HEADER 0x29c
  55. /* DSI IRQ handling */
  56. #define NWL_DSI_IRQ_STATUS 0x2a0
  57. #define NWL_DSI_SM_NOT_IDLE BIT(0)
  58. #define NWL_DSI_TX_PKT_DONE BIT(1)
  59. #define NWL_DSI_DPHY_DIRECTION BIT(2)
  60. #define NWL_DSI_TX_FIFO_OVFLW BIT(3)
  61. #define NWL_DSI_TX_FIFO_UDFLW BIT(4)
  62. #define NWL_DSI_RX_FIFO_OVFLW BIT(5)
  63. #define NWL_DSI_RX_FIFO_UDFLW BIT(6)
  64. #define NWL_DSI_RX_PKT_HDR_RCVD BIT(7)
  65. #define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD BIT(8)
  66. #define NWL_DSI_BTA_TIMEOUT BIT(29)
  67. #define NWL_DSI_LP_RX_TIMEOUT BIT(30)
  68. #define NWL_DSI_HS_TX_TIMEOUT BIT(31)
  69. #define NWL_DSI_IRQ_STATUS2 0x2a4
  70. #define NWL_DSI_SINGLE_BIT_ECC_ERR BIT(0)
  71. #define NWL_DSI_MULTI_BIT_ECC_ERR BIT(1)
  72. #define NWL_DSI_CRC_ERR BIT(2)
  73. #define NWL_DSI_IRQ_MASK 0x2a8
  74. #define NWL_DSI_SM_NOT_IDLE_MASK BIT(0)
  75. #define NWL_DSI_TX_PKT_DONE_MASK BIT(1)
  76. #define NWL_DSI_DPHY_DIRECTION_MASK BIT(2)
  77. #define NWL_DSI_TX_FIFO_OVFLW_MASK BIT(3)
  78. #define NWL_DSI_TX_FIFO_UDFLW_MASK BIT(4)
  79. #define NWL_DSI_RX_FIFO_OVFLW_MASK BIT(5)
  80. #define NWL_DSI_RX_FIFO_UDFLW_MASK BIT(6)
  81. #define NWL_DSI_RX_PKT_HDR_RCVD_MASK BIT(7)
  82. #define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK BIT(8)
  83. #define NWL_DSI_BTA_TIMEOUT_MASK BIT(29)
  84. #define NWL_DSI_LP_RX_TIMEOUT_MASK BIT(30)
  85. #define NWL_DSI_HS_TX_TIMEOUT_MASK BIT(31)
  86. #define NWL_DSI_IRQ_MASK2 0x2ac
  87. #define NWL_DSI_SINGLE_BIT_ECC_ERR_MASK BIT(0)
  88. #define NWL_DSI_MULTI_BIT_ECC_ERR_MASK BIT(1)
  89. #define NWL_DSI_CRC_ERR_MASK BIT(2)
  90. /*
  91. * PKT_CONTROL format:
  92. * [15: 0] - word count
  93. * [17:16] - virtual channel
  94. * [23:18] - data type
  95. * [24] - LP or HS select (0 - LP, 1 - HS)
  96. * [25] - perform BTA after packet is sent
  97. * [26] - perform BTA only, no packet tx
  98. */
  99. #define NWL_DSI_WC(x) FIELD_PREP(GENMASK(15, 0), (x))
  100. #define NWL_DSI_TX_VC(x) FIELD_PREP(GENMASK(17, 16), (x))
  101. #define NWL_DSI_TX_DT(x) FIELD_PREP(GENMASK(23, 18), (x))
  102. #define NWL_DSI_HS_SEL(x) FIELD_PREP(GENMASK(24, 24), (x))
  103. #define NWL_DSI_BTA_TX(x) FIELD_PREP(GENMASK(25, 25), (x))
  104. #define NWL_DSI_BTA_NO_TX(x) FIELD_PREP(GENMASK(26, 26), (x))
  105. /*
  106. * RX_PKT_HEADER format:
  107. * [15: 0] - word count
  108. * [21:16] - data type
  109. * [23:22] - virtual channel
  110. */
  111. #define NWL_DSI_RX_DT(x) FIELD_GET(GENMASK(21, 16), (x))
  112. #define NWL_DSI_RX_VC(x) FIELD_GET(GENMASK(23, 22), (x))
  113. /* DSI Video mode */
  114. #define NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES 0
  115. #define NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS BIT(0)
  116. #define NWL_DSI_VM_BURST_MODE BIT(1)
  117. /* * DPI color coding */
  118. #define NWL_DSI_DPI_16_BIT_565_PACKED 0
  119. #define NWL_DSI_DPI_16_BIT_565_ALIGNED 1
  120. #define NWL_DSI_DPI_16_BIT_565_SHIFTED 2
  121. #define NWL_DSI_DPI_18_BIT_PACKED 3
  122. #define NWL_DSI_DPI_18_BIT_ALIGNED 4
  123. #define NWL_DSI_DPI_24_BIT 5
  124. /* * DPI Pixel format */
  125. #define NWL_DSI_PIXEL_FORMAT_16 0
  126. #define NWL_DSI_PIXEL_FORMAT_18 BIT(0)
  127. #define NWL_DSI_PIXEL_FORMAT_18L BIT(1)
  128. #define NWL_DSI_PIXEL_FORMAT_24 (BIT(0) | BIT(1))
  129. #endif /* __NWL_DSI_H__ */