nwl-dsi.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * i.MX8 NWL MIPI DSI host driver
  4. *
  5. * Copyright (C) 2017 NXP
  6. * Copyright (C) 2020 Purism SPC
  7. */
  8. #include <linux/bitfield.h>
  9. #include <linux/clk.h>
  10. #include <linux/irq.h>
  11. #include <linux/math64.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <linux/module.h>
  14. #include <linux/mux/consumer.h>
  15. #include <linux/of.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/phy/phy.h>
  18. #include <linux/regmap.h>
  19. #include <linux/reset.h>
  20. #include <linux/sys_soc.h>
  21. #include <linux/time64.h>
  22. #include <drm/drm_atomic_state_helper.h>
  23. #include <drm/drm_bridge.h>
  24. #include <drm/drm_mipi_dsi.h>
  25. #include <drm/drm_of.h>
  26. #include <drm/drm_panel.h>
  27. #include <drm/drm_print.h>
  28. #include <video/mipi_display.h>
  29. #include "nwl-dsi.h"
  30. #define DRV_NAME "nwl-dsi"
  31. /* i.MX8 NWL quirks */
  32. /* i.MX8MQ errata E11418 */
  33. #define E11418_HS_MODE_QUIRK BIT(0)
  34. #define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500)
  35. enum transfer_direction {
  36. DSI_PACKET_SEND,
  37. DSI_PACKET_RECEIVE,
  38. };
  39. #define NWL_DSI_ENDPOINT_LCDIF 0
  40. #define NWL_DSI_ENDPOINT_DCSS 1
  41. struct nwl_dsi_plat_clk_config {
  42. const char *id;
  43. struct clk *clk;
  44. bool present;
  45. };
  46. struct nwl_dsi_transfer {
  47. const struct mipi_dsi_msg *msg;
  48. struct mipi_dsi_packet packet;
  49. struct completion completed;
  50. int status; /* status of transmission */
  51. enum transfer_direction direction;
  52. bool need_bta;
  53. u8 cmd;
  54. u16 rx_word_count;
  55. size_t tx_len; /* in bytes */
  56. size_t rx_len; /* in bytes */
  57. };
  58. struct nwl_dsi {
  59. struct drm_bridge bridge;
  60. struct mipi_dsi_host dsi_host;
  61. struct drm_bridge *panel_bridge;
  62. struct device *dev;
  63. struct phy *phy;
  64. union phy_configure_opts phy_cfg;
  65. unsigned int quirks;
  66. struct regmap *regmap;
  67. int irq;
  68. /*
  69. * The DSI host controller needs this reset sequence according to NWL:
  70. * 1. Deassert pclk reset to get access to DSI regs
  71. * 2. Configure DSI Host and DPHY and enable DPHY
  72. * 3. Deassert ESC and BYTE resets to allow host TX operations)
  73. * 4. Send DSI cmds to configure peripheral (handled by panel drv)
  74. * 5. Deassert DPI reset so DPI receives pixels and starts sending
  75. * DSI data
  76. *
  77. * TODO: Since panel_bridges do their DSI setup in enable we
  78. * currently have 4. and 5. swapped.
  79. */
  80. struct reset_control *rst_byte;
  81. struct reset_control *rst_esc;
  82. struct reset_control *rst_dpi;
  83. struct reset_control *rst_pclk;
  84. struct mux_control *mux;
  85. /* DSI clocks */
  86. struct clk *phy_ref_clk;
  87. struct clk *rx_esc_clk;
  88. struct clk *tx_esc_clk;
  89. struct clk *core_clk;
  90. /*
  91. * hardware bug: the i.MX8MQ needs this clock on during reset
  92. * even when not using LCDIF.
  93. */
  94. struct clk *lcdif_clk;
  95. /* dsi lanes */
  96. u32 lanes;
  97. enum mipi_dsi_pixel_format format;
  98. struct drm_display_mode mode;
  99. unsigned long dsi_mode_flags;
  100. int error;
  101. struct nwl_dsi_transfer *xfer;
  102. };
  103. static const struct regmap_config nwl_dsi_regmap_config = {
  104. .reg_bits = 16,
  105. .val_bits = 32,
  106. .reg_stride = 4,
  107. .max_register = NWL_DSI_IRQ_MASK2,
  108. .name = DRV_NAME,
  109. };
  110. static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge)
  111. {
  112. return container_of(bridge, struct nwl_dsi, bridge);
  113. }
  114. static int nwl_dsi_clear_error(struct nwl_dsi *dsi)
  115. {
  116. int ret = dsi->error;
  117. dsi->error = 0;
  118. return ret;
  119. }
  120. static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
  121. {
  122. int ret;
  123. if (dsi->error)
  124. return;
  125. ret = regmap_write(dsi->regmap, reg, val);
  126. if (ret < 0) {
  127. DRM_DEV_ERROR(dsi->dev,
  128. "Failed to write NWL DSI reg 0x%x: %d\n", reg,
  129. ret);
  130. dsi->error = ret;
  131. }
  132. }
  133. static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
  134. {
  135. unsigned int val;
  136. int ret;
  137. if (dsi->error)
  138. return 0;
  139. ret = regmap_read(dsi->regmap, reg, &val);
  140. if (ret < 0) {
  141. DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
  142. reg, ret);
  143. dsi->error = ret;
  144. }
  145. return val;
  146. }
  147. static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)
  148. {
  149. switch (format) {
  150. case MIPI_DSI_FMT_RGB565:
  151. return NWL_DSI_PIXEL_FORMAT_16;
  152. case MIPI_DSI_FMT_RGB666:
  153. return NWL_DSI_PIXEL_FORMAT_18L;
  154. case MIPI_DSI_FMT_RGB666_PACKED:
  155. return NWL_DSI_PIXEL_FORMAT_18;
  156. case MIPI_DSI_FMT_RGB888:
  157. return NWL_DSI_PIXEL_FORMAT_24;
  158. default:
  159. return -EINVAL;
  160. }
  161. }
  162. /*
  163. * ps2bc - Picoseconds to byte clock cycles
  164. */
  165. static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
  166. {
  167. u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
  168. return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
  169. dsi->lanes * 8ULL * NSEC_PER_SEC);
  170. }
  171. /*
  172. * ui2bc - UI time periods to byte clock cycles
  173. */
  174. static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui)
  175. {
  176. u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
  177. return DIV64_U64_ROUND_UP(ui * dsi->lanes,
  178. dsi->mode.clock * 1000 * bpp);
  179. }
  180. /*
  181. * us2bc - micro seconds to lp clock cycles
  182. */
  183. static u32 us2lp(u32 lp_clk_rate, unsigned long us)
  184. {
  185. return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC);
  186. }
  187. static int nwl_dsi_config_host(struct nwl_dsi *dsi)
  188. {
  189. u32 cycles;
  190. struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
  191. if (dsi->lanes < 1 || dsi->lanes > 4)
  192. return -EINVAL;
  193. DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
  194. nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
  195. if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
  196. nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
  197. nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
  198. } else {
  199. nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
  200. nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
  201. }
  202. /* values in byte clock cycles */
  203. cycles = ui2bc(dsi, cfg->clk_pre);
  204. DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
  205. nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
  206. cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
  207. DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
  208. cycles += ui2bc(dsi, cfg->clk_pre);
  209. DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
  210. nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
  211. cycles = ps2bc(dsi, cfg->hs_exit);
  212. DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
  213. nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
  214. nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
  215. nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
  216. nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
  217. nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
  218. /* In LP clock cycles */
  219. cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);
  220. DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
  221. nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
  222. return nwl_dsi_clear_error(dsi);
  223. }
  224. static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
  225. {
  226. u32 mode;
  227. int color_format;
  228. bool burst_mode;
  229. int hfront_porch, hback_porch, vfront_porch, vback_porch;
  230. int hsync_len, vsync_len;
  231. hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
  232. hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
  233. hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
  234. vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
  235. vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
  236. vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
  237. DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
  238. DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
  239. DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
  240. DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
  241. DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
  242. DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
  243. DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
  244. DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
  245. DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
  246. color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
  247. if (color_format < 0) {
  248. DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
  249. dsi->format);
  250. return color_format;
  251. }
  252. DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
  253. nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
  254. nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
  255. /*
  256. * Adjusting input polarity based on the video mode results in
  257. * a black screen so always pick active low:
  258. */
  259. nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
  260. NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
  261. nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
  262. NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
  263. burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
  264. !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
  265. if (burst_mode) {
  266. nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
  267. nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
  268. } else {
  269. mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
  270. NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES :
  271. NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS);
  272. nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
  273. nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
  274. dsi->mode.hdisplay);
  275. }
  276. nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
  277. nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
  278. nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
  279. nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
  280. nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
  281. nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
  282. nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
  283. nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
  284. nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
  285. nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
  286. nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
  287. return nwl_dsi_clear_error(dsi);
  288. }
  289. static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
  290. {
  291. u32 irq_enable;
  292. nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff);
  293. nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
  294. irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK |
  295. NWL_DSI_RX_PKT_HDR_RCVD_MASK |
  296. NWL_DSI_TX_FIFO_OVFLW_MASK |
  297. NWL_DSI_HS_TX_TIMEOUT_MASK);
  298. nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
  299. return nwl_dsi_clear_error(dsi);
  300. }
  301. static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host,
  302. struct mipi_dsi_device *device)
  303. {
  304. struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
  305. struct device *dev = dsi->dev;
  306. DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,
  307. device->format, device->mode_flags);
  308. if (device->lanes < 1 || device->lanes > 4)
  309. return -EINVAL;
  310. dsi->lanes = device->lanes;
  311. dsi->format = device->format;
  312. dsi->dsi_mode_flags = device->mode_flags;
  313. return 0;
  314. }
  315. static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
  316. {
  317. struct device *dev = dsi->dev;
  318. struct nwl_dsi_transfer *xfer = dsi->xfer;
  319. int err;
  320. u8 *payload = xfer->msg->rx_buf;
  321. u32 val;
  322. u16 word_count;
  323. u8 channel;
  324. u8 data_type;
  325. xfer->status = 0;
  326. if (xfer->rx_word_count == 0) {
  327. if (!(status & NWL_DSI_RX_PKT_HDR_RCVD))
  328. return false;
  329. /* Get the RX header and parse it */
  330. val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
  331. err = nwl_dsi_clear_error(dsi);
  332. if (err)
  333. xfer->status = err;
  334. word_count = NWL_DSI_WC(val);
  335. channel = NWL_DSI_RX_VC(val);
  336. data_type = NWL_DSI_RX_DT(val);
  337. if (channel != xfer->msg->channel) {
  338. DRM_DEV_ERROR(dev,
  339. "[%02X] Channel mismatch (%u != %u)\n",
  340. xfer->cmd, channel, xfer->msg->channel);
  341. xfer->status = -EINVAL;
  342. return true;
  343. }
  344. switch (data_type) {
  345. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
  346. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
  347. if (xfer->msg->rx_len > 1) {
  348. /* read second byte */
  349. payload[1] = word_count >> 8;
  350. ++xfer->rx_len;
  351. }
  352. fallthrough;
  353. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
  354. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
  355. if (xfer->msg->rx_len > 0) {
  356. /* read first byte */
  357. payload[0] = word_count & 0xff;
  358. ++xfer->rx_len;
  359. }
  360. xfer->status = xfer->rx_len;
  361. return true;
  362. case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
  363. word_count &= 0xff;
  364. DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n",
  365. xfer->cmd, word_count);
  366. xfer->status = -EPROTO;
  367. return true;
  368. }
  369. if (word_count > xfer->msg->rx_len) {
  370. DRM_DEV_ERROR(dev,
  371. "[%02X] Receive buffer too small: %zu (< %u)\n",
  372. xfer->cmd, xfer->msg->rx_len, word_count);
  373. xfer->status = -EINVAL;
  374. return true;
  375. }
  376. xfer->rx_word_count = word_count;
  377. } else {
  378. /* Set word_count from previous header read */
  379. word_count = xfer->rx_word_count;
  380. }
  381. /* If RX payload is not yet received, wait for it */
  382. if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD))
  383. return false;
  384. /* Read the RX payload */
  385. while (word_count >= 4) {
  386. val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
  387. payload[0] = (val >> 0) & 0xff;
  388. payload[1] = (val >> 8) & 0xff;
  389. payload[2] = (val >> 16) & 0xff;
  390. payload[3] = (val >> 24) & 0xff;
  391. payload += 4;
  392. xfer->rx_len += 4;
  393. word_count -= 4;
  394. }
  395. if (word_count > 0) {
  396. val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
  397. switch (word_count) {
  398. case 3:
  399. payload[2] = (val >> 16) & 0xff;
  400. ++xfer->rx_len;
  401. fallthrough;
  402. case 2:
  403. payload[1] = (val >> 8) & 0xff;
  404. ++xfer->rx_len;
  405. fallthrough;
  406. case 1:
  407. payload[0] = (val >> 0) & 0xff;
  408. ++xfer->rx_len;
  409. break;
  410. }
  411. }
  412. xfer->status = xfer->rx_len;
  413. err = nwl_dsi_clear_error(dsi);
  414. if (err)
  415. xfer->status = err;
  416. return true;
  417. }
  418. static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
  419. {
  420. struct nwl_dsi_transfer *xfer = dsi->xfer;
  421. bool end_packet = false;
  422. if (!xfer)
  423. return;
  424. if (xfer->direction == DSI_PACKET_SEND &&
  425. status & NWL_DSI_TX_PKT_DONE) {
  426. xfer->status = xfer->tx_len;
  427. end_packet = true;
  428. } else if (status & NWL_DSI_DPHY_DIRECTION &&
  429. ((status & (NWL_DSI_RX_PKT_HDR_RCVD |
  430. NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) {
  431. end_packet = nwl_dsi_read_packet(dsi, status);
  432. }
  433. if (end_packet)
  434. complete(&xfer->completed);
  435. }
  436. static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
  437. {
  438. struct nwl_dsi_transfer *xfer = dsi->xfer;
  439. struct mipi_dsi_packet *pkt = &xfer->packet;
  440. const u8 *payload;
  441. size_t length;
  442. u16 word_count;
  443. u8 hs_mode;
  444. u32 val;
  445. u32 hs_workaround = 0;
  446. /* Send the payload, if any */
  447. length = pkt->payload_length;
  448. payload = pkt->payload;
  449. while (length >= 4) {
  450. val = *(u32 *)payload;
  451. hs_workaround |= !(val & 0xFFFF00);
  452. nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
  453. payload += 4;
  454. length -= 4;
  455. }
  456. /* Send the rest of the payload */
  457. val = 0;
  458. switch (length) {
  459. case 3:
  460. val |= payload[2] << 16;
  461. fallthrough;
  462. case 2:
  463. val |= payload[1] << 8;
  464. hs_workaround |= !(val & 0xFFFF00);
  465. fallthrough;
  466. case 1:
  467. val |= payload[0];
  468. nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
  469. break;
  470. }
  471. xfer->tx_len = pkt->payload_length;
  472. /*
  473. * Send the header
  474. * header[0] = Virtual Channel + Data Type
  475. * header[1] = Word Count LSB (LP) or first param (SP)
  476. * header[2] = Word Count MSB (LP) or second param (SP)
  477. */
  478. word_count = pkt->header[1] | (pkt->header[2] << 8);
  479. if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
  480. DRM_DEV_DEBUG_DRIVER(dsi->dev,
  481. "Using hs mode workaround for cmd 0x%x\n",
  482. xfer->cmd);
  483. hs_mode = 1;
  484. } else {
  485. hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1;
  486. }
  487. val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) |
  488. NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) |
  489. NWL_DSI_BTA_TX(xfer->need_bta);
  490. nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
  491. /* Send packet command */
  492. nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
  493. }
  494. static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host,
  495. const struct mipi_dsi_msg *msg)
  496. {
  497. struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
  498. struct nwl_dsi_transfer xfer;
  499. ssize_t ret = 0;
  500. /* Create packet to be sent */
  501. dsi->xfer = &xfer;
  502. ret = mipi_dsi_create_packet(&xfer.packet, msg);
  503. if (ret < 0) {
  504. dsi->xfer = NULL;
  505. return ret;
  506. }
  507. if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||
  508. msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||
  509. msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||
  510. msg->type & MIPI_DSI_DCS_READ) &&
  511. msg->rx_len > 0 && msg->rx_buf)
  512. xfer.direction = DSI_PACKET_RECEIVE;
  513. else
  514. xfer.direction = DSI_PACKET_SEND;
  515. xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE);
  516. xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;
  517. xfer.msg = msg;
  518. xfer.status = -ETIMEDOUT;
  519. xfer.rx_word_count = 0;
  520. xfer.rx_len = 0;
  521. xfer.cmd = 0x00;
  522. if (msg->tx_len > 0)
  523. xfer.cmd = ((u8 *)(msg->tx_buf))[0];
  524. init_completion(&xfer.completed);
  525. ret = clk_prepare_enable(dsi->rx_esc_clk);
  526. if (ret < 0) {
  527. DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
  528. ret);
  529. return ret;
  530. }
  531. DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
  532. clk_get_rate(dsi->rx_esc_clk));
  533. /* Initiate the DSI packet transmision */
  534. nwl_dsi_begin_transmission(dsi);
  535. if (!wait_for_completion_timeout(&xfer.completed,
  536. NWL_DSI_MIPI_FIFO_TIMEOUT)) {
  537. DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n",
  538. xfer.cmd);
  539. ret = -ETIMEDOUT;
  540. } else {
  541. ret = xfer.status;
  542. }
  543. clk_disable_unprepare(dsi->rx_esc_clk);
  544. return ret;
  545. }
  546. static const struct mipi_dsi_host_ops nwl_dsi_host_ops = {
  547. .attach = nwl_dsi_host_attach,
  548. .transfer = nwl_dsi_host_transfer,
  549. };
  550. static irqreturn_t nwl_dsi_irq_handler(int irq, void *data)
  551. {
  552. u32 irq_status;
  553. struct nwl_dsi *dsi = data;
  554. irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
  555. if (irq_status & NWL_DSI_TX_FIFO_OVFLW)
  556. DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
  557. if (irq_status & NWL_DSI_HS_TX_TIMEOUT)
  558. DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
  559. if (irq_status & NWL_DSI_TX_PKT_DONE ||
  560. irq_status & NWL_DSI_RX_PKT_HDR_RCVD ||
  561. irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)
  562. nwl_dsi_finish_transmission(dsi, irq_status);
  563. return IRQ_HANDLED;
  564. }
  565. static int nwl_dsi_enable(struct nwl_dsi *dsi)
  566. {
  567. struct device *dev = dsi->dev;
  568. union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
  569. int ret;
  570. if (!dsi->lanes) {
  571. DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
  572. return -EINVAL;
  573. }
  574. ret = phy_init(dsi->phy);
  575. if (ret < 0) {
  576. DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret);
  577. return ret;
  578. }
  579. ret = phy_configure(dsi->phy, phy_cfg);
  580. if (ret < 0) {
  581. DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
  582. goto uninit_phy;
  583. }
  584. ret = clk_prepare_enable(dsi->tx_esc_clk);
  585. if (ret < 0) {
  586. DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
  587. ret);
  588. goto uninit_phy;
  589. }
  590. DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
  591. clk_get_rate(dsi->tx_esc_clk));
  592. ret = nwl_dsi_config_host(dsi);
  593. if (ret < 0) {
  594. DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret);
  595. goto disable_clock;
  596. }
  597. ret = nwl_dsi_config_dpi(dsi);
  598. if (ret < 0) {
  599. DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret);
  600. goto disable_clock;
  601. }
  602. ret = phy_power_on(dsi->phy);
  603. if (ret < 0) {
  604. DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret);
  605. goto disable_clock;
  606. }
  607. ret = nwl_dsi_init_interrupts(dsi);
  608. if (ret < 0)
  609. goto power_off_phy;
  610. return ret;
  611. power_off_phy:
  612. phy_power_off(dsi->phy);
  613. disable_clock:
  614. clk_disable_unprepare(dsi->tx_esc_clk);
  615. uninit_phy:
  616. phy_exit(dsi->phy);
  617. return ret;
  618. }
  619. static int nwl_dsi_disable(struct nwl_dsi *dsi)
  620. {
  621. struct device *dev = dsi->dev;
  622. DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n");
  623. phy_power_off(dsi->phy);
  624. phy_exit(dsi->phy);
  625. /* Disabling the clock before the phy breaks enabling dsi again */
  626. clk_disable_unprepare(dsi->tx_esc_clk);
  627. return 0;
  628. }
  629. static void
  630. nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
  631. struct drm_bridge_state *old_bridge_state)
  632. {
  633. struct nwl_dsi *dsi = bridge_to_dsi(bridge);
  634. int ret;
  635. nwl_dsi_disable(dsi);
  636. ret = reset_control_assert(dsi->rst_dpi);
  637. if (ret < 0) {
  638. DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);
  639. return;
  640. }
  641. ret = reset_control_assert(dsi->rst_byte);
  642. if (ret < 0) {
  643. DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);
  644. return;
  645. }
  646. ret = reset_control_assert(dsi->rst_esc);
  647. if (ret < 0) {
  648. DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);
  649. return;
  650. }
  651. ret = reset_control_assert(dsi->rst_pclk);
  652. if (ret < 0) {
  653. DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);
  654. return;
  655. }
  656. clk_disable_unprepare(dsi->core_clk);
  657. clk_disable_unprepare(dsi->lcdif_clk);
  658. pm_runtime_put(dsi->dev);
  659. }
  660. static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi,
  661. const struct drm_display_mode *mode,
  662. union phy_configure_opts *phy_opts)
  663. {
  664. unsigned long rate;
  665. int ret;
  666. if (dsi->lanes < 1 || dsi->lanes > 4)
  667. return -EINVAL;
  668. /*
  669. * So far the DPHY spec minimal timings work for both mixel
  670. * dphy and nwl dsi host
  671. */
  672. ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,
  673. mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
  674. &phy_opts->mipi_dphy);
  675. if (ret < 0)
  676. return ret;
  677. rate = clk_get_rate(dsi->tx_esc_clk);
  678. DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
  679. phy_opts->mipi_dphy.lp_clk_rate = rate;
  680. return 0;
  681. }
  682. static enum drm_mode_status
  683. nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge,
  684. const struct drm_display_info *info,
  685. const struct drm_display_mode *mode)
  686. {
  687. struct nwl_dsi *dsi = bridge_to_dsi(bridge);
  688. int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
  689. if (mode->clock * bpp > 15000000 * dsi->lanes)
  690. return MODE_CLOCK_HIGH;
  691. if (mode->clock * bpp < 80000 * dsi->lanes)
  692. return MODE_CLOCK_LOW;
  693. return MODE_OK;
  694. }
  695. static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge,
  696. struct drm_bridge_state *bridge_state,
  697. struct drm_crtc_state *crtc_state,
  698. struct drm_connector_state *conn_state)
  699. {
  700. struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
  701. /* At least LCDIF + NWL needs active high sync */
  702. adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  703. adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
  704. /* Do a full modeset if crtc_state->active is changed to be true. */
  705. if (crtc_state->active_changed && crtc_state->active)
  706. crtc_state->mode_changed = true;
  707. return 0;
  708. }
  709. static void
  710. nwl_dsi_bridge_mode_set(struct drm_bridge *bridge,
  711. const struct drm_display_mode *mode,
  712. const struct drm_display_mode *adjusted_mode)
  713. {
  714. struct nwl_dsi *dsi = bridge_to_dsi(bridge);
  715. struct device *dev = dsi->dev;
  716. union phy_configure_opts new_cfg;
  717. unsigned long phy_ref_rate;
  718. int ret;
  719. ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg);
  720. if (ret < 0)
  721. return;
  722. /*
  723. * If hs clock is unchanged, we're all good - all parameters are
  724. * derived from it atm.
  725. */
  726. if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate)
  727. return;
  728. phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
  729. DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
  730. /* Save the new desired phy config */
  731. memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
  732. memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode));
  733. drm_mode_debug_printmodeline(adjusted_mode);
  734. }
  735. static void
  736. nwl_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
  737. struct drm_bridge_state *old_bridge_state)
  738. {
  739. struct nwl_dsi *dsi = bridge_to_dsi(bridge);
  740. int ret;
  741. pm_runtime_get_sync(dsi->dev);
  742. if (clk_prepare_enable(dsi->lcdif_clk) < 0)
  743. return;
  744. if (clk_prepare_enable(dsi->core_clk) < 0)
  745. return;
  746. /* Step 1 from DSI reset-out instructions */
  747. ret = reset_control_deassert(dsi->rst_pclk);
  748. if (ret < 0) {
  749. DRM_DEV_ERROR(dsi->dev, "Failed to deassert PCLK: %d\n", ret);
  750. return;
  751. }
  752. /* Step 2 from DSI reset-out instructions */
  753. nwl_dsi_enable(dsi);
  754. /* Step 3 from DSI reset-out instructions */
  755. ret = reset_control_deassert(dsi->rst_esc);
  756. if (ret < 0) {
  757. DRM_DEV_ERROR(dsi->dev, "Failed to deassert ESC: %d\n", ret);
  758. return;
  759. }
  760. ret = reset_control_deassert(dsi->rst_byte);
  761. if (ret < 0) {
  762. DRM_DEV_ERROR(dsi->dev, "Failed to deassert BYTE: %d\n", ret);
  763. return;
  764. }
  765. }
  766. static void
  767. nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
  768. struct drm_bridge_state *old_bridge_state)
  769. {
  770. struct nwl_dsi *dsi = bridge_to_dsi(bridge);
  771. int ret;
  772. /* Step 5 from DSI reset-out instructions */
  773. ret = reset_control_deassert(dsi->rst_dpi);
  774. if (ret < 0)
  775. DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);
  776. }
  777. static int nwl_dsi_bridge_attach(struct drm_bridge *bridge,
  778. enum drm_bridge_attach_flags flags)
  779. {
  780. struct nwl_dsi *dsi = bridge_to_dsi(bridge);
  781. struct drm_bridge *panel_bridge;
  782. struct drm_panel *panel;
  783. int ret;
  784. ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel,
  785. &panel_bridge);
  786. if (ret)
  787. return ret;
  788. if (panel) {
  789. panel_bridge = drm_panel_bridge_add(panel);
  790. if (IS_ERR(panel_bridge))
  791. return PTR_ERR(panel_bridge);
  792. }
  793. dsi->panel_bridge = panel_bridge;
  794. if (!dsi->panel_bridge)
  795. return -EPROBE_DEFER;
  796. return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
  797. flags);
  798. }
  799. static void nwl_dsi_bridge_detach(struct drm_bridge *bridge)
  800. { struct nwl_dsi *dsi = bridge_to_dsi(bridge);
  801. drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0);
  802. }
  803. static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = {
  804. .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
  805. .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
  806. .atomic_reset = drm_atomic_helper_bridge_reset,
  807. .atomic_check = nwl_dsi_bridge_atomic_check,
  808. .atomic_pre_enable = nwl_dsi_bridge_atomic_pre_enable,
  809. .atomic_enable = nwl_dsi_bridge_atomic_enable,
  810. .atomic_disable = nwl_dsi_bridge_atomic_disable,
  811. .mode_set = nwl_dsi_bridge_mode_set,
  812. .mode_valid = nwl_dsi_bridge_mode_valid,
  813. .attach = nwl_dsi_bridge_attach,
  814. .detach = nwl_dsi_bridge_detach,
  815. };
  816. static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
  817. {
  818. struct platform_device *pdev = to_platform_device(dsi->dev);
  819. struct clk *clk;
  820. void __iomem *base;
  821. int ret;
  822. dsi->phy = devm_phy_get(dsi->dev, "dphy");
  823. if (IS_ERR(dsi->phy)) {
  824. ret = PTR_ERR(dsi->phy);
  825. if (ret != -EPROBE_DEFER)
  826. DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);
  827. return ret;
  828. }
  829. clk = devm_clk_get(dsi->dev, "lcdif");
  830. if (IS_ERR(clk)) {
  831. ret = PTR_ERR(clk);
  832. DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",
  833. ret);
  834. return ret;
  835. }
  836. dsi->lcdif_clk = clk;
  837. clk = devm_clk_get(dsi->dev, "core");
  838. if (IS_ERR(clk)) {
  839. ret = PTR_ERR(clk);
  840. DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",
  841. ret);
  842. return ret;
  843. }
  844. dsi->core_clk = clk;
  845. clk = devm_clk_get(dsi->dev, "phy_ref");
  846. if (IS_ERR(clk)) {
  847. ret = PTR_ERR(clk);
  848. DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",
  849. ret);
  850. return ret;
  851. }
  852. dsi->phy_ref_clk = clk;
  853. clk = devm_clk_get(dsi->dev, "rx_esc");
  854. if (IS_ERR(clk)) {
  855. ret = PTR_ERR(clk);
  856. DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",
  857. ret);
  858. return ret;
  859. }
  860. dsi->rx_esc_clk = clk;
  861. clk = devm_clk_get(dsi->dev, "tx_esc");
  862. if (IS_ERR(clk)) {
  863. ret = PTR_ERR(clk);
  864. DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",
  865. ret);
  866. return ret;
  867. }
  868. dsi->tx_esc_clk = clk;
  869. dsi->mux = devm_mux_control_get(dsi->dev, NULL);
  870. if (IS_ERR(dsi->mux)) {
  871. ret = PTR_ERR(dsi->mux);
  872. if (ret != -EPROBE_DEFER)
  873. DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
  874. return ret;
  875. }
  876. base = devm_platform_ioremap_resource(pdev, 0);
  877. if (IS_ERR(base))
  878. return PTR_ERR(base);
  879. dsi->regmap =
  880. devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);
  881. if (IS_ERR(dsi->regmap)) {
  882. ret = PTR_ERR(dsi->regmap);
  883. DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",
  884. ret);
  885. return ret;
  886. }
  887. dsi->irq = platform_get_irq(pdev, 0);
  888. if (dsi->irq < 0) {
  889. DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",
  890. dsi->irq);
  891. return dsi->irq;
  892. }
  893. dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");
  894. if (IS_ERR(dsi->rst_pclk)) {
  895. DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",
  896. PTR_ERR(dsi->rst_pclk));
  897. return PTR_ERR(dsi->rst_pclk);
  898. }
  899. dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");
  900. if (IS_ERR(dsi->rst_byte)) {
  901. DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",
  902. PTR_ERR(dsi->rst_byte));
  903. return PTR_ERR(dsi->rst_byte);
  904. }
  905. dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");
  906. if (IS_ERR(dsi->rst_esc)) {
  907. DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",
  908. PTR_ERR(dsi->rst_esc));
  909. return PTR_ERR(dsi->rst_esc);
  910. }
  911. dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");
  912. if (IS_ERR(dsi->rst_dpi)) {
  913. DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",
  914. PTR_ERR(dsi->rst_dpi));
  915. return PTR_ERR(dsi->rst_dpi);
  916. }
  917. return 0;
  918. }
  919. static int nwl_dsi_select_input(struct nwl_dsi *dsi)
  920. {
  921. struct device_node *remote;
  922. u32 use_dcss = 1;
  923. int ret;
  924. remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
  925. NWL_DSI_ENDPOINT_LCDIF);
  926. if (remote) {
  927. use_dcss = 0;
  928. } else {
  929. remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
  930. NWL_DSI_ENDPOINT_DCSS);
  931. if (!remote) {
  932. DRM_DEV_ERROR(dsi->dev,
  933. "No valid input endpoint found\n");
  934. return -EINVAL;
  935. }
  936. }
  937. DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
  938. (use_dcss) ? "DCSS" : "LCDIF");
  939. ret = mux_control_try_select(dsi->mux, use_dcss);
  940. if (ret < 0)
  941. DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
  942. of_node_put(remote);
  943. return ret;
  944. }
  945. static int nwl_dsi_deselect_input(struct nwl_dsi *dsi)
  946. {
  947. int ret;
  948. ret = mux_control_deselect(dsi->mux);
  949. if (ret < 0)
  950. DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);
  951. return ret;
  952. }
  953. static const struct drm_bridge_timings nwl_dsi_timings = {
  954. .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
  955. };
  956. static const struct of_device_id nwl_dsi_dt_ids[] = {
  957. { .compatible = "fsl,imx8mq-nwl-dsi", },
  958. { /* sentinel */ }
  959. };
  960. MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids);
  961. static const struct soc_device_attribute nwl_dsi_quirks_match[] = {
  962. { .soc_id = "i.MX8MQ", .revision = "2.0",
  963. .data = (void *)E11418_HS_MODE_QUIRK },
  964. { /* sentinel. */ },
  965. };
  966. static int nwl_dsi_probe(struct platform_device *pdev)
  967. {
  968. struct device *dev = &pdev->dev;
  969. const struct soc_device_attribute *attr;
  970. struct nwl_dsi *dsi;
  971. int ret;
  972. dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
  973. if (!dsi)
  974. return -ENOMEM;
  975. dsi->dev = dev;
  976. ret = nwl_dsi_parse_dt(dsi);
  977. if (ret)
  978. return ret;
  979. ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,
  980. dev_name(dev), dsi);
  981. if (ret < 0) {
  982. DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,
  983. ret);
  984. return ret;
  985. }
  986. dsi->dsi_host.ops = &nwl_dsi_host_ops;
  987. dsi->dsi_host.dev = dev;
  988. ret = mipi_dsi_host_register(&dsi->dsi_host);
  989. if (ret) {
  990. DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
  991. return ret;
  992. }
  993. attr = soc_device_match(nwl_dsi_quirks_match);
  994. if (attr)
  995. dsi->quirks = (uintptr_t)attr->data;
  996. dsi->bridge.driver_private = dsi;
  997. dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
  998. dsi->bridge.of_node = dev->of_node;
  999. dsi->bridge.timings = &nwl_dsi_timings;
  1000. dev_set_drvdata(dev, dsi);
  1001. pm_runtime_enable(dev);
  1002. ret = nwl_dsi_select_input(dsi);
  1003. if (ret < 0) {
  1004. pm_runtime_disable(dev);
  1005. mipi_dsi_host_unregister(&dsi->dsi_host);
  1006. return ret;
  1007. }
  1008. drm_bridge_add(&dsi->bridge);
  1009. return 0;
  1010. }
  1011. static int nwl_dsi_remove(struct platform_device *pdev)
  1012. {
  1013. struct nwl_dsi *dsi = platform_get_drvdata(pdev);
  1014. nwl_dsi_deselect_input(dsi);
  1015. mipi_dsi_host_unregister(&dsi->dsi_host);
  1016. drm_bridge_remove(&dsi->bridge);
  1017. pm_runtime_disable(&pdev->dev);
  1018. return 0;
  1019. }
  1020. static struct platform_driver nwl_dsi_driver = {
  1021. .probe = nwl_dsi_probe,
  1022. .remove = nwl_dsi_remove,
  1023. .driver = {
  1024. .of_match_table = nwl_dsi_dt_ids,
  1025. .name = DRV_NAME,
  1026. },
  1027. };
  1028. module_platform_driver(nwl_dsi_driver);
  1029. MODULE_AUTHOR("NXP Semiconductor");
  1030. MODULE_AUTHOR("Purism SPC");
  1031. MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");
  1032. MODULE_LICENSE("GPL"); /* GPLv2 or later */