chrontel-ch7033.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Chrontel CH7033 Video Encoder Driver
  4. *
  5. * Copyright (C) 2019,2020 Lubomir Rintel
  6. */
  7. #include <linux/gpio/consumer.h>
  8. #include <linux/module.h>
  9. #include <linux/regmap.h>
  10. #include <drm/drm_atomic_helper.h>
  11. #include <drm/drm_bridge.h>
  12. #include <drm/drm_edid.h>
  13. #include <drm/drm_of.h>
  14. #include <drm/drm_print.h>
  15. #include <drm/drm_probe_helper.h>
  16. /* Page 0, Register 0x07 */
  17. enum {
  18. DRI_PD = BIT(3),
  19. IO_PD = BIT(5),
  20. };
  21. /* Page 0, Register 0x08 */
  22. enum {
  23. DRI_PDDRI = GENMASK(7, 4),
  24. PDDAC = GENMASK(3, 1),
  25. PANEN = BIT(0),
  26. };
  27. /* Page 0, Register 0x09 */
  28. enum {
  29. DPD = BIT(7),
  30. GCKOFF = BIT(6),
  31. TV_BP = BIT(5),
  32. SCLPD = BIT(4),
  33. SDPD = BIT(3),
  34. VGA_PD = BIT(2),
  35. HDBKPD = BIT(1),
  36. HDMI_PD = BIT(0),
  37. };
  38. /* Page 0, Register 0x0a */
  39. enum {
  40. MEMINIT = BIT(7),
  41. MEMIDLE = BIT(6),
  42. MEMPD = BIT(5),
  43. STOP = BIT(4),
  44. LVDS_PD = BIT(3),
  45. HD_DVIB = BIT(2),
  46. HDCP_PD = BIT(1),
  47. MCU_PD = BIT(0),
  48. };
  49. /* Page 0, Register 0x18 */
  50. enum {
  51. IDF = GENMASK(7, 4),
  52. INTEN = BIT(3),
  53. SWAP = GENMASK(2, 0),
  54. };
  55. enum {
  56. BYTE_SWAP_RGB = 0,
  57. BYTE_SWAP_RBG = 1,
  58. BYTE_SWAP_GRB = 2,
  59. BYTE_SWAP_GBR = 3,
  60. BYTE_SWAP_BRG = 4,
  61. BYTE_SWAP_BGR = 5,
  62. };
  63. /* Page 0, Register 0x19 */
  64. enum {
  65. HPO_I = BIT(5),
  66. VPO_I = BIT(4),
  67. DEPO_I = BIT(3),
  68. CRYS_EN = BIT(2),
  69. GCLKFREQ = GENMASK(2, 0),
  70. };
  71. /* Page 0, Register 0x2e */
  72. enum {
  73. HFLIP = BIT(7),
  74. VFLIP = BIT(6),
  75. DEPO_O = BIT(5),
  76. HPO_O = BIT(4),
  77. VPO_O = BIT(3),
  78. TE = GENMASK(2, 0),
  79. };
  80. /* Page 0, Register 0x2b */
  81. enum {
  82. SWAPS = GENMASK(7, 4),
  83. VFMT = GENMASK(3, 0),
  84. };
  85. /* Page 0, Register 0x54 */
  86. enum {
  87. COMP_BP = BIT(7),
  88. DAC_EN_T = BIT(6),
  89. HWO_HDMI_HI = GENMASK(5, 3),
  90. HOO_HDMI_HI = GENMASK(2, 0),
  91. };
  92. /* Page 0, Register 0x57 */
  93. enum {
  94. FLDSEN = BIT(7),
  95. VWO_HDMI_HI = GENMASK(5, 3),
  96. VOO_HDMI_HI = GENMASK(2, 0),
  97. };
  98. /* Page 0, Register 0x7e */
  99. enum {
  100. HDMI_LVDS_SEL = BIT(7),
  101. DE_GEN = BIT(6),
  102. PWM_INDEX_HI = BIT(5),
  103. USE_DE = BIT(4),
  104. R_INT = GENMASK(3, 0),
  105. };
  106. /* Page 1, Register 0x07 */
  107. enum {
  108. BPCKSEL = BIT(7),
  109. DRI_CMFB_EN = BIT(6),
  110. CEC_PUEN = BIT(5),
  111. CEC_T = BIT(3),
  112. CKINV = BIT(2),
  113. CK_TVINV = BIT(1),
  114. DRI_CKS2 = BIT(0),
  115. };
  116. /* Page 1, Register 0x08 */
  117. enum {
  118. DACG = BIT(6),
  119. DACKTST = BIT(5),
  120. DEDGEB = BIT(4),
  121. SYO = BIT(3),
  122. DRI_IT_LVDS = GENMASK(2, 1),
  123. DISPON = BIT(0),
  124. };
  125. /* Page 1, Register 0x0c */
  126. enum {
  127. DRI_PLL_CP = GENMASK(7, 6),
  128. DRI_PLL_DIVSEL = BIT(5),
  129. DRI_PLL_N1_1 = BIT(4),
  130. DRI_PLL_N1_0 = BIT(3),
  131. DRI_PLL_N3_1 = BIT(2),
  132. DRI_PLL_N3_0 = BIT(1),
  133. DRI_PLL_CKTSTEN = BIT(0),
  134. };
  135. /* Page 1, Register 0x6b */
  136. enum {
  137. VCO3CS = GENMASK(7, 6),
  138. ICPGBK2_0 = GENMASK(5, 3),
  139. DRI_VCO357SC = BIT(2),
  140. PDPLL2 = BIT(1),
  141. DRI_PD_SER = BIT(0),
  142. };
  143. /* Page 1, Register 0x6c */
  144. enum {
  145. PLL2N11 = GENMASK(7, 4),
  146. PLL2N5_4 = BIT(3),
  147. PLL2N5_TOP = BIT(2),
  148. DRI_PLL_PD = BIT(1),
  149. PD_I2CM = BIT(0),
  150. };
  151. /* Page 3, Register 0x28 */
  152. enum {
  153. DIFF_EN = GENMASK(7, 6),
  154. CORREC_EN = GENMASK(5, 4),
  155. VGACLK_BP = BIT(3),
  156. HM_LV_SEL = BIT(2),
  157. HD_VGA_SEL = BIT(1),
  158. };
  159. /* Page 3, Register 0x2a */
  160. enum {
  161. LVDSCLK_BP = BIT(7),
  162. HDTVCLK_BP = BIT(6),
  163. HDMICLK_BP = BIT(5),
  164. HDTV_BP = BIT(4),
  165. HDMI_BP = BIT(3),
  166. THRWL = GENMASK(2, 0),
  167. };
  168. /* Page 4, Register 0x52 */
  169. enum {
  170. PGM_ARSTB = BIT(7),
  171. MCU_ARSTB = BIT(6),
  172. MCU_RETB = BIT(2),
  173. RESETIB = BIT(1),
  174. RESETDB = BIT(0),
  175. };
  176. struct ch7033_priv {
  177. struct regmap *regmap;
  178. struct drm_bridge *next_bridge;
  179. struct drm_bridge bridge;
  180. struct drm_connector connector;
  181. };
  182. #define conn_to_ch7033_priv(x) \
  183. container_of(x, struct ch7033_priv, connector)
  184. #define bridge_to_ch7033_priv(x) \
  185. container_of(x, struct ch7033_priv, bridge)
  186. static enum drm_connector_status ch7033_connector_detect(
  187. struct drm_connector *connector, bool force)
  188. {
  189. struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
  190. return drm_bridge_detect(priv->next_bridge);
  191. }
  192. static const struct drm_connector_funcs ch7033_connector_funcs = {
  193. .reset = drm_atomic_helper_connector_reset,
  194. .fill_modes = drm_helper_probe_single_connector_modes,
  195. .detect = ch7033_connector_detect,
  196. .destroy = drm_connector_cleanup,
  197. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  198. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  199. };
  200. static int ch7033_connector_get_modes(struct drm_connector *connector)
  201. {
  202. struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
  203. struct edid *edid;
  204. int ret;
  205. edid = drm_bridge_get_edid(priv->next_bridge, connector);
  206. drm_connector_update_edid_property(connector, edid);
  207. if (edid) {
  208. ret = drm_add_edid_modes(connector, edid);
  209. kfree(edid);
  210. } else {
  211. ret = drm_add_modes_noedid(connector, 1920, 1080);
  212. drm_set_preferred_mode(connector, 1024, 768);
  213. }
  214. return ret;
  215. }
  216. static struct drm_encoder *ch7033_connector_best_encoder(
  217. struct drm_connector *connector)
  218. {
  219. struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
  220. return priv->bridge.encoder;
  221. }
  222. static const struct drm_connector_helper_funcs ch7033_connector_helper_funcs = {
  223. .get_modes = ch7033_connector_get_modes,
  224. .best_encoder = ch7033_connector_best_encoder,
  225. };
  226. static void ch7033_hpd_event(void *arg, enum drm_connector_status status)
  227. {
  228. struct ch7033_priv *priv = arg;
  229. if (priv->bridge.dev)
  230. drm_helper_hpd_irq_event(priv->connector.dev);
  231. }
  232. static int ch7033_bridge_attach(struct drm_bridge *bridge,
  233. enum drm_bridge_attach_flags flags)
  234. {
  235. struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
  236. struct drm_connector *connector = &priv->connector;
  237. int ret;
  238. ret = drm_bridge_attach(bridge->encoder, priv->next_bridge, bridge,
  239. DRM_BRIDGE_ATTACH_NO_CONNECTOR);
  240. if (ret)
  241. return ret;
  242. if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
  243. return 0;
  244. if (priv->next_bridge->ops & DRM_BRIDGE_OP_DETECT) {
  245. connector->polled = DRM_CONNECTOR_POLL_HPD;
  246. } else {
  247. connector->polled = DRM_CONNECTOR_POLL_CONNECT |
  248. DRM_CONNECTOR_POLL_DISCONNECT;
  249. }
  250. if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) {
  251. drm_bridge_hpd_enable(priv->next_bridge, ch7033_hpd_event,
  252. priv);
  253. }
  254. drm_connector_helper_add(connector,
  255. &ch7033_connector_helper_funcs);
  256. ret = drm_connector_init_with_ddc(bridge->dev, &priv->connector,
  257. &ch7033_connector_funcs,
  258. priv->next_bridge->type,
  259. priv->next_bridge->ddc);
  260. if (ret) {
  261. DRM_ERROR("Failed to initialize connector\n");
  262. return ret;
  263. }
  264. return drm_connector_attach_encoder(&priv->connector, bridge->encoder);
  265. }
  266. static void ch7033_bridge_detach(struct drm_bridge *bridge)
  267. {
  268. struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
  269. if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD)
  270. drm_bridge_hpd_disable(priv->next_bridge);
  271. drm_connector_cleanup(&priv->connector);
  272. }
  273. static enum drm_mode_status ch7033_bridge_mode_valid(struct drm_bridge *bridge,
  274. const struct drm_display_info *info,
  275. const struct drm_display_mode *mode)
  276. {
  277. if (mode->clock > 165000)
  278. return MODE_CLOCK_HIGH;
  279. if (mode->hdisplay >= 1920)
  280. return MODE_BAD_HVALUE;
  281. if (mode->vdisplay >= 1080)
  282. return MODE_BAD_VVALUE;
  283. return MODE_OK;
  284. }
  285. static void ch7033_bridge_disable(struct drm_bridge *bridge)
  286. {
  287. struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
  288. regmap_write(priv->regmap, 0x03, 0x04);
  289. regmap_update_bits(priv->regmap, 0x52, RESETDB, 0x00);
  290. }
  291. static void ch7033_bridge_enable(struct drm_bridge *bridge)
  292. {
  293. struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
  294. regmap_write(priv->regmap, 0x03, 0x04);
  295. regmap_update_bits(priv->regmap, 0x52, RESETDB, RESETDB);
  296. }
  297. static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
  298. const struct drm_display_mode *mode,
  299. const struct drm_display_mode *adjusted_mode)
  300. {
  301. struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
  302. int hbporch = mode->hsync_start - mode->hdisplay;
  303. int hsynclen = mode->hsync_end - mode->hsync_start;
  304. int vbporch = mode->vsync_start - mode->vdisplay;
  305. int vsynclen = mode->vsync_end - mode->vsync_start;
  306. /*
  307. * Page 4
  308. */
  309. regmap_write(priv->regmap, 0x03, 0x04);
  310. /* Turn everything off to set all the registers to their defaults. */
  311. regmap_write(priv->regmap, 0x52, 0x00);
  312. /* Bring I/O block up. */
  313. regmap_write(priv->regmap, 0x52, RESETIB);
  314. /*
  315. * Page 0
  316. */
  317. regmap_write(priv->regmap, 0x03, 0x00);
  318. /* Bring up parts we need from the power down. */
  319. regmap_update_bits(priv->regmap, 0x07, DRI_PD | IO_PD, 0);
  320. regmap_update_bits(priv->regmap, 0x08, DRI_PDDRI | PDDAC | PANEN, 0);
  321. regmap_update_bits(priv->regmap, 0x09, DPD | GCKOFF |
  322. HDMI_PD | VGA_PD, 0);
  323. regmap_update_bits(priv->regmap, 0x0a, HD_DVIB, 0);
  324. /* Horizontal input timing. */
  325. regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 |
  326. (mode->hdisplay >> 8));
  327. regmap_write(priv->regmap, 0x0c, mode->hdisplay);
  328. regmap_write(priv->regmap, 0x0d, mode->htotal);
  329. regmap_write(priv->regmap, 0x0e, (hsynclen >> 8) << 3 |
  330. (hbporch >> 8));
  331. regmap_write(priv->regmap, 0x0f, hbporch);
  332. regmap_write(priv->regmap, 0x10, hsynclen);
  333. /* Vertical input timing. */
  334. regmap_write(priv->regmap, 0x11, (mode->vtotal >> 8) << 3 |
  335. (mode->vdisplay >> 8));
  336. regmap_write(priv->regmap, 0x12, mode->vdisplay);
  337. regmap_write(priv->regmap, 0x13, mode->vtotal);
  338. regmap_write(priv->regmap, 0x14, ((vsynclen >> 8) << 3) |
  339. (vbporch >> 8));
  340. regmap_write(priv->regmap, 0x15, vbporch);
  341. regmap_write(priv->regmap, 0x16, vsynclen);
  342. /* Input color swap. */
  343. regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
  344. /* Input clock and sync polarity. */
  345. regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
  346. regmap_update_bits(priv->regmap, 0x19, HPO_I | VPO_I | GCLKFREQ,
  347. (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0 |
  348. (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0 |
  349. mode->clock >> 16);
  350. regmap_write(priv->regmap, 0x1a, mode->clock >> 8);
  351. regmap_write(priv->regmap, 0x1b, mode->clock);
  352. /* Horizontal output timing. */
  353. regmap_write(priv->regmap, 0x1f, (mode->htotal >> 8) << 3 |
  354. (mode->hdisplay >> 8));
  355. regmap_write(priv->regmap, 0x20, mode->hdisplay);
  356. regmap_write(priv->regmap, 0x21, mode->htotal);
  357. /* Vertical output timing. */
  358. regmap_write(priv->regmap, 0x25, (mode->vtotal >> 8) << 3 |
  359. (mode->vdisplay >> 8));
  360. regmap_write(priv->regmap, 0x26, mode->vdisplay);
  361. regmap_write(priv->regmap, 0x27, mode->vtotal);
  362. /* VGA channel bypass */
  363. regmap_update_bits(priv->regmap, 0x2b, VFMT, 9);
  364. /* Output sync polarity. */
  365. regmap_update_bits(priv->regmap, 0x2e, HPO_O | VPO_O,
  366. (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0 |
  367. (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0);
  368. /* HDMI horizontal output timing. */
  369. regmap_update_bits(priv->regmap, 0x54, HWO_HDMI_HI | HOO_HDMI_HI,
  370. (hsynclen >> 8) << 3 |
  371. (hbporch >> 8));
  372. regmap_write(priv->regmap, 0x55, hbporch);
  373. regmap_write(priv->regmap, 0x56, hsynclen);
  374. /* HDMI vertical output timing. */
  375. regmap_update_bits(priv->regmap, 0x57, VWO_HDMI_HI | VOO_HDMI_HI,
  376. (vsynclen >> 8) << 3 |
  377. (vbporch >> 8));
  378. regmap_write(priv->regmap, 0x58, vbporch);
  379. regmap_write(priv->regmap, 0x59, vsynclen);
  380. /* Pick HDMI, not LVDS. */
  381. regmap_update_bits(priv->regmap, 0x7e, HDMI_LVDS_SEL, HDMI_LVDS_SEL);
  382. /*
  383. * Page 1
  384. */
  385. regmap_write(priv->regmap, 0x03, 0x01);
  386. /* No idea what these do, but VGA is wobbly and blinky without them. */
  387. regmap_update_bits(priv->regmap, 0x07, CKINV, CKINV);
  388. regmap_update_bits(priv->regmap, 0x08, DISPON, DISPON);
  389. /* DRI PLL */
  390. regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_DIVSEL, DRI_PLL_DIVSEL);
  391. if (mode->clock <= 40000) {
  392. regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 |
  393. DRI_PLL_N1_0 |
  394. DRI_PLL_N3_1 |
  395. DRI_PLL_N3_0,
  396. 0);
  397. } else if (mode->clock < 80000) {
  398. regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 |
  399. DRI_PLL_N1_0 |
  400. DRI_PLL_N3_1 |
  401. DRI_PLL_N3_0,
  402. DRI_PLL_N3_0 |
  403. DRI_PLL_N1_0);
  404. } else {
  405. regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 |
  406. DRI_PLL_N1_0 |
  407. DRI_PLL_N3_1 |
  408. DRI_PLL_N3_0,
  409. DRI_PLL_N3_1 |
  410. DRI_PLL_N1_1);
  411. }
  412. /* This seems to be color calibration for VGA. */
  413. regmap_write(priv->regmap, 0x64, 0x29); /* LSB Blue */
  414. regmap_write(priv->regmap, 0x65, 0x29); /* LSB Green */
  415. regmap_write(priv->regmap, 0x66, 0x29); /* LSB Red */
  416. regmap_write(priv->regmap, 0x67, 0x00); /* MSB Blue */
  417. regmap_write(priv->regmap, 0x68, 0x00); /* MSB Green */
  418. regmap_write(priv->regmap, 0x69, 0x00); /* MSB Red */
  419. regmap_update_bits(priv->regmap, 0x6b, DRI_PD_SER, 0x00);
  420. regmap_update_bits(priv->regmap, 0x6c, DRI_PLL_PD, 0x00);
  421. /*
  422. * Page 3
  423. */
  424. regmap_write(priv->regmap, 0x03, 0x03);
  425. /* More bypasses and apparently another HDMI/LVDS selector. */
  426. regmap_update_bits(priv->regmap, 0x28, VGACLK_BP | HM_LV_SEL,
  427. VGACLK_BP | HM_LV_SEL);
  428. regmap_update_bits(priv->regmap, 0x2a, HDMICLK_BP | HDMI_BP,
  429. HDMICLK_BP | HDMI_BP);
  430. /*
  431. * Page 4
  432. */
  433. regmap_write(priv->regmap, 0x03, 0x04);
  434. /* Output clock. */
  435. regmap_write(priv->regmap, 0x10, mode->clock >> 16);
  436. regmap_write(priv->regmap, 0x11, mode->clock >> 8);
  437. regmap_write(priv->regmap, 0x12, mode->clock);
  438. }
  439. static const struct drm_bridge_funcs ch7033_bridge_funcs = {
  440. .attach = ch7033_bridge_attach,
  441. .detach = ch7033_bridge_detach,
  442. .mode_valid = ch7033_bridge_mode_valid,
  443. .disable = ch7033_bridge_disable,
  444. .enable = ch7033_bridge_enable,
  445. .mode_set = ch7033_bridge_mode_set,
  446. };
  447. static const struct regmap_config ch7033_regmap_config = {
  448. .reg_bits = 8,
  449. .val_bits = 8,
  450. .max_register = 0x7f,
  451. };
  452. static int ch7033_probe(struct i2c_client *client,
  453. const struct i2c_device_id *id)
  454. {
  455. struct device *dev = &client->dev;
  456. struct ch7033_priv *priv;
  457. unsigned int val;
  458. int ret;
  459. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  460. if (!priv)
  461. return -ENOMEM;
  462. dev_set_drvdata(dev, priv);
  463. ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1, NULL,
  464. &priv->next_bridge);
  465. if (ret)
  466. return ret;
  467. priv->regmap = devm_regmap_init_i2c(client, &ch7033_regmap_config);
  468. if (IS_ERR(priv->regmap)) {
  469. dev_err(&client->dev, "regmap init failed\n");
  470. return PTR_ERR(priv->regmap);
  471. }
  472. ret = regmap_read(priv->regmap, 0x00, &val);
  473. if (ret < 0) {
  474. dev_err(&client->dev, "error reading the model id: %d\n", ret);
  475. return ret;
  476. }
  477. if ((val & 0xf7) != 0x56) {
  478. dev_err(&client->dev, "the device is not a ch7033\n");
  479. return -ENODEV;
  480. }
  481. regmap_write(priv->regmap, 0x03, 0x04);
  482. ret = regmap_read(priv->regmap, 0x51, &val);
  483. if (ret < 0) {
  484. dev_err(&client->dev, "error reading the model id: %d\n", ret);
  485. return ret;
  486. }
  487. if ((val & 0x0f) != 3) {
  488. dev_err(&client->dev, "unknown revision %u\n", val);
  489. return -ENODEV;
  490. }
  491. INIT_LIST_HEAD(&priv->bridge.list);
  492. priv->bridge.funcs = &ch7033_bridge_funcs;
  493. priv->bridge.of_node = dev->of_node;
  494. drm_bridge_add(&priv->bridge);
  495. dev_info(dev, "Chrontel CH7033 Video Encoder\n");
  496. return 0;
  497. }
  498. static int ch7033_remove(struct i2c_client *client)
  499. {
  500. struct device *dev = &client->dev;
  501. struct ch7033_priv *priv = dev_get_drvdata(dev);
  502. drm_bridge_remove(&priv->bridge);
  503. return 0;
  504. }
  505. static const struct of_device_id ch7033_dt_ids[] = {
  506. { .compatible = "chrontel,ch7033", },
  507. { }
  508. };
  509. MODULE_DEVICE_TABLE(of, ch7033_dt_ids);
  510. static const struct i2c_device_id ch7033_ids[] = {
  511. { "ch7033", 0 },
  512. { }
  513. };
  514. MODULE_DEVICE_TABLE(i2c, ch7033_ids);
  515. static struct i2c_driver ch7033_driver = {
  516. .probe = ch7033_probe,
  517. .remove = ch7033_remove,
  518. .driver = {
  519. .name = "ch7033",
  520. .of_match_table = of_match_ptr(ch7033_dt_ids),
  521. },
  522. .id_table = ch7033_ids,
  523. };
  524. module_i2c_driver(ch7033_driver);
  525. MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
  526. MODULE_DESCRIPTION("Chrontel CH7033 Video Encoder Driver");
  527. MODULE_LICENSE("GPL v2");