cdns-mhdp8546-core.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Cadence MHDP8546 DP bridge driver.
  4. *
  5. * Copyright (C) 2020 Cadence Design Systems, Inc.
  6. *
  7. * Author: Quentin Schulz <quentin.schulz@free-electrons.com>
  8. * Swapnil Jakhade <sjakhade@cadence.com>
  9. */
  10. #ifndef CDNS_MHDP8546_CORE_H
  11. #define CDNS_MHDP8546_CORE_H
  12. #include <linux/bits.h>
  13. #include <linux/mutex.h>
  14. #include <linux/spinlock.h>
  15. #include <drm/drm_bridge.h>
  16. #include <drm/drm_connector.h>
  17. #include <drm/drm_dp_helper.h>
  18. struct clk;
  19. struct device;
  20. struct phy;
  21. /* Register offsets */
  22. #define CDNS_APB_CTRL 0x00000
  23. #define CDNS_CPU_STALL BIT(3)
  24. #define CDNS_MAILBOX_FULL 0x00008
  25. #define CDNS_MAILBOX_EMPTY 0x0000c
  26. #define CDNS_MAILBOX_TX_DATA 0x00010
  27. #define CDNS_MAILBOX_RX_DATA 0x00014
  28. #define CDNS_KEEP_ALIVE 0x00018
  29. #define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0)
  30. #define CDNS_VER_L 0x0001C
  31. #define CDNS_VER_H 0x00020
  32. #define CDNS_LIB_L_ADDR 0x00024
  33. #define CDNS_LIB_H_ADDR 0x00028
  34. #define CDNS_MB_INT_MASK 0x00034
  35. #define CDNS_MB_INT_STATUS 0x00038
  36. #define CDNS_SW_CLK_L 0x0003c
  37. #define CDNS_SW_CLK_H 0x00040
  38. #define CDNS_SW_EVENT0 0x00044
  39. #define CDNS_DPTX_HPD BIT(0)
  40. #define CDNS_SW_EVENT1 0x00048
  41. #define CDNS_SW_EVENT2 0x0004c
  42. #define CDNS_SW_EVENT3 0x00050
  43. #define CDNS_APB_INT_MASK 0x0006C
  44. #define CDNS_APB_INT_MASK_MAILBOX_INT BIT(0)
  45. #define CDNS_APB_INT_MASK_SW_EVENT_INT BIT(1)
  46. #define CDNS_APB_INT_STATUS 0x00070
  47. #define CDNS_DPTX_CAR 0x00904
  48. #define CDNS_VIF_CLK_EN BIT(0)
  49. #define CDNS_VIF_CLK_RSTN BIT(1)
  50. #define CDNS_SOURCE_VIDEO_IF(s) (0x00b00 + ((s) * 0x20))
  51. #define CDNS_BND_HSYNC2VSYNC(s) (CDNS_SOURCE_VIDEO_IF(s) + \
  52. 0x00)
  53. #define CDNS_IP_DTCT_WIN GENMASK(11, 0)
  54. #define CDNS_IP_DET_INTERLACE_FORMAT BIT(12)
  55. #define CDNS_IP_BYPASS_V_INTERFACE BIT(13)
  56. #define CDNS_HSYNC2VSYNC_POL_CTRL(s) (CDNS_SOURCE_VIDEO_IF(s) + \
  57. 0x10)
  58. #define CDNS_H2V_HSYNC_POL_ACTIVE_LOW BIT(1)
  59. #define CDNS_H2V_VSYNC_POL_ACTIVE_LOW BIT(2)
  60. #define CDNS_DPTX_PHY_CONFIG 0x02000
  61. #define CDNS_PHY_TRAINING_EN BIT(0)
  62. #define CDNS_PHY_TRAINING_TYPE(x) (((x) & GENMASK(3, 0)) << 1)
  63. #define CDNS_PHY_SCRAMBLER_BYPASS BIT(5)
  64. #define CDNS_PHY_ENCODER_BYPASS BIT(6)
  65. #define CDNS_PHY_SKEW_BYPASS BIT(7)
  66. #define CDNS_PHY_TRAINING_AUTO BIT(8)
  67. #define CDNS_PHY_LANE0_SKEW(x) (((x) & GENMASK(2, 0)) << 9)
  68. #define CDNS_PHY_LANE1_SKEW(x) (((x) & GENMASK(2, 0)) << 12)
  69. #define CDNS_PHY_LANE2_SKEW(x) (((x) & GENMASK(2, 0)) << 15)
  70. #define CDNS_PHY_LANE3_SKEW(x) (((x) & GENMASK(2, 0)) << 18)
  71. #define CDNS_PHY_COMMON_CONFIG (CDNS_PHY_LANE1_SKEW(1) | \
  72. CDNS_PHY_LANE2_SKEW(2) | \
  73. CDNS_PHY_LANE3_SKEW(3))
  74. #define CDNS_PHY_10BIT_EN BIT(21)
  75. #define CDNS_DP_FRAMER_GLOBAL_CONFIG 0x02200
  76. #define CDNS_DP_NUM_LANES(x) ((x) - 1)
  77. #define CDNS_DP_MST_EN BIT(2)
  78. #define CDNS_DP_FRAMER_EN BIT(3)
  79. #define CDNS_DP_RATE_GOVERNOR_EN BIT(4)
  80. #define CDNS_DP_NO_VIDEO_MODE BIT(5)
  81. #define CDNS_DP_DISABLE_PHY_RST BIT(6)
  82. #define CDNS_DP_WR_FAILING_EDGE_VSYNC BIT(7)
  83. #define CDNS_DP_FRAMER_TU 0x02208
  84. #define CDNS_DP_FRAMER_TU_SIZE(x) (((x) & GENMASK(6, 0)) << 8)
  85. #define CDNS_DP_FRAMER_TU_VS(x) ((x) & GENMASK(5, 0))
  86. #define CDNS_DP_FRAMER_TU_CNT_RST_EN BIT(15)
  87. #define CDNS_DP_MTPH_CONTROL 0x02264
  88. #define CDNS_DP_MTPH_ECF_EN BIT(0)
  89. #define CDNS_DP_MTPH_ACT_EN BIT(1)
  90. #define CDNS_DP_MTPH_LVP_EN BIT(2)
  91. #define CDNS_DP_MTPH_STATUS 0x0226C
  92. #define CDNS_DP_MTPH_ACT_STATUS BIT(0)
  93. #define CDNS_DP_LANE_EN 0x02300
  94. #define CDNS_DP_LANE_EN_LANES(x) GENMASK((x) - 1, 0)
  95. #define CDNS_DP_ENHNCD 0x02304
  96. #define CDNS_DPTX_STREAM(s) (0x03000 + (s) * 0x80)
  97. #define CDNS_DP_MSA_HORIZONTAL_0(s) (CDNS_DPTX_STREAM(s) + 0x00)
  98. #define CDNS_DP_MSAH0_H_TOTAL(x) (x)
  99. #define CDNS_DP_MSAH0_HSYNC_START(x) ((x) << 16)
  100. #define CDNS_DP_MSA_HORIZONTAL_1(s) (CDNS_DPTX_STREAM(s) + 0x04)
  101. #define CDNS_DP_MSAH1_HSYNC_WIDTH(x) (x)
  102. #define CDNS_DP_MSAH1_HSYNC_POL_LOW BIT(15)
  103. #define CDNS_DP_MSAH1_HDISP_WIDTH(x) ((x) << 16)
  104. #define CDNS_DP_MSA_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x08)
  105. #define CDNS_DP_MSAV0_V_TOTAL(x) (x)
  106. #define CDNS_DP_MSAV0_VSYNC_START(x) ((x) << 16)
  107. #define CDNS_DP_MSA_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x0c)
  108. #define CDNS_DP_MSAV1_VSYNC_WIDTH(x) (x)
  109. #define CDNS_DP_MSAV1_VSYNC_POL_LOW BIT(15)
  110. #define CDNS_DP_MSAV1_VDISP_WIDTH(x) ((x) << 16)
  111. #define CDNS_DP_MSA_MISC(s) (CDNS_DPTX_STREAM(s) + 0x10)
  112. #define CDNS_DP_STREAM_CONFIG(s) (CDNS_DPTX_STREAM(s) + 0x14)
  113. #define CDNS_DP_STREAM_CONFIG_2(s) (CDNS_DPTX_STREAM(s) + 0x2c)
  114. #define CDNS_DP_SC2_TU_VS_DIFF(x) ((x) << 8)
  115. #define CDNS_DP_HORIZONTAL(s) (CDNS_DPTX_STREAM(s) + 0x30)
  116. #define CDNS_DP_H_HSYNC_WIDTH(x) (x)
  117. #define CDNS_DP_H_H_TOTAL(x) ((x) << 16)
  118. #define CDNS_DP_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x34)
  119. #define CDNS_DP_V0_VHEIGHT(x) (x)
  120. #define CDNS_DP_V0_VSTART(x) ((x) << 16)
  121. #define CDNS_DP_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x38)
  122. #define CDNS_DP_V1_VTOTAL(x) (x)
  123. #define CDNS_DP_V1_VTOTAL_EVEN BIT(16)
  124. #define CDNS_DP_MST_SLOT_ALLOCATE(s) (CDNS_DPTX_STREAM(s) + 0x44)
  125. #define CDNS_DP_S_ALLOC_START_SLOT(x) (x)
  126. #define CDNS_DP_S_ALLOC_END_SLOT(x) ((x) << 8)
  127. #define CDNS_DP_RATE_GOVERNING(s) (CDNS_DPTX_STREAM(s) + 0x48)
  128. #define CDNS_DP_RG_TARG_AV_SLOTS_Y(x) (x)
  129. #define CDNS_DP_RG_TARG_AV_SLOTS_X(x) ((x) << 4)
  130. #define CDNS_DP_RG_ENABLE BIT(10)
  131. #define CDNS_DP_FRAMER_PXL_REPR(s) (CDNS_DPTX_STREAM(s) + 0x4c)
  132. #define CDNS_DP_FRAMER_6_BPC BIT(0)
  133. #define CDNS_DP_FRAMER_8_BPC BIT(1)
  134. #define CDNS_DP_FRAMER_10_BPC BIT(2)
  135. #define CDNS_DP_FRAMER_12_BPC BIT(3)
  136. #define CDNS_DP_FRAMER_16_BPC BIT(4)
  137. #define CDNS_DP_FRAMER_PXL_FORMAT 0x8
  138. #define CDNS_DP_FRAMER_RGB BIT(0)
  139. #define CDNS_DP_FRAMER_YCBCR444 BIT(1)
  140. #define CDNS_DP_FRAMER_YCBCR422 BIT(2)
  141. #define CDNS_DP_FRAMER_YCBCR420 BIT(3)
  142. #define CDNS_DP_FRAMER_Y_ONLY BIT(4)
  143. #define CDNS_DP_FRAMER_SP(s) (CDNS_DPTX_STREAM(s) + 0x50)
  144. #define CDNS_DP_FRAMER_VSYNC_POL_LOW BIT(0)
  145. #define CDNS_DP_FRAMER_HSYNC_POL_LOW BIT(1)
  146. #define CDNS_DP_FRAMER_INTERLACE BIT(2)
  147. #define CDNS_DP_LINE_THRESH(s) (CDNS_DPTX_STREAM(s) + 0x64)
  148. #define CDNS_DP_ACTIVE_LINE_THRESH(x) (x)
  149. #define CDNS_DP_VB_ID(s) (CDNS_DPTX_STREAM(s) + 0x68)
  150. #define CDNS_DP_VB_ID_INTERLACED BIT(2)
  151. #define CDNS_DP_VB_ID_COMPRESSED BIT(6)
  152. #define CDNS_DP_FRONT_BACK_PORCH(s) (CDNS_DPTX_STREAM(s) + 0x78)
  153. #define CDNS_DP_BACK_PORCH(x) (x)
  154. #define CDNS_DP_FRONT_PORCH(x) ((x) << 16)
  155. #define CDNS_DP_BYTE_COUNT(s) (CDNS_DPTX_STREAM(s) + 0x7c)
  156. #define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT 16
  157. /* mailbox */
  158. #define MAILBOX_RETRY_US 1000
  159. #define MAILBOX_TIMEOUT_US 2000000
  160. #define MB_OPCODE_ID 0
  161. #define MB_MODULE_ID 1
  162. #define MB_SIZE_MSB_ID 2
  163. #define MB_SIZE_LSB_ID 3
  164. #define MB_DATA_ID 4
  165. #define MB_MODULE_ID_DP_TX 0x01
  166. #define MB_MODULE_ID_HDCP_TX 0x07
  167. #define MB_MODULE_ID_HDCP_RX 0x08
  168. #define MB_MODULE_ID_HDCP_GENERAL 0x09
  169. #define MB_MODULE_ID_GENERAL 0x0a
  170. /* firmware and opcodes */
  171. #define FW_NAME "cadence/mhdp8546.bin"
  172. #define CDNS_MHDP_IMEM 0x10000
  173. #define GENERAL_MAIN_CONTROL 0x01
  174. #define GENERAL_TEST_ECHO 0x02
  175. #define GENERAL_BUS_SETTINGS 0x03
  176. #define GENERAL_TEST_ACCESS 0x04
  177. #define GENERAL_REGISTER_READ 0x07
  178. #define DPTX_SET_POWER_MNG 0x00
  179. #define DPTX_GET_EDID 0x02
  180. #define DPTX_READ_DPCD 0x03
  181. #define DPTX_WRITE_DPCD 0x04
  182. #define DPTX_ENABLE_EVENT 0x05
  183. #define DPTX_WRITE_REGISTER 0x06
  184. #define DPTX_READ_REGISTER 0x07
  185. #define DPTX_WRITE_FIELD 0x08
  186. #define DPTX_READ_EVENT 0x0a
  187. #define DPTX_GET_LAST_AUX_STAUS 0x0e
  188. #define DPTX_HPD_STATE 0x11
  189. #define DPTX_ADJUST_LT 0x12
  190. #define FW_STANDBY 0
  191. #define FW_ACTIVE 1
  192. /* HPD */
  193. #define DPTX_READ_EVENT_HPD_TO_HIGH BIT(0)
  194. #define DPTX_READ_EVENT_HPD_TO_LOW BIT(1)
  195. #define DPTX_READ_EVENT_HPD_PULSE BIT(2)
  196. #define DPTX_READ_EVENT_HPD_STATE BIT(3)
  197. /* general */
  198. #define CDNS_DP_TRAINING_PATTERN_4 0x7
  199. #define CDNS_KEEP_ALIVE_TIMEOUT 2000
  200. #define CDNS_VOLT_SWING(x) ((x) & GENMASK(1, 0))
  201. #define CDNS_FORCE_VOLT_SWING BIT(2)
  202. #define CDNS_PRE_EMPHASIS(x) ((x) & GENMASK(1, 0))
  203. #define CDNS_FORCE_PRE_EMPHASIS BIT(2)
  204. #define CDNS_SUPPORT_TPS(x) BIT((x) - 1)
  205. #define CDNS_FAST_LINK_TRAINING BIT(0)
  206. #define CDNS_LANE_MAPPING_TYPE_C_LANE_0(x) ((x) & GENMASK(1, 0))
  207. #define CDNS_LANE_MAPPING_TYPE_C_LANE_1(x) ((x) & GENMASK(3, 2))
  208. #define CDNS_LANE_MAPPING_TYPE_C_LANE_2(x) ((x) & GENMASK(5, 4))
  209. #define CDNS_LANE_MAPPING_TYPE_C_LANE_3(x) ((x) & GENMASK(7, 6))
  210. #define CDNS_LANE_MAPPING_NORMAL 0xe4
  211. #define CDNS_LANE_MAPPING_FLIPPED 0x1b
  212. #define CDNS_DP_MAX_NUM_LANES 4
  213. #define CDNS_DP_TEST_VSC_SDP BIT(6) /* 1.3+ */
  214. #define CDNS_DP_TEST_COLOR_FORMAT_RAW_Y_ONLY BIT(7)
  215. #define CDNS_MHDP_MAX_STREAMS 4
  216. #define DP_LINK_CAP_ENHANCED_FRAMING BIT(0)
  217. struct cdns_mhdp_link {
  218. unsigned char revision;
  219. unsigned int rate;
  220. unsigned int num_lanes;
  221. unsigned long capabilities;
  222. };
  223. struct cdns_mhdp_host {
  224. unsigned int link_rate;
  225. u8 lanes_cnt;
  226. u8 volt_swing;
  227. u8 pre_emphasis;
  228. u8 pattern_supp;
  229. u8 lane_mapping;
  230. bool fast_link;
  231. bool enhanced;
  232. bool scrambler;
  233. bool ssc;
  234. };
  235. struct cdns_mhdp_sink {
  236. unsigned int link_rate;
  237. u8 lanes_cnt;
  238. u8 pattern_supp;
  239. bool fast_link;
  240. bool enhanced;
  241. bool ssc;
  242. };
  243. struct cdns_mhdp_display_fmt {
  244. u32 color_format;
  245. u32 bpc;
  246. bool y_only;
  247. };
  248. /*
  249. * These enums present MHDP hw initialization state
  250. * Legal state transitions are:
  251. * MHDP_HW_READY <-> MHDP_HW_STOPPED
  252. */
  253. enum mhdp_hw_state {
  254. MHDP_HW_READY = 1, /* HW ready, FW active */
  255. MHDP_HW_STOPPED /* Driver removal FW to be stopped */
  256. };
  257. struct cdns_mhdp_device;
  258. struct mhdp_platform_ops {
  259. int (*init)(struct cdns_mhdp_device *mhdp);
  260. void (*exit)(struct cdns_mhdp_device *mhdp);
  261. void (*enable)(struct cdns_mhdp_device *mhdp);
  262. void (*disable)(struct cdns_mhdp_device *mhdp);
  263. };
  264. struct cdns_mhdp_bridge_state {
  265. struct drm_bridge_state base;
  266. struct drm_display_mode *current_mode;
  267. };
  268. struct cdns_mhdp_platform_info {
  269. const struct drm_bridge_timings *timings;
  270. const struct mhdp_platform_ops *ops;
  271. };
  272. #define to_cdns_mhdp_bridge_state(s) \
  273. container_of(s, struct cdns_mhdp_bridge_state, base)
  274. struct cdns_mhdp_device {
  275. void __iomem *regs;
  276. void __iomem *j721e_regs;
  277. struct device *dev;
  278. struct clk *clk;
  279. struct phy *phy;
  280. const struct cdns_mhdp_platform_info *info;
  281. /* This is to protect mailbox communications with the firmware */
  282. struct mutex mbox_mutex;
  283. /*
  284. * "link_mutex" protects the access to all the link parameters
  285. * including the link training process. Link training will be
  286. * invoked both from threaded interrupt handler and from atomic
  287. * callbacks when link_up is not set. So this mutex protects
  288. * flags such as link_up, bridge_enabled, link.num_lanes,
  289. * link.rate etc.
  290. */
  291. struct mutex link_mutex;
  292. struct drm_connector connector;
  293. struct drm_bridge bridge;
  294. struct cdns_mhdp_link link;
  295. struct drm_dp_aux aux;
  296. struct cdns_mhdp_host host;
  297. struct cdns_mhdp_sink sink;
  298. struct cdns_mhdp_display_fmt display_fmt;
  299. u8 stream_id;
  300. bool link_up;
  301. bool plugged;
  302. /*
  303. * "start_lock" protects the access to bridge_attached and
  304. * hw_state data members that control the delayed firmware
  305. * loading and attaching the bridge. They are accessed from
  306. * both the DRM core and cdns_mhdp_fw_cb(). In most cases just
  307. * protecting the data members is enough, but the irq mask
  308. * setting needs to be protected when enabling the FW.
  309. */
  310. spinlock_t start_lock;
  311. bool bridge_attached;
  312. bool bridge_enabled;
  313. enum mhdp_hw_state hw_state;
  314. wait_queue_head_t fw_load_wq;
  315. /* Work struct to schedule a uevent on link train failure */
  316. struct work_struct modeset_retry_work;
  317. };
  318. #define connector_to_mhdp(x) container_of(x, struct cdns_mhdp_device, connector)
  319. #define bridge_to_mhdp(x) container_of(x, struct cdns_mhdp_device, bridge)
  320. #endif