analogix_dp_core.c 46 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Analogix DP (Display Port) core interface driver.
  4. *
  5. * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  6. * Author: Jingoo Han <jg1.han@samsung.com>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/component.h>
  10. #include <linux/err.h>
  11. #include <linux/gpio/consumer.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/iopoll.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/phy/phy.h>
  18. #include <linux/platform_device.h>
  19. #include <drm/bridge/analogix_dp.h>
  20. #include <drm/drm_atomic.h>
  21. #include <drm/drm_atomic_helper.h>
  22. #include <drm/drm_bridge.h>
  23. #include <drm/drm_crtc.h>
  24. #include <drm/drm_device.h>
  25. #include <drm/drm_panel.h>
  26. #include <drm/drm_print.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "analogix_dp_core.h"
  29. #include "analogix_dp_reg.h"
  30. #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
  31. static const bool verify_fast_training;
  32. struct bridge_init {
  33. struct i2c_client *client;
  34. struct device_node *node;
  35. };
  36. static int analogix_dp_init_dp(struct analogix_dp_device *dp)
  37. {
  38. int ret;
  39. analogix_dp_reset(dp);
  40. analogix_dp_swreset(dp);
  41. analogix_dp_init_analog_param(dp);
  42. analogix_dp_init_interrupt(dp);
  43. /* SW defined function Normal operation */
  44. analogix_dp_enable_sw_function(dp);
  45. analogix_dp_config_interrupt(dp);
  46. ret = analogix_dp_init_analog_func(dp);
  47. if (ret)
  48. return ret;
  49. analogix_dp_init_hpd(dp);
  50. analogix_dp_init_aux(dp);
  51. return 0;
  52. }
  53. static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
  54. {
  55. int timeout_loop = 0;
  56. while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
  57. if (analogix_dp_get_plug_in_status(dp) == 0)
  58. return 0;
  59. timeout_loop++;
  60. usleep_range(1000, 1100);
  61. }
  62. /*
  63. * Some edp screen do not have hpd signal, so we can't just
  64. * return failed when hpd plug in detect failed, DT property
  65. * "force-hpd" would indicate whether driver need this.
  66. */
  67. if (!dp->force_hpd)
  68. return -ETIMEDOUT;
  69. /*
  70. * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
  71. * will not work, so we need to give a force hpd action to
  72. * set HPD_STATUS manually.
  73. */
  74. dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
  75. analogix_dp_force_hpd(dp);
  76. if (analogix_dp_get_plug_in_status(dp) != 0) {
  77. dev_err(dp->dev, "failed to get hpd plug in status\n");
  78. return -EINVAL;
  79. }
  80. dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
  81. return 0;
  82. }
  83. static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
  84. {
  85. unsigned char psr_version;
  86. int ret;
  87. ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
  88. if (ret != 1) {
  89. dev_err(dp->dev, "failed to get PSR version, disable it\n");
  90. return false;
  91. }
  92. dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
  93. return psr_version & DP_PSR_IS_SUPPORTED;
  94. }
  95. static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
  96. {
  97. unsigned char psr_en;
  98. int ret;
  99. /* Disable psr function */
  100. ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
  101. if (ret != 1) {
  102. dev_err(dp->dev, "failed to get psr config\n");
  103. goto end;
  104. }
  105. psr_en &= ~DP_PSR_ENABLE;
  106. ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
  107. if (ret != 1) {
  108. dev_err(dp->dev, "failed to disable panel psr\n");
  109. goto end;
  110. }
  111. /* Main-Link transmitter remains active during PSR active states */
  112. psr_en = DP_PSR_CRC_VERIFICATION;
  113. ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
  114. if (ret != 1) {
  115. dev_err(dp->dev, "failed to set panel psr\n");
  116. goto end;
  117. }
  118. /* Enable psr function */
  119. psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
  120. ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
  121. if (ret != 1) {
  122. dev_err(dp->dev, "failed to set panel psr\n");
  123. goto end;
  124. }
  125. analogix_dp_enable_psr_crc(dp);
  126. dp->psr_supported = true;
  127. return 0;
  128. end:
  129. dev_err(dp->dev, "enable psr fail, force to disable psr\n");
  130. return ret;
  131. }
  132. static int
  133. analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
  134. bool enable)
  135. {
  136. u8 data;
  137. int ret;
  138. ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
  139. if (ret != 1)
  140. return ret;
  141. if (enable)
  142. ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
  143. DP_LANE_COUNT_ENHANCED_FRAME_EN |
  144. DPCD_LANE_COUNT_SET(data));
  145. else
  146. ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
  147. DPCD_LANE_COUNT_SET(data));
  148. return ret < 0 ? ret : 0;
  149. }
  150. static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
  151. u8 *enhanced_mode_support)
  152. {
  153. u8 data;
  154. int ret;
  155. ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
  156. if (ret != 1) {
  157. *enhanced_mode_support = 0;
  158. return ret;
  159. }
  160. *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
  161. return 0;
  162. }
  163. static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
  164. {
  165. u8 data;
  166. int ret;
  167. ret = analogix_dp_is_enhanced_mode_available(dp, &data);
  168. if (ret < 0)
  169. return ret;
  170. ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
  171. if (ret < 0)
  172. return ret;
  173. analogix_dp_enable_enhanced_mode(dp, data);
  174. return 0;
  175. }
  176. static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
  177. {
  178. int ret;
  179. analogix_dp_set_training_pattern(dp, DP_NONE);
  180. ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
  181. DP_TRAINING_PATTERN_DISABLE);
  182. return ret < 0 ? ret : 0;
  183. }
  184. static void
  185. analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
  186. int pre_emphasis, int lane)
  187. {
  188. switch (lane) {
  189. case 0:
  190. analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
  191. break;
  192. case 1:
  193. analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
  194. break;
  195. case 2:
  196. analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
  197. break;
  198. case 3:
  199. analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
  200. break;
  201. }
  202. }
  203. static int analogix_dp_link_start(struct analogix_dp_device *dp)
  204. {
  205. u8 buf[4];
  206. int lane, lane_count, pll_tries, retval;
  207. lane_count = dp->link_train.lane_count;
  208. dp->link_train.lt_state = CLOCK_RECOVERY;
  209. dp->link_train.eq_loop = 0;
  210. for (lane = 0; lane < lane_count; lane++)
  211. dp->link_train.cr_loop[lane] = 0;
  212. /* Set link rate and count as you want to establish*/
  213. analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
  214. analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
  215. /* Setup RX configuration */
  216. buf[0] = dp->link_train.link_rate;
  217. buf[1] = dp->link_train.lane_count;
  218. retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
  219. if (retval < 0)
  220. return retval;
  221. /* set enhanced mode if available */
  222. retval = analogix_dp_set_enhanced_mode(dp);
  223. if (retval < 0) {
  224. dev_err(dp->dev, "failed to set enhance mode\n");
  225. return retval;
  226. }
  227. /* Set TX pre-emphasis to minimum */
  228. for (lane = 0; lane < lane_count; lane++)
  229. analogix_dp_set_lane_lane_pre_emphasis(dp,
  230. PRE_EMPHASIS_LEVEL_0, lane);
  231. /* Wait for PLL lock */
  232. pll_tries = 0;
  233. while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
  234. if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
  235. dev_err(dp->dev, "Wait for PLL lock timed out\n");
  236. return -ETIMEDOUT;
  237. }
  238. pll_tries++;
  239. usleep_range(90, 120);
  240. }
  241. /* Set training pattern 1 */
  242. analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
  243. /* Set RX training pattern */
  244. retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
  245. DP_LINK_SCRAMBLING_DISABLE |
  246. DP_TRAINING_PATTERN_1);
  247. if (retval < 0)
  248. return retval;
  249. for (lane = 0; lane < lane_count; lane++)
  250. buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
  251. DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
  252. retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
  253. lane_count);
  254. if (retval < 0)
  255. return retval;
  256. return 0;
  257. }
  258. static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
  259. {
  260. int shift = (lane & 1) * 4;
  261. u8 link_value = link_status[lane >> 1];
  262. return (link_value >> shift) & 0xf;
  263. }
  264. static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
  265. {
  266. int lane;
  267. u8 lane_status;
  268. for (lane = 0; lane < lane_count; lane++) {
  269. lane_status = analogix_dp_get_lane_status(link_status, lane);
  270. if ((lane_status & DP_LANE_CR_DONE) == 0)
  271. return -EINVAL;
  272. }
  273. return 0;
  274. }
  275. static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
  276. int lane_count)
  277. {
  278. int lane;
  279. u8 lane_status;
  280. if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
  281. return -EINVAL;
  282. for (lane = 0; lane < lane_count; lane++) {
  283. lane_status = analogix_dp_get_lane_status(link_status, lane);
  284. lane_status &= DP_CHANNEL_EQ_BITS;
  285. if (lane_status != DP_CHANNEL_EQ_BITS)
  286. return -EINVAL;
  287. }
  288. return 0;
  289. }
  290. static unsigned char
  291. analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
  292. {
  293. int shift = (lane & 1) * 4;
  294. u8 link_value = adjust_request[lane >> 1];
  295. return (link_value >> shift) & 0x3;
  296. }
  297. static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
  298. u8 adjust_request[2],
  299. int lane)
  300. {
  301. int shift = (lane & 1) * 4;
  302. u8 link_value = adjust_request[lane >> 1];
  303. return ((link_value >> shift) & 0xc) >> 2;
  304. }
  305. static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
  306. u8 training_lane_set, int lane)
  307. {
  308. switch (lane) {
  309. case 0:
  310. analogix_dp_set_lane0_link_training(dp, training_lane_set);
  311. break;
  312. case 1:
  313. analogix_dp_set_lane1_link_training(dp, training_lane_set);
  314. break;
  315. case 2:
  316. analogix_dp_set_lane2_link_training(dp, training_lane_set);
  317. break;
  318. case 3:
  319. analogix_dp_set_lane3_link_training(dp, training_lane_set);
  320. break;
  321. }
  322. }
  323. static unsigned int
  324. analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
  325. int lane)
  326. {
  327. u32 reg;
  328. switch (lane) {
  329. case 0:
  330. reg = analogix_dp_get_lane0_link_training(dp);
  331. break;
  332. case 1:
  333. reg = analogix_dp_get_lane1_link_training(dp);
  334. break;
  335. case 2:
  336. reg = analogix_dp_get_lane2_link_training(dp);
  337. break;
  338. case 3:
  339. reg = analogix_dp_get_lane3_link_training(dp);
  340. break;
  341. default:
  342. WARN_ON(1);
  343. return 0;
  344. }
  345. return reg;
  346. }
  347. static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
  348. {
  349. analogix_dp_training_pattern_dis(dp);
  350. analogix_dp_set_enhanced_mode(dp);
  351. dp->link_train.lt_state = FAILED;
  352. }
  353. static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
  354. u8 adjust_request[2])
  355. {
  356. int lane, lane_count;
  357. u8 voltage_swing, pre_emphasis, training_lane;
  358. lane_count = dp->link_train.lane_count;
  359. for (lane = 0; lane < lane_count; lane++) {
  360. voltage_swing = analogix_dp_get_adjust_request_voltage(
  361. adjust_request, lane);
  362. pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
  363. adjust_request, lane);
  364. training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
  365. DPCD_PRE_EMPHASIS_SET(pre_emphasis);
  366. if (voltage_swing == VOLTAGE_LEVEL_3)
  367. training_lane |= DP_TRAIN_MAX_SWING_REACHED;
  368. if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
  369. training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  370. dp->link_train.training_lane[lane] = training_lane;
  371. }
  372. }
  373. static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
  374. {
  375. int lane, lane_count, retval;
  376. u8 voltage_swing, pre_emphasis, training_lane;
  377. u8 link_status[2], adjust_request[2];
  378. usleep_range(100, 101);
  379. lane_count = dp->link_train.lane_count;
  380. retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
  381. if (retval < 0)
  382. return retval;
  383. retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
  384. adjust_request, 2);
  385. if (retval < 0)
  386. return retval;
  387. if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
  388. /* set training pattern 2 for EQ */
  389. analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
  390. retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
  391. DP_LINK_SCRAMBLING_DISABLE |
  392. DP_TRAINING_PATTERN_2);
  393. if (retval < 0)
  394. return retval;
  395. dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
  396. dp->link_train.lt_state = EQUALIZER_TRAINING;
  397. } else {
  398. for (lane = 0; lane < lane_count; lane++) {
  399. training_lane = analogix_dp_get_lane_link_training(
  400. dp, lane);
  401. voltage_swing = analogix_dp_get_adjust_request_voltage(
  402. adjust_request, lane);
  403. pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
  404. adjust_request, lane);
  405. if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
  406. voltage_swing &&
  407. DPCD_PRE_EMPHASIS_GET(training_lane) ==
  408. pre_emphasis)
  409. dp->link_train.cr_loop[lane]++;
  410. if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
  411. voltage_swing == VOLTAGE_LEVEL_3 ||
  412. pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
  413. dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
  414. dp->link_train.cr_loop[lane],
  415. voltage_swing, pre_emphasis);
  416. analogix_dp_reduce_link_rate(dp);
  417. return -EIO;
  418. }
  419. }
  420. }
  421. analogix_dp_get_adjust_training_lane(dp, adjust_request);
  422. for (lane = 0; lane < lane_count; lane++)
  423. analogix_dp_set_lane_link_training(dp,
  424. dp->link_train.training_lane[lane], lane);
  425. retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
  426. dp->link_train.training_lane, lane_count);
  427. if (retval < 0)
  428. return retval;
  429. return 0;
  430. }
  431. static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
  432. {
  433. int lane, lane_count, retval;
  434. u32 reg;
  435. u8 link_align, link_status[2], adjust_request[2];
  436. usleep_range(400, 401);
  437. lane_count = dp->link_train.lane_count;
  438. retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
  439. if (retval < 0)
  440. return retval;
  441. if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
  442. analogix_dp_reduce_link_rate(dp);
  443. return -EIO;
  444. }
  445. retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
  446. adjust_request, 2);
  447. if (retval < 0)
  448. return retval;
  449. retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
  450. &link_align);
  451. if (retval < 0)
  452. return retval;
  453. analogix_dp_get_adjust_training_lane(dp, adjust_request);
  454. if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
  455. /* traing pattern Set to Normal */
  456. retval = analogix_dp_training_pattern_dis(dp);
  457. if (retval < 0)
  458. return retval;
  459. dev_dbg(dp->dev, "Link Training success!\n");
  460. analogix_dp_get_link_bandwidth(dp, &reg);
  461. dp->link_train.link_rate = reg;
  462. dev_dbg(dp->dev, "final bandwidth = %.2x\n",
  463. dp->link_train.link_rate);
  464. analogix_dp_get_lane_count(dp, &reg);
  465. dp->link_train.lane_count = reg;
  466. dev_dbg(dp->dev, "final lane count = %.2x\n",
  467. dp->link_train.lane_count);
  468. dp->link_train.lt_state = FINISHED;
  469. return 0;
  470. }
  471. /* not all locked */
  472. dp->link_train.eq_loop++;
  473. if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
  474. dev_err(dp->dev, "EQ Max loop\n");
  475. analogix_dp_reduce_link_rate(dp);
  476. return -EIO;
  477. }
  478. for (lane = 0; lane < lane_count; lane++)
  479. analogix_dp_set_lane_link_training(dp,
  480. dp->link_train.training_lane[lane], lane);
  481. retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
  482. dp->link_train.training_lane, lane_count);
  483. if (retval < 0)
  484. return retval;
  485. return 0;
  486. }
  487. static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
  488. u8 *bandwidth)
  489. {
  490. u8 data;
  491. /*
  492. * For DP rev.1.1, Maximum link rate of Main Link lanes
  493. * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
  494. * For DP rev.1.2, Maximum link rate of Main Link lanes
  495. * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
  496. */
  497. drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
  498. *bandwidth = data;
  499. }
  500. static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
  501. u8 *lane_count)
  502. {
  503. u8 data;
  504. /*
  505. * For DP rev.1.1, Maximum number of Main Link lanes
  506. * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
  507. */
  508. drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
  509. *lane_count = DPCD_MAX_LANE_COUNT(data);
  510. }
  511. static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
  512. u32 max_lanes, u32 max_rate)
  513. {
  514. int retval = 0;
  515. bool training_finished = false;
  516. /*
  517. * MACRO_RST must be applied after the PLL_LOCK to avoid
  518. * the DP inter pair skew issue for at least 10 us
  519. */
  520. analogix_dp_reset_macro(dp);
  521. /* Initialize by reading RX's DPCD */
  522. analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
  523. analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
  524. if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
  525. (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
  526. (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
  527. dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
  528. dp->link_train.link_rate);
  529. dp->link_train.link_rate = DP_LINK_BW_1_62;
  530. }
  531. if (dp->link_train.lane_count == 0) {
  532. dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
  533. dp->link_train.lane_count);
  534. dp->link_train.lane_count = (u8)LANE_COUNT1;
  535. }
  536. /* Setup TX lane count & rate */
  537. if (dp->link_train.lane_count > max_lanes)
  538. dp->link_train.lane_count = max_lanes;
  539. if (dp->link_train.link_rate > max_rate)
  540. dp->link_train.link_rate = max_rate;
  541. /* All DP analog module power up */
  542. analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
  543. dp->link_train.lt_state = START;
  544. /* Process here */
  545. while (!retval && !training_finished) {
  546. switch (dp->link_train.lt_state) {
  547. case START:
  548. retval = analogix_dp_link_start(dp);
  549. if (retval)
  550. dev_err(dp->dev, "LT link start failed!\n");
  551. break;
  552. case CLOCK_RECOVERY:
  553. retval = analogix_dp_process_clock_recovery(dp);
  554. if (retval)
  555. dev_err(dp->dev, "LT CR failed!\n");
  556. break;
  557. case EQUALIZER_TRAINING:
  558. retval = analogix_dp_process_equalizer_training(dp);
  559. if (retval)
  560. dev_err(dp->dev, "LT EQ failed!\n");
  561. break;
  562. case FINISHED:
  563. training_finished = 1;
  564. break;
  565. case FAILED:
  566. return -EREMOTEIO;
  567. }
  568. }
  569. if (retval)
  570. dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
  571. return retval;
  572. }
  573. static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
  574. {
  575. int i, ret;
  576. u8 link_align, link_status[2];
  577. enum pll_status status;
  578. analogix_dp_reset_macro(dp);
  579. analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
  580. analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
  581. for (i = 0; i < dp->link_train.lane_count; i++) {
  582. analogix_dp_set_lane_link_training(dp,
  583. dp->link_train.training_lane[i], i);
  584. }
  585. ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
  586. status != PLL_UNLOCKED, 120,
  587. 120 * DP_TIMEOUT_LOOP_COUNT);
  588. if (ret) {
  589. DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
  590. return ret;
  591. }
  592. /* source Set training pattern 1 */
  593. analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
  594. /* From DP spec, pattern must be on-screen for a minimum 500us */
  595. usleep_range(500, 600);
  596. analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
  597. /* From DP spec, pattern must be on-screen for a minimum 500us */
  598. usleep_range(500, 600);
  599. /* TODO: enhanced_mode?*/
  600. analogix_dp_set_training_pattern(dp, DP_NONE);
  601. /*
  602. * Useful for debugging issues with fast link training, disable for more
  603. * speed
  604. */
  605. if (verify_fast_training) {
  606. ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
  607. &link_align);
  608. if (ret < 0) {
  609. DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
  610. ret);
  611. return ret;
  612. }
  613. ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
  614. 2);
  615. if (ret < 0) {
  616. DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
  617. ret);
  618. return ret;
  619. }
  620. if (analogix_dp_clock_recovery_ok(link_status,
  621. dp->link_train.lane_count)) {
  622. DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
  623. analogix_dp_reduce_link_rate(dp);
  624. return -EIO;
  625. }
  626. if (analogix_dp_channel_eq_ok(link_status, link_align,
  627. dp->link_train.lane_count)) {
  628. DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
  629. analogix_dp_reduce_link_rate(dp);
  630. return -EIO;
  631. }
  632. }
  633. return 0;
  634. }
  635. static int analogix_dp_train_link(struct analogix_dp_device *dp)
  636. {
  637. if (dp->fast_train_enable)
  638. return analogix_dp_fast_link_train(dp);
  639. return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
  640. dp->video_info.max_link_rate);
  641. }
  642. static int analogix_dp_config_video(struct analogix_dp_device *dp)
  643. {
  644. int timeout_loop = 0;
  645. int done_count = 0;
  646. analogix_dp_config_video_slave_mode(dp);
  647. analogix_dp_set_video_color_format(dp);
  648. if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
  649. dev_err(dp->dev, "PLL is not locked yet.\n");
  650. return -EINVAL;
  651. }
  652. for (;;) {
  653. timeout_loop++;
  654. if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
  655. break;
  656. if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
  657. dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
  658. return -ETIMEDOUT;
  659. }
  660. usleep_range(1000, 1001);
  661. }
  662. /* Set to use the register calculated M/N video */
  663. analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
  664. /* For video bist, Video timing must be generated by register */
  665. analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
  666. /* Disable video mute */
  667. analogix_dp_enable_video_mute(dp, 0);
  668. /* Configure video slave mode */
  669. analogix_dp_enable_video_master(dp, 0);
  670. /* Enable video */
  671. analogix_dp_start_video(dp);
  672. timeout_loop = 0;
  673. for (;;) {
  674. timeout_loop++;
  675. if (analogix_dp_is_video_stream_on(dp) == 0) {
  676. done_count++;
  677. if (done_count > 10)
  678. break;
  679. } else if (done_count) {
  680. done_count = 0;
  681. }
  682. if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
  683. dev_warn(dp->dev,
  684. "Ignoring timeout of video streamclk ok\n");
  685. break;
  686. }
  687. usleep_range(1000, 1001);
  688. }
  689. return 0;
  690. }
  691. static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
  692. bool enable)
  693. {
  694. u8 data;
  695. int ret;
  696. if (enable) {
  697. analogix_dp_enable_scrambling(dp);
  698. ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
  699. &data);
  700. if (ret != 1)
  701. return ret;
  702. ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
  703. (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
  704. } else {
  705. analogix_dp_disable_scrambling(dp);
  706. ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
  707. &data);
  708. if (ret != 1)
  709. return ret;
  710. ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
  711. (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
  712. }
  713. return ret < 0 ? ret : 0;
  714. }
  715. static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
  716. {
  717. struct analogix_dp_device *dp = arg;
  718. irqreturn_t ret = IRQ_NONE;
  719. enum dp_irq_type irq_type;
  720. irq_type = analogix_dp_get_irq_type(dp);
  721. if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
  722. analogix_dp_mute_hpd_interrupt(dp);
  723. ret = IRQ_WAKE_THREAD;
  724. }
  725. return ret;
  726. }
  727. static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
  728. {
  729. struct analogix_dp_device *dp = arg;
  730. enum dp_irq_type irq_type;
  731. irq_type = analogix_dp_get_irq_type(dp);
  732. if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
  733. irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
  734. dev_dbg(dp->dev, "Detected cable status changed!\n");
  735. if (dp->drm_dev)
  736. drm_helper_hpd_irq_event(dp->drm_dev);
  737. }
  738. if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
  739. analogix_dp_clear_hotplug_interrupts(dp);
  740. analogix_dp_unmute_hpd_interrupt(dp);
  741. }
  742. return IRQ_HANDLED;
  743. }
  744. static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
  745. {
  746. int ret;
  747. u8 spread;
  748. ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
  749. if (ret != 1) {
  750. dev_err(dp->dev, "failed to read downspread %d\n", ret);
  751. return ret;
  752. }
  753. dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
  754. dev_dbg(dp->dev, "fast link training %s\n",
  755. dp->fast_train_enable ? "supported" : "unsupported");
  756. return 0;
  757. }
  758. static int analogix_dp_commit(struct analogix_dp_device *dp)
  759. {
  760. int ret;
  761. /* Keep the panel disabled while we configure video */
  762. if (dp->plat_data->panel) {
  763. if (drm_panel_disable(dp->plat_data->panel))
  764. DRM_ERROR("failed to disable the panel\n");
  765. }
  766. ret = analogix_dp_train_link(dp);
  767. if (ret) {
  768. dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
  769. return ret;
  770. }
  771. ret = analogix_dp_enable_scramble(dp, 1);
  772. if (ret < 0) {
  773. dev_err(dp->dev, "can not enable scramble\n");
  774. return ret;
  775. }
  776. analogix_dp_init_video(dp);
  777. ret = analogix_dp_config_video(dp);
  778. if (ret) {
  779. dev_err(dp->dev, "unable to config video\n");
  780. return ret;
  781. }
  782. /* Safe to enable the panel now */
  783. if (dp->plat_data->panel) {
  784. ret = drm_panel_enable(dp->plat_data->panel);
  785. if (ret) {
  786. DRM_ERROR("failed to enable the panel\n");
  787. return ret;
  788. }
  789. }
  790. /* Check whether panel supports fast training */
  791. ret = analogix_dp_fast_link_train_detection(dp);
  792. if (ret)
  793. return ret;
  794. if (analogix_dp_detect_sink_psr(dp)) {
  795. ret = analogix_dp_enable_sink_psr(dp);
  796. if (ret)
  797. return ret;
  798. }
  799. return ret;
  800. }
  801. static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
  802. {
  803. struct dp_sdp psr_vsc;
  804. int ret;
  805. u8 sink;
  806. ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
  807. if (ret != 1)
  808. DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
  809. else if (sink == DP_PSR_SINK_ACTIVE_RFB)
  810. return 0;
  811. /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
  812. memset(&psr_vsc, 0, sizeof(psr_vsc));
  813. psr_vsc.sdp_header.HB0 = 0;
  814. psr_vsc.sdp_header.HB1 = 0x7;
  815. psr_vsc.sdp_header.HB2 = 0x2;
  816. psr_vsc.sdp_header.HB3 = 0x8;
  817. psr_vsc.db[0] = 0;
  818. psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
  819. ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
  820. if (!ret)
  821. analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
  822. return ret;
  823. }
  824. static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
  825. {
  826. struct dp_sdp psr_vsc;
  827. int ret;
  828. u8 sink;
  829. analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
  830. ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
  831. if (ret != 1) {
  832. DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
  833. return ret;
  834. }
  835. ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
  836. if (ret != 1) {
  837. DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
  838. return ret;
  839. } else if (sink == DP_PSR_SINK_INACTIVE) {
  840. DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
  841. return 0;
  842. }
  843. ret = analogix_dp_train_link(dp);
  844. if (ret) {
  845. DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
  846. return ret;
  847. }
  848. /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
  849. memset(&psr_vsc, 0, sizeof(psr_vsc));
  850. psr_vsc.sdp_header.HB0 = 0;
  851. psr_vsc.sdp_header.HB1 = 0x7;
  852. psr_vsc.sdp_header.HB2 = 0x2;
  853. psr_vsc.sdp_header.HB3 = 0x8;
  854. psr_vsc.db[0] = 0;
  855. psr_vsc.db[1] = 0;
  856. return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
  857. }
  858. /*
  859. * This function is a bit of a catch-all for panel preparation, hopefully
  860. * simplifying the logic of functions that need to prepare/unprepare the panel
  861. * below.
  862. *
  863. * If @prepare is true, this function will prepare the panel. Conversely, if it
  864. * is false, the panel will be unprepared.
  865. *
  866. * If @is_modeset_prepare is true, the function will disregard the current state
  867. * of the panel and either prepare/unprepare the panel based on @prepare. Once
  868. * it finishes, it will update dp->panel_is_modeset to reflect the current state
  869. * of the panel.
  870. */
  871. static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
  872. bool prepare, bool is_modeset_prepare)
  873. {
  874. int ret = 0;
  875. if (!dp->plat_data->panel)
  876. return 0;
  877. mutex_lock(&dp->panel_lock);
  878. /*
  879. * Exit early if this is a temporary prepare/unprepare and we're already
  880. * modeset (since we neither want to prepare twice or unprepare early).
  881. */
  882. if (dp->panel_is_modeset && !is_modeset_prepare)
  883. goto out;
  884. if (prepare)
  885. ret = drm_panel_prepare(dp->plat_data->panel);
  886. else
  887. ret = drm_panel_unprepare(dp->plat_data->panel);
  888. if (ret)
  889. goto out;
  890. if (is_modeset_prepare)
  891. dp->panel_is_modeset = prepare;
  892. out:
  893. mutex_unlock(&dp->panel_lock);
  894. return ret;
  895. }
  896. static int analogix_dp_get_modes(struct drm_connector *connector)
  897. {
  898. struct analogix_dp_device *dp = to_dp(connector);
  899. struct edid *edid;
  900. int ret, num_modes = 0;
  901. if (dp->plat_data->panel) {
  902. num_modes += drm_panel_get_modes(dp->plat_data->panel, connector);
  903. } else {
  904. ret = analogix_dp_prepare_panel(dp, true, false);
  905. if (ret) {
  906. DRM_ERROR("Failed to prepare panel (%d)\n", ret);
  907. return 0;
  908. }
  909. pm_runtime_get_sync(dp->dev);
  910. edid = drm_get_edid(connector, &dp->aux.ddc);
  911. pm_runtime_put(dp->dev);
  912. if (edid) {
  913. drm_connector_update_edid_property(&dp->connector,
  914. edid);
  915. num_modes += drm_add_edid_modes(&dp->connector, edid);
  916. kfree(edid);
  917. }
  918. ret = analogix_dp_prepare_panel(dp, false, false);
  919. if (ret)
  920. DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
  921. }
  922. if (dp->plat_data->get_modes)
  923. num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
  924. return num_modes;
  925. }
  926. static struct drm_encoder *
  927. analogix_dp_best_encoder(struct drm_connector *connector)
  928. {
  929. struct analogix_dp_device *dp = to_dp(connector);
  930. return dp->encoder;
  931. }
  932. static int analogix_dp_atomic_check(struct drm_connector *connector,
  933. struct drm_atomic_state *state)
  934. {
  935. struct analogix_dp_device *dp = to_dp(connector);
  936. struct drm_connector_state *conn_state;
  937. struct drm_crtc_state *crtc_state;
  938. conn_state = drm_atomic_get_new_connector_state(state, connector);
  939. if (WARN_ON(!conn_state))
  940. return -ENODEV;
  941. conn_state->self_refresh_aware = true;
  942. if (!conn_state->crtc)
  943. return 0;
  944. crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
  945. if (!crtc_state)
  946. return 0;
  947. if (crtc_state->self_refresh_active && !dp->psr_supported)
  948. return -EINVAL;
  949. return 0;
  950. }
  951. static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
  952. .get_modes = analogix_dp_get_modes,
  953. .best_encoder = analogix_dp_best_encoder,
  954. .atomic_check = analogix_dp_atomic_check,
  955. };
  956. static enum drm_connector_status
  957. analogix_dp_detect(struct drm_connector *connector, bool force)
  958. {
  959. struct analogix_dp_device *dp = to_dp(connector);
  960. enum drm_connector_status status = connector_status_disconnected;
  961. int ret;
  962. if (dp->plat_data->panel)
  963. return connector_status_connected;
  964. ret = analogix_dp_prepare_panel(dp, true, false);
  965. if (ret) {
  966. DRM_ERROR("Failed to prepare panel (%d)\n", ret);
  967. return connector_status_disconnected;
  968. }
  969. if (!analogix_dp_detect_hpd(dp))
  970. status = connector_status_connected;
  971. ret = analogix_dp_prepare_panel(dp, false, false);
  972. if (ret)
  973. DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
  974. return status;
  975. }
  976. static const struct drm_connector_funcs analogix_dp_connector_funcs = {
  977. .fill_modes = drm_helper_probe_single_connector_modes,
  978. .detect = analogix_dp_detect,
  979. .destroy = drm_connector_cleanup,
  980. .reset = drm_atomic_helper_connector_reset,
  981. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  982. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  983. };
  984. static int analogix_dp_bridge_attach(struct drm_bridge *bridge,
  985. enum drm_bridge_attach_flags flags)
  986. {
  987. struct analogix_dp_device *dp = bridge->driver_private;
  988. struct drm_encoder *encoder = dp->encoder;
  989. struct drm_connector *connector = NULL;
  990. int ret = 0;
  991. if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
  992. DRM_ERROR("Fix bridge driver to make connector optional!");
  993. return -EINVAL;
  994. }
  995. if (!bridge->encoder) {
  996. DRM_ERROR("Parent encoder object not found");
  997. return -ENODEV;
  998. }
  999. if (!dp->plat_data->skip_connector) {
  1000. connector = &dp->connector;
  1001. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1002. ret = drm_connector_init(dp->drm_dev, connector,
  1003. &analogix_dp_connector_funcs,
  1004. DRM_MODE_CONNECTOR_eDP);
  1005. if (ret) {
  1006. DRM_ERROR("Failed to initialize connector with drm\n");
  1007. return ret;
  1008. }
  1009. drm_connector_helper_add(connector,
  1010. &analogix_dp_connector_helper_funcs);
  1011. drm_connector_attach_encoder(connector, encoder);
  1012. }
  1013. /*
  1014. * NOTE: the connector registration is implemented in analogix
  1015. * platform driver, that to say connector would be exist after
  1016. * plat_data->attch return, that's why we record the connector
  1017. * point after plat attached.
  1018. */
  1019. if (dp->plat_data->attach) {
  1020. ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
  1021. if (ret) {
  1022. DRM_ERROR("Failed at platform attach func\n");
  1023. return ret;
  1024. }
  1025. }
  1026. return 0;
  1027. }
  1028. static
  1029. struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
  1030. struct drm_atomic_state *state)
  1031. {
  1032. struct drm_encoder *encoder = dp->encoder;
  1033. struct drm_connector *connector;
  1034. struct drm_connector_state *conn_state;
  1035. connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
  1036. if (!connector)
  1037. return NULL;
  1038. conn_state = drm_atomic_get_new_connector_state(state, connector);
  1039. if (!conn_state)
  1040. return NULL;
  1041. return conn_state->crtc;
  1042. }
  1043. static void
  1044. analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
  1045. struct drm_bridge_state *old_bridge_state)
  1046. {
  1047. struct drm_atomic_state *old_state = old_bridge_state->base.state;
  1048. struct analogix_dp_device *dp = bridge->driver_private;
  1049. struct drm_crtc *crtc;
  1050. struct drm_crtc_state *old_crtc_state;
  1051. int ret;
  1052. crtc = analogix_dp_get_new_crtc(dp, old_state);
  1053. if (!crtc)
  1054. return;
  1055. old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
  1056. /* Don't touch the panel if we're coming back from PSR */
  1057. if (old_crtc_state && old_crtc_state->self_refresh_active)
  1058. return;
  1059. ret = analogix_dp_prepare_panel(dp, true, true);
  1060. if (ret)
  1061. DRM_ERROR("failed to setup the panel ret = %d\n", ret);
  1062. }
  1063. static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
  1064. {
  1065. int ret;
  1066. pm_runtime_get_sync(dp->dev);
  1067. ret = clk_prepare_enable(dp->clock);
  1068. if (ret < 0) {
  1069. DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
  1070. goto out_dp_clk_pre;
  1071. }
  1072. if (dp->plat_data->power_on_start)
  1073. dp->plat_data->power_on_start(dp->plat_data);
  1074. phy_power_on(dp->phy);
  1075. ret = analogix_dp_init_dp(dp);
  1076. if (ret)
  1077. goto out_dp_init;
  1078. /*
  1079. * According to DP spec v1.3 chap 3.5.1.2 Link Training,
  1080. * We should first make sure the HPD signal is asserted high by device
  1081. * when we want to establish a link with it.
  1082. */
  1083. ret = analogix_dp_detect_hpd(dp);
  1084. if (ret) {
  1085. DRM_ERROR("failed to get hpd single ret = %d\n", ret);
  1086. goto out_dp_init;
  1087. }
  1088. ret = analogix_dp_commit(dp);
  1089. if (ret) {
  1090. DRM_ERROR("dp commit error, ret = %d\n", ret);
  1091. goto out_dp_init;
  1092. }
  1093. if (dp->plat_data->power_on_end)
  1094. dp->plat_data->power_on_end(dp->plat_data);
  1095. enable_irq(dp->irq);
  1096. return 0;
  1097. out_dp_init:
  1098. phy_power_off(dp->phy);
  1099. if (dp->plat_data->power_off)
  1100. dp->plat_data->power_off(dp->plat_data);
  1101. clk_disable_unprepare(dp->clock);
  1102. out_dp_clk_pre:
  1103. pm_runtime_put_sync(dp->dev);
  1104. return ret;
  1105. }
  1106. static void
  1107. analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
  1108. struct drm_bridge_state *old_bridge_state)
  1109. {
  1110. struct drm_atomic_state *old_state = old_bridge_state->base.state;
  1111. struct analogix_dp_device *dp = bridge->driver_private;
  1112. struct drm_crtc *crtc;
  1113. struct drm_crtc_state *old_crtc_state;
  1114. int timeout_loop = 0;
  1115. int ret;
  1116. crtc = analogix_dp_get_new_crtc(dp, old_state);
  1117. if (!crtc)
  1118. return;
  1119. old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
  1120. /* Not a full enable, just disable PSR and continue */
  1121. if (old_crtc_state && old_crtc_state->self_refresh_active) {
  1122. ret = analogix_dp_disable_psr(dp);
  1123. if (ret)
  1124. DRM_ERROR("Failed to disable psr %d\n", ret);
  1125. return;
  1126. }
  1127. if (dp->dpms_mode == DRM_MODE_DPMS_ON)
  1128. return;
  1129. while (timeout_loop < MAX_PLL_LOCK_LOOP) {
  1130. if (analogix_dp_set_bridge(dp) == 0) {
  1131. dp->dpms_mode = DRM_MODE_DPMS_ON;
  1132. return;
  1133. }
  1134. dev_err(dp->dev, "failed to set bridge, retry: %d\n",
  1135. timeout_loop);
  1136. timeout_loop++;
  1137. usleep_range(10, 11);
  1138. }
  1139. dev_err(dp->dev, "too many times retry set bridge, give it up\n");
  1140. }
  1141. static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
  1142. {
  1143. struct analogix_dp_device *dp = bridge->driver_private;
  1144. int ret;
  1145. if (dp->dpms_mode != DRM_MODE_DPMS_ON)
  1146. return;
  1147. if (dp->plat_data->panel) {
  1148. if (drm_panel_disable(dp->plat_data->panel)) {
  1149. DRM_ERROR("failed to disable the panel\n");
  1150. return;
  1151. }
  1152. }
  1153. disable_irq(dp->irq);
  1154. if (dp->plat_data->power_off)
  1155. dp->plat_data->power_off(dp->plat_data);
  1156. analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
  1157. phy_power_off(dp->phy);
  1158. clk_disable_unprepare(dp->clock);
  1159. pm_runtime_put_sync(dp->dev);
  1160. ret = analogix_dp_prepare_panel(dp, false, true);
  1161. if (ret)
  1162. DRM_ERROR("failed to setup the panel ret = %d\n", ret);
  1163. dp->fast_train_enable = false;
  1164. dp->psr_supported = false;
  1165. dp->dpms_mode = DRM_MODE_DPMS_OFF;
  1166. }
  1167. static void
  1168. analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
  1169. struct drm_bridge_state *old_bridge_state)
  1170. {
  1171. struct drm_atomic_state *old_state = old_bridge_state->base.state;
  1172. struct analogix_dp_device *dp = bridge->driver_private;
  1173. struct drm_crtc *crtc;
  1174. struct drm_crtc_state *new_crtc_state = NULL;
  1175. crtc = analogix_dp_get_new_crtc(dp, old_state);
  1176. if (!crtc)
  1177. goto out;
  1178. new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
  1179. if (!new_crtc_state)
  1180. goto out;
  1181. /* Don't do a full disable on PSR transitions */
  1182. if (new_crtc_state->self_refresh_active)
  1183. return;
  1184. out:
  1185. analogix_dp_bridge_disable(bridge);
  1186. }
  1187. static void
  1188. analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
  1189. struct drm_bridge_state *old_bridge_state)
  1190. {
  1191. struct drm_atomic_state *old_state = old_bridge_state->base.state;
  1192. struct analogix_dp_device *dp = bridge->driver_private;
  1193. struct drm_crtc *crtc;
  1194. struct drm_crtc_state *new_crtc_state;
  1195. int ret;
  1196. crtc = analogix_dp_get_new_crtc(dp, old_state);
  1197. if (!crtc)
  1198. return;
  1199. new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
  1200. if (!new_crtc_state || !new_crtc_state->self_refresh_active)
  1201. return;
  1202. ret = analogix_dp_enable_psr(dp);
  1203. if (ret)
  1204. DRM_ERROR("Failed to enable psr (%d)\n", ret);
  1205. }
  1206. static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
  1207. const struct drm_display_mode *orig_mode,
  1208. const struct drm_display_mode *mode)
  1209. {
  1210. struct analogix_dp_device *dp = bridge->driver_private;
  1211. struct drm_display_info *display_info = &dp->connector.display_info;
  1212. struct video_info *video = &dp->video_info;
  1213. struct device_node *dp_node = dp->dev->of_node;
  1214. int vic;
  1215. /* Input video interlaces & hsync pol & vsync pol */
  1216. video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
  1217. video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
  1218. video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
  1219. /* Input video dynamic_range & colorimetry */
  1220. vic = drm_match_cea_mode(mode);
  1221. if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
  1222. (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
  1223. video->dynamic_range = CEA;
  1224. video->ycbcr_coeff = COLOR_YCBCR601;
  1225. } else if (vic) {
  1226. video->dynamic_range = CEA;
  1227. video->ycbcr_coeff = COLOR_YCBCR709;
  1228. } else {
  1229. video->dynamic_range = VESA;
  1230. video->ycbcr_coeff = COLOR_YCBCR709;
  1231. }
  1232. /* Input vide bpc and color_formats */
  1233. switch (display_info->bpc) {
  1234. case 12:
  1235. video->color_depth = COLOR_12;
  1236. break;
  1237. case 10:
  1238. video->color_depth = COLOR_10;
  1239. break;
  1240. case 8:
  1241. video->color_depth = COLOR_8;
  1242. break;
  1243. case 6:
  1244. video->color_depth = COLOR_6;
  1245. break;
  1246. default:
  1247. video->color_depth = COLOR_8;
  1248. break;
  1249. }
  1250. if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
  1251. video->color_space = COLOR_YCBCR444;
  1252. else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
  1253. video->color_space = COLOR_YCBCR422;
  1254. else
  1255. video->color_space = COLOR_RGB;
  1256. /*
  1257. * NOTE: those property parsing code is used for providing backward
  1258. * compatibility for samsung platform.
  1259. * Due to we used the "of_property_read_u32" interfaces, when this
  1260. * property isn't present, the "video_info" can keep the original
  1261. * values and wouldn't be modified.
  1262. */
  1263. of_property_read_u32(dp_node, "samsung,color-space",
  1264. &video->color_space);
  1265. of_property_read_u32(dp_node, "samsung,dynamic-range",
  1266. &video->dynamic_range);
  1267. of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
  1268. &video->ycbcr_coeff);
  1269. of_property_read_u32(dp_node, "samsung,color-depth",
  1270. &video->color_depth);
  1271. if (of_property_read_bool(dp_node, "hsync-active-high"))
  1272. video->h_sync_polarity = true;
  1273. if (of_property_read_bool(dp_node, "vsync-active-high"))
  1274. video->v_sync_polarity = true;
  1275. if (of_property_read_bool(dp_node, "interlaced"))
  1276. video->interlaced = true;
  1277. }
  1278. static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
  1279. .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
  1280. .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
  1281. .atomic_reset = drm_atomic_helper_bridge_reset,
  1282. .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
  1283. .atomic_enable = analogix_dp_bridge_atomic_enable,
  1284. .atomic_disable = analogix_dp_bridge_atomic_disable,
  1285. .atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
  1286. .mode_set = analogix_dp_bridge_mode_set,
  1287. .attach = analogix_dp_bridge_attach,
  1288. };
  1289. static int analogix_dp_create_bridge(struct drm_device *drm_dev,
  1290. struct analogix_dp_device *dp)
  1291. {
  1292. struct drm_bridge *bridge;
  1293. int ret;
  1294. bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
  1295. if (!bridge) {
  1296. DRM_ERROR("failed to allocate for drm bridge\n");
  1297. return -ENOMEM;
  1298. }
  1299. dp->bridge = bridge;
  1300. bridge->driver_private = dp;
  1301. bridge->funcs = &analogix_dp_bridge_funcs;
  1302. ret = drm_bridge_attach(dp->encoder, bridge, NULL, 0);
  1303. if (ret) {
  1304. DRM_ERROR("failed to attach drm bridge\n");
  1305. return -EINVAL;
  1306. }
  1307. return 0;
  1308. }
  1309. static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
  1310. {
  1311. struct device_node *dp_node = dp->dev->of_node;
  1312. struct video_info *video_info = &dp->video_info;
  1313. switch (dp->plat_data->dev_type) {
  1314. case RK3288_DP:
  1315. case RK3399_EDP:
  1316. /*
  1317. * Like Rk3288 DisplayPort TRM indicate that "Main link
  1318. * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
  1319. */
  1320. video_info->max_link_rate = 0x0A;
  1321. video_info->max_lane_count = 0x04;
  1322. break;
  1323. case EXYNOS_DP:
  1324. /*
  1325. * NOTE: those property parseing code is used for
  1326. * providing backward compatibility for samsung platform.
  1327. */
  1328. of_property_read_u32(dp_node, "samsung,link-rate",
  1329. &video_info->max_link_rate);
  1330. of_property_read_u32(dp_node, "samsung,lane-count",
  1331. &video_info->max_lane_count);
  1332. break;
  1333. }
  1334. return 0;
  1335. }
  1336. static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
  1337. struct drm_dp_aux_msg *msg)
  1338. {
  1339. struct analogix_dp_device *dp = to_dp(aux);
  1340. return analogix_dp_transfer(dp, msg);
  1341. }
  1342. struct analogix_dp_device *
  1343. analogix_dp_probe(struct device *dev, struct analogix_dp_plat_data *plat_data)
  1344. {
  1345. struct platform_device *pdev = to_platform_device(dev);
  1346. struct analogix_dp_device *dp;
  1347. struct resource *res;
  1348. unsigned int irq_flags;
  1349. int ret;
  1350. if (!plat_data) {
  1351. dev_err(dev, "Invalided input plat_data\n");
  1352. return ERR_PTR(-EINVAL);
  1353. }
  1354. dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
  1355. if (!dp)
  1356. return ERR_PTR(-ENOMEM);
  1357. dp->dev = &pdev->dev;
  1358. dp->dpms_mode = DRM_MODE_DPMS_OFF;
  1359. mutex_init(&dp->panel_lock);
  1360. dp->panel_is_modeset = false;
  1361. /*
  1362. * platform dp driver need containor_of the plat_data to get
  1363. * the driver private data, so we need to store the point of
  1364. * plat_data, not the context of plat_data.
  1365. */
  1366. dp->plat_data = plat_data;
  1367. ret = analogix_dp_dt_parse_pdata(dp);
  1368. if (ret)
  1369. return ERR_PTR(ret);
  1370. dp->phy = devm_phy_get(dp->dev, "dp");
  1371. if (IS_ERR(dp->phy)) {
  1372. dev_err(dp->dev, "no DP phy configured\n");
  1373. ret = PTR_ERR(dp->phy);
  1374. if (ret) {
  1375. /*
  1376. * phy itself is not enabled, so we can move forward
  1377. * assigning NULL to phy pointer.
  1378. */
  1379. if (ret == -ENOSYS || ret == -ENODEV)
  1380. dp->phy = NULL;
  1381. else
  1382. return ERR_PTR(ret);
  1383. }
  1384. }
  1385. dp->clock = devm_clk_get(&pdev->dev, "dp");
  1386. if (IS_ERR(dp->clock)) {
  1387. dev_err(&pdev->dev, "failed to get clock\n");
  1388. return ERR_CAST(dp->clock);
  1389. }
  1390. clk_prepare_enable(dp->clock);
  1391. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1392. dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
  1393. if (IS_ERR(dp->reg_base))
  1394. return ERR_CAST(dp->reg_base);
  1395. dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
  1396. /* Try two different names */
  1397. dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
  1398. if (!dp->hpd_gpiod)
  1399. dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
  1400. GPIOD_IN);
  1401. if (IS_ERR(dp->hpd_gpiod)) {
  1402. dev_err(dev, "error getting HDP GPIO: %ld\n",
  1403. PTR_ERR(dp->hpd_gpiod));
  1404. return ERR_CAST(dp->hpd_gpiod);
  1405. }
  1406. if (dp->hpd_gpiod) {
  1407. /*
  1408. * Set up the hotplug GPIO from the device tree as an interrupt.
  1409. * Simply specifying a different interrupt in the device tree
  1410. * doesn't work since we handle hotplug rather differently when
  1411. * using a GPIO. We also need the actual GPIO specifier so
  1412. * that we can get the current state of the GPIO.
  1413. */
  1414. dp->irq = gpiod_to_irq(dp->hpd_gpiod);
  1415. irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
  1416. } else {
  1417. dp->irq = platform_get_irq(pdev, 0);
  1418. irq_flags = 0;
  1419. }
  1420. if (dp->irq == -ENXIO) {
  1421. dev_err(&pdev->dev, "failed to get irq\n");
  1422. return ERR_PTR(-ENODEV);
  1423. }
  1424. ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
  1425. analogix_dp_hardirq,
  1426. analogix_dp_irq_thread,
  1427. irq_flags, "analogix-dp", dp);
  1428. if (ret) {
  1429. dev_err(&pdev->dev, "failed to request irq\n");
  1430. return ERR_PTR(ret);
  1431. }
  1432. disable_irq(dp->irq);
  1433. return dp;
  1434. }
  1435. EXPORT_SYMBOL_GPL(analogix_dp_probe);
  1436. int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev)
  1437. {
  1438. int ret;
  1439. dp->drm_dev = drm_dev;
  1440. dp->encoder = dp->plat_data->encoder;
  1441. dp->aux.name = "DP-AUX";
  1442. dp->aux.transfer = analogix_dpaux_transfer;
  1443. dp->aux.dev = dp->dev;
  1444. ret = drm_dp_aux_register(&dp->aux);
  1445. if (ret)
  1446. return ret;
  1447. pm_runtime_enable(dp->dev);
  1448. ret = analogix_dp_create_bridge(drm_dev, dp);
  1449. if (ret) {
  1450. DRM_ERROR("failed to create bridge (%d)\n", ret);
  1451. goto err_disable_pm_runtime;
  1452. }
  1453. return 0;
  1454. err_disable_pm_runtime:
  1455. pm_runtime_disable(dp->dev);
  1456. return ret;
  1457. }
  1458. EXPORT_SYMBOL_GPL(analogix_dp_bind);
  1459. void analogix_dp_unbind(struct analogix_dp_device *dp)
  1460. {
  1461. analogix_dp_bridge_disable(dp->bridge);
  1462. dp->connector.funcs->destroy(&dp->connector);
  1463. if (dp->plat_data->panel) {
  1464. if (drm_panel_unprepare(dp->plat_data->panel))
  1465. DRM_ERROR("failed to turnoff the panel\n");
  1466. }
  1467. drm_dp_aux_unregister(&dp->aux);
  1468. pm_runtime_disable(dp->dev);
  1469. }
  1470. EXPORT_SYMBOL_GPL(analogix_dp_unbind);
  1471. void analogix_dp_remove(struct analogix_dp_device *dp)
  1472. {
  1473. clk_disable_unprepare(dp->clock);
  1474. }
  1475. EXPORT_SYMBOL_GPL(analogix_dp_remove);
  1476. #ifdef CONFIG_PM
  1477. int analogix_dp_suspend(struct analogix_dp_device *dp)
  1478. {
  1479. clk_disable_unprepare(dp->clock);
  1480. if (dp->plat_data->panel) {
  1481. if (drm_panel_unprepare(dp->plat_data->panel))
  1482. DRM_ERROR("failed to turnoff the panel\n");
  1483. }
  1484. return 0;
  1485. }
  1486. EXPORT_SYMBOL_GPL(analogix_dp_suspend);
  1487. int analogix_dp_resume(struct analogix_dp_device *dp)
  1488. {
  1489. int ret;
  1490. ret = clk_prepare_enable(dp->clock);
  1491. if (ret < 0) {
  1492. DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
  1493. return ret;
  1494. }
  1495. if (dp->plat_data->panel) {
  1496. if (drm_panel_prepare(dp->plat_data->panel)) {
  1497. DRM_ERROR("failed to setup the panel\n");
  1498. return -EBUSY;
  1499. }
  1500. }
  1501. return 0;
  1502. }
  1503. EXPORT_SYMBOL_GPL(analogix_dp_resume);
  1504. #endif
  1505. int analogix_dp_start_crc(struct drm_connector *connector)
  1506. {
  1507. struct analogix_dp_device *dp = to_dp(connector);
  1508. if (!connector->state->crtc) {
  1509. DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
  1510. connector->name);
  1511. return -EINVAL;
  1512. }
  1513. return drm_dp_start_crc(&dp->aux, connector->state->crtc);
  1514. }
  1515. EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
  1516. int analogix_dp_stop_crc(struct drm_connector *connector)
  1517. {
  1518. struct analogix_dp_device *dp = to_dp(connector);
  1519. return drm_dp_stop_crc(&dp->aux);
  1520. }
  1521. EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
  1522. MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
  1523. MODULE_DESCRIPTION("Analogix DP Core Driver");
  1524. MODULE_LICENSE("GPL v2");