analogix-i2c-txcommon.h 6.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright(c) 2016, Analogix Semiconductor. All rights reserved.
  4. */
  5. #ifndef _ANALOGIX_I2C_TXCOMMON_H_
  6. #define _ANALOGIX_I2C_TXCOMMON_H_
  7. /***************************************************************/
  8. /* Register definitions for TX_P2 */
  9. /***************************************************************/
  10. /*
  11. * Core Register Definitions
  12. */
  13. /* Device ID Low Byte Register */
  14. #define SP_DEVICE_IDL_REG 0x02
  15. /* Device ID High Byte Register */
  16. #define SP_DEVICE_IDH_REG 0x03
  17. /* Device version register */
  18. #define SP_DEVICE_VERSION_REG 0x04
  19. /* Power Down Control Register */
  20. #define SP_POWERDOWN_CTRL_REG 0x05
  21. #define SP_REGISTER_PD BIT(7)
  22. #define SP_HDCP_PD BIT(5)
  23. #define SP_AUDIO_PD BIT(4)
  24. #define SP_VIDEO_PD BIT(3)
  25. #define SP_LINK_PD BIT(2)
  26. #define SP_TOTAL_PD BIT(1)
  27. /* Reset Control Register 1 */
  28. #define SP_RESET_CTRL1_REG 0x06
  29. #define SP_MISC_RST BIT(7)
  30. #define SP_VIDCAP_RST BIT(6)
  31. #define SP_VIDFIF_RST BIT(5)
  32. #define SP_AUDFIF_RST BIT(4)
  33. #define SP_AUDCAP_RST BIT(3)
  34. #define SP_HDCP_RST BIT(2)
  35. #define SP_SW_RST BIT(1)
  36. #define SP_HW_RST BIT(0)
  37. /* Reset Control Register 2 */
  38. #define SP_RESET_CTRL2_REG 0x07
  39. #define SP_AUX_RST BIT(2)
  40. #define SP_SERDES_FIFO_RST BIT(1)
  41. #define SP_I2C_REG_RST BIT(0)
  42. /* Video Control Register 1 */
  43. #define SP_VID_CTRL1_REG 0x08
  44. #define SP_VIDEO_EN BIT(7)
  45. #define SP_VIDEO_MUTE BIT(2)
  46. #define SP_DE_GEN BIT(1)
  47. #define SP_DEMUX BIT(0)
  48. /* Video Control Register 2 */
  49. #define SP_VID_CTRL2_REG 0x09
  50. #define SP_IN_COLOR_F_MASK 0x03
  51. #define SP_IN_YC_BIT_SEL BIT(2)
  52. #define SP_IN_BPC_MASK 0x70
  53. #define SP_IN_BPC_SHIFT 4
  54. # define SP_IN_BPC_12BIT 0x03
  55. # define SP_IN_BPC_10BIT 0x02
  56. # define SP_IN_BPC_8BIT 0x01
  57. # define SP_IN_BPC_6BIT 0x00
  58. #define SP_IN_D_RANGE BIT(7)
  59. /* Video Control Register 3 */
  60. #define SP_VID_CTRL3_REG 0x0a
  61. #define SP_HPD_OUT BIT(6)
  62. /* Video Control Register 5 */
  63. #define SP_VID_CTRL5_REG 0x0c
  64. #define SP_CSC_STD_SEL BIT(7)
  65. #define SP_XVYCC_RNG_LMT BIT(6)
  66. #define SP_RANGE_Y2R BIT(5)
  67. #define SP_CSPACE_Y2R BIT(4)
  68. #define SP_RGB_RNG_LMT BIT(3)
  69. #define SP_Y_RNG_LMT BIT(2)
  70. #define SP_RANGE_R2Y BIT(1)
  71. #define SP_CSPACE_R2Y BIT(0)
  72. /* Video Control Register 6 */
  73. #define SP_VID_CTRL6_REG 0x0d
  74. #define SP_TEST_PATTERN_EN BIT(7)
  75. #define SP_VIDEO_PROCESS_EN BIT(6)
  76. #define SP_VID_US_MODE BIT(3)
  77. #define SP_VID_DS_MODE BIT(2)
  78. #define SP_UP_SAMPLE BIT(1)
  79. #define SP_DOWN_SAMPLE BIT(0)
  80. /* Video Control Register 8 */
  81. #define SP_VID_CTRL8_REG 0x0f
  82. #define SP_VID_VRES_TH BIT(0)
  83. /* Total Line Status Low Byte Register */
  84. #define SP_TOTAL_LINE_STAL_REG 0x24
  85. /* Total Line Status High Byte Register */
  86. #define SP_TOTAL_LINE_STAH_REG 0x25
  87. /* Active Line Status Low Byte Register */
  88. #define SP_ACT_LINE_STAL_REG 0x26
  89. /* Active Line Status High Byte Register */
  90. #define SP_ACT_LINE_STAH_REG 0x27
  91. /* Vertical Front Porch Status Register */
  92. #define SP_V_F_PORCH_STA_REG 0x28
  93. /* Vertical SYNC Width Status Register */
  94. #define SP_V_SYNC_STA_REG 0x29
  95. /* Vertical Back Porch Status Register */
  96. #define SP_V_B_PORCH_STA_REG 0x2a
  97. /* Total Pixel Status Low Byte Register */
  98. #define SP_TOTAL_PIXEL_STAL_REG 0x2b
  99. /* Total Pixel Status High Byte Register */
  100. #define SP_TOTAL_PIXEL_STAH_REG 0x2c
  101. /* Active Pixel Status Low Byte Register */
  102. #define SP_ACT_PIXEL_STAL_REG 0x2d
  103. /* Active Pixel Status High Byte Register */
  104. #define SP_ACT_PIXEL_STAH_REG 0x2e
  105. /* Horizontal Front Porch Status Low Byte Register */
  106. #define SP_H_F_PORCH_STAL_REG 0x2f
  107. /* Horizontal Front Porch Statys High Byte Register */
  108. #define SP_H_F_PORCH_STAH_REG 0x30
  109. /* Horizontal SYNC Width Status Low Byte Register */
  110. #define SP_H_SYNC_STAL_REG 0x31
  111. /* Horizontal SYNC Width Status High Byte Register */
  112. #define SP_H_SYNC_STAH_REG 0x32
  113. /* Horizontal Back Porch Status Low Byte Register */
  114. #define SP_H_B_PORCH_STAL_REG 0x33
  115. /* Horizontal Back Porch Status High Byte Register */
  116. #define SP_H_B_PORCH_STAH_REG 0x34
  117. /* InfoFrame AVI Packet DB1 Register */
  118. #define SP_INFOFRAME_AVI_DB1_REG 0x70
  119. /* Bit Control Specific Register */
  120. #define SP_BIT_CTRL_SPECIFIC_REG 0x80
  121. #define SP_BIT_CTRL_SELECT_SHIFT 1
  122. #define SP_ENABLE_BIT_CTRL BIT(0)
  123. /* InfoFrame Audio Packet DB1 Register */
  124. #define SP_INFOFRAME_AUD_DB1_REG 0x83
  125. /* InfoFrame MPEG Packet DB1 Register */
  126. #define SP_INFOFRAME_MPEG_DB1_REG 0xb0
  127. /* Audio Channel Status Registers */
  128. #define SP_AUD_CH_STATUS_BASE 0xd0
  129. /* Audio Channel Num Register 5 */
  130. #define SP_I2S_CHANNEL_NUM_MASK 0xe0
  131. # define SP_I2S_CH_NUM_1 (0x00 << 5)
  132. # define SP_I2S_CH_NUM_2 (0x01 << 5)
  133. # define SP_I2S_CH_NUM_3 (0x02 << 5)
  134. # define SP_I2S_CH_NUM_4 (0x03 << 5)
  135. # define SP_I2S_CH_NUM_5 (0x04 << 5)
  136. # define SP_I2S_CH_NUM_6 (0x05 << 5)
  137. # define SP_I2S_CH_NUM_7 (0x06 << 5)
  138. # define SP_I2S_CH_NUM_8 (0x07 << 5)
  139. #define SP_EXT_VUCP BIT(2)
  140. #define SP_VBIT BIT(1)
  141. #define SP_AUDIO_LAYOUT BIT(0)
  142. /* Analog Debug Register 1 */
  143. #define SP_ANALOG_DEBUG1_REG 0xdc
  144. /* Analog Debug Register 2 */
  145. #define SP_ANALOG_DEBUG2_REG 0xdd
  146. #define SP_FORCE_SW_OFF_BYPASS 0x20
  147. #define SP_XTAL_FRQ 0x1c
  148. # define SP_XTAL_FRQ_19M2 (0x00 << 2)
  149. # define SP_XTAL_FRQ_24M (0x01 << 2)
  150. # define SP_XTAL_FRQ_25M (0x02 << 2)
  151. # define SP_XTAL_FRQ_26M (0x03 << 2)
  152. # define SP_XTAL_FRQ_27M (0x04 << 2)
  153. # define SP_XTAL_FRQ_38M4 (0x05 << 2)
  154. # define SP_XTAL_FRQ_52M (0x06 << 2)
  155. #define SP_POWERON_TIME_1P5MS 0x03
  156. /* Analog Control 0 Register */
  157. #define SP_ANALOG_CTRL0_REG 0xe1
  158. /* Common Interrupt Status Register 1 */
  159. #define SP_COMMON_INT_STATUS_BASE (0xf1 - 1)
  160. #define SP_PLL_LOCK_CHG 0x40
  161. /* Common Interrupt Status Register 2 */
  162. #define SP_COMMON_INT_STATUS2 0xf2
  163. #define SP_HDCP_AUTH_CHG BIT(1)
  164. #define SP_HDCP_AUTH_DONE BIT(0)
  165. #define SP_HDCP_LINK_CHECK_FAIL BIT(0)
  166. /* Common Interrupt Status Register 4 */
  167. #define SP_COMMON_INT_STATUS4_REG 0xf4
  168. #define SP_HPD_IRQ BIT(6)
  169. #define SP_HPD_ESYNC_ERR BIT(4)
  170. #define SP_HPD_CHG BIT(2)
  171. #define SP_HPD_LOST BIT(1)
  172. #define SP_HPD_PLUG BIT(0)
  173. /* DP Interrupt Status Register */
  174. #define SP_DP_INT_STATUS1_REG 0xf7
  175. #define SP_TRAINING_FINISH BIT(5)
  176. #define SP_POLLING_ERR BIT(4)
  177. /* Common Interrupt Mask Register */
  178. #define SP_COMMON_INT_MASK_BASE (0xf8 - 1)
  179. #define SP_COMMON_INT_MASK4_REG 0xfb
  180. /* DP Interrupts Mask Register */
  181. #define SP_DP_INT_MASK1_REG 0xfe
  182. /* Interrupt Control Register */
  183. #define SP_INT_CTRL_REG 0xff
  184. #endif /* _ANALOGIX_I2C_TXCOMMON_H_ */