analogix-anx78xx.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright(c) 2016, Analogix Semiconductor.
  4. *
  5. * Based on anx7808 driver obtained from chromeos with copyright:
  6. * Copyright(c) 2013, Google Inc.
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/err.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/i2c.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/regmap.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/types.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_bridge.h>
  22. #include <drm/drm_crtc.h>
  23. #include <drm/drm_dp_helper.h>
  24. #include <drm/drm_edid.h>
  25. #include <drm/drm_print.h>
  26. #include <drm/drm_probe_helper.h>
  27. #include "analogix-anx78xx.h"
  28. #define I2C_NUM_ADDRESSES 5
  29. #define I2C_IDX_TX_P0 0
  30. #define I2C_IDX_TX_P1 1
  31. #define I2C_IDX_TX_P2 2
  32. #define I2C_IDX_RX_P0 3
  33. #define I2C_IDX_RX_P1 4
  34. #define XTAL_CLK 270 /* 27M */
  35. static const u8 anx7808_i2c_addresses[] = {
  36. [I2C_IDX_TX_P0] = 0x78,
  37. [I2C_IDX_TX_P1] = 0x7a,
  38. [I2C_IDX_TX_P2] = 0x72,
  39. [I2C_IDX_RX_P0] = 0x7e,
  40. [I2C_IDX_RX_P1] = 0x80,
  41. };
  42. static const u8 anx781x_i2c_addresses[] = {
  43. [I2C_IDX_TX_P0] = 0x70,
  44. [I2C_IDX_TX_P1] = 0x7a,
  45. [I2C_IDX_TX_P2] = 0x72,
  46. [I2C_IDX_RX_P0] = 0x7e,
  47. [I2C_IDX_RX_P1] = 0x80,
  48. };
  49. struct anx78xx_platform_data {
  50. struct regulator *dvdd10;
  51. struct gpio_desc *gpiod_hpd;
  52. struct gpio_desc *gpiod_pd;
  53. struct gpio_desc *gpiod_reset;
  54. int hpd_irq;
  55. int intp_irq;
  56. };
  57. struct anx78xx {
  58. struct drm_dp_aux aux;
  59. struct drm_bridge bridge;
  60. struct i2c_client *client;
  61. struct edid *edid;
  62. struct drm_connector connector;
  63. struct anx78xx_platform_data pdata;
  64. struct mutex lock;
  65. /*
  66. * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,
  67. * RX_P0 and RX_P1.
  68. */
  69. struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
  70. struct regmap *map[I2C_NUM_ADDRESSES];
  71. u16 chipid;
  72. u8 dpcd[DP_RECEIVER_CAP_SIZE];
  73. bool powered;
  74. };
  75. static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
  76. {
  77. return container_of(c, struct anx78xx, connector);
  78. }
  79. static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
  80. {
  81. return container_of(bridge, struct anx78xx, bridge);
  82. }
  83. static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
  84. {
  85. return regmap_update_bits(map, reg, mask, mask);
  86. }
  87. static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
  88. {
  89. return regmap_update_bits(map, reg, mask, 0);
  90. }
  91. static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
  92. struct drm_dp_aux_msg *msg)
  93. {
  94. struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
  95. return anx_dp_aux_transfer(anx78xx->map[I2C_IDX_TX_P0], msg);
  96. }
  97. static int anx78xx_set_hpd(struct anx78xx *anx78xx)
  98. {
  99. int err;
  100. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
  101. SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
  102. if (err)
  103. return err;
  104. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
  105. SP_HPD_OUT);
  106. if (err)
  107. return err;
  108. return 0;
  109. }
  110. static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
  111. {
  112. int err;
  113. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
  114. SP_HPD_OUT);
  115. if (err)
  116. return err;
  117. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
  118. SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
  119. if (err)
  120. return err;
  121. return 0;
  122. }
  123. static const struct reg_sequence tmds_phy_initialization[] = {
  124. { SP_TMDS_CTRL_BASE + 1, 0x90 },
  125. { SP_TMDS_CTRL_BASE + 2, 0xa9 },
  126. { SP_TMDS_CTRL_BASE + 6, 0x92 },
  127. { SP_TMDS_CTRL_BASE + 7, 0x80 },
  128. { SP_TMDS_CTRL_BASE + 20, 0xf2 },
  129. { SP_TMDS_CTRL_BASE + 22, 0xc4 },
  130. { SP_TMDS_CTRL_BASE + 23, 0x18 },
  131. };
  132. static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
  133. {
  134. int err;
  135. err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
  136. SP_AUD_MUTE | SP_VID_MUTE);
  137. if (err)
  138. return err;
  139. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
  140. SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
  141. SP_DIGITAL_CKDT_EN);
  142. if (err)
  143. return err;
  144. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
  145. SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
  146. SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
  147. if (err)
  148. return err;
  149. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
  150. SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
  151. SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
  152. if (err)
  153. return err;
  154. /* Sync detect change, GP set mute */
  155. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
  156. SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
  157. BIT(6));
  158. if (err)
  159. return err;
  160. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
  161. SP_AUD_EXCEPTION_ENABLE_BASE + 3,
  162. SP_AEC_EN21);
  163. if (err)
  164. return err;
  165. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
  166. SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
  167. if (err)
  168. return err;
  169. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
  170. SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
  171. if (err)
  172. return err;
  173. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
  174. SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
  175. if (err)
  176. return err;
  177. /* Enable DDC stretch */
  178. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
  179. SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
  180. if (err)
  181. return err;
  182. /* TMDS phy initialization */
  183. err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
  184. tmds_phy_initialization,
  185. ARRAY_SIZE(tmds_phy_initialization));
  186. if (err)
  187. return err;
  188. err = anx78xx_clear_hpd(anx78xx);
  189. if (err)
  190. return err;
  191. return 0;
  192. }
  193. static const u8 dp_tx_output_precise_tune_bits[20] = {
  194. 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
  195. 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
  196. 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
  197. };
  198. static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
  199. {
  200. int err;
  201. /*
  202. * REVISIT : It is writing to a RESERVED bits in Analog Control 0
  203. * register.
  204. */
  205. err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
  206. 0x02);
  207. if (err)
  208. return err;
  209. /*
  210. * Write DP TX output emphasis precise tune bits.
  211. */
  212. err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
  213. SP_DP_TX_LT_CTRL0_REG,
  214. dp_tx_output_precise_tune_bits,
  215. ARRAY_SIZE(dp_tx_output_precise_tune_bits));
  216. if (err)
  217. return err;
  218. return 0;
  219. }
  220. static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
  221. {
  222. unsigned int value;
  223. int err;
  224. err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
  225. SP_ANALOG_DEBUG2_REG,
  226. SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
  227. SP_XTAL_FRQ_27M);
  228. if (err)
  229. return err;
  230. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
  231. XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
  232. if (err)
  233. return err;
  234. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
  235. ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
  236. if (err)
  237. return err;
  238. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
  239. SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
  240. if (err)
  241. return err;
  242. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
  243. SP_I2C_GEN_10US_TIMER1_REG,
  244. (XTAL_CLK & 0xff00) >> 8);
  245. if (err)
  246. return err;
  247. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
  248. XTAL_CLK / 10 - 1);
  249. if (err)
  250. return err;
  251. err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
  252. SP_HDMI_US_TIMER_CTRL_REG,
  253. &value);
  254. if (err)
  255. return err;
  256. err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
  257. SP_HDMI_US_TIMER_CTRL_REG,
  258. (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
  259. ((((XTAL_CLK / 10) >> 1) - 2) << 3));
  260. if (err)
  261. return err;
  262. return 0;
  263. }
  264. static const struct reg_sequence otp_key_protect[] = {
  265. { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
  266. { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
  267. { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
  268. };
  269. static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
  270. {
  271. int err;
  272. /* Set terminal resistor to 50 ohm */
  273. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
  274. 0x30);
  275. if (err)
  276. return err;
  277. /* Enable aux double diff output */
  278. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  279. SP_DP_AUX_CH_CTRL2_REG, 0x08);
  280. if (err)
  281. return err;
  282. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
  283. SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
  284. SP_AUTO_START);
  285. if (err)
  286. return err;
  287. err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
  288. otp_key_protect,
  289. ARRAY_SIZE(otp_key_protect));
  290. if (err)
  291. return err;
  292. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  293. SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
  294. if (err)
  295. return err;
  296. err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
  297. SP_VID_VRES_TH);
  298. if (err)
  299. return err;
  300. /*
  301. * DP HDCP auto authentication wait timer (when downstream starts to
  302. * auth, DP side will wait for this period then do auth automatically)
  303. */
  304. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
  305. 0x00);
  306. if (err)
  307. return err;
  308. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  309. SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
  310. if (err)
  311. return err;
  312. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  313. SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
  314. if (err)
  315. return err;
  316. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
  317. SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
  318. if (err)
  319. return err;
  320. err = anx78xx_xtal_clk_sel(anx78xx);
  321. if (err)
  322. return err;
  323. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
  324. SP_DEFER_CTRL_EN | 0x0c);
  325. if (err)
  326. return err;
  327. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  328. SP_DP_POLLING_CTRL_REG,
  329. SP_AUTO_POLLING_DISABLE);
  330. if (err)
  331. return err;
  332. /*
  333. * Short the link integrity check timer to speed up bstatus
  334. * polling for HDCP CTS item 1A-07
  335. */
  336. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
  337. SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
  338. if (err)
  339. return err;
  340. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  341. SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
  342. if (err)
  343. return err;
  344. /* Power down the main link by default */
  345. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  346. SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
  347. if (err)
  348. return err;
  349. err = anx78xx_link_phy_initialization(anx78xx);
  350. if (err)
  351. return err;
  352. /* Gen m_clk with downspreading */
  353. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  354. SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
  355. if (err)
  356. return err;
  357. return 0;
  358. }
  359. static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
  360. {
  361. int err;
  362. /*
  363. * BIT0: INT pin assertion polarity: 1 = assert high
  364. * BIT1: INT pin output type: 0 = push/pull
  365. */
  366. err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
  367. if (err)
  368. return err;
  369. err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
  370. SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
  371. if (err)
  372. return err;
  373. err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
  374. SP_TRAINING_FINISH);
  375. if (err)
  376. return err;
  377. err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
  378. SP_CKDT_CHG | SP_SCDT_CHG);
  379. if (err)
  380. return err;
  381. return 0;
  382. }
  383. static void anx78xx_poweron(struct anx78xx *anx78xx)
  384. {
  385. struct anx78xx_platform_data *pdata = &anx78xx->pdata;
  386. int err;
  387. if (WARN_ON(anx78xx->powered))
  388. return;
  389. if (pdata->dvdd10) {
  390. err = regulator_enable(pdata->dvdd10);
  391. if (err) {
  392. DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
  393. err);
  394. return;
  395. }
  396. usleep_range(1000, 2000);
  397. }
  398. gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
  399. usleep_range(1000, 2000);
  400. gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
  401. usleep_range(1000, 2000);
  402. gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
  403. /* Power on registers module */
  404. anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
  405. SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
  406. anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
  407. SP_REGISTER_PD | SP_TOTAL_PD);
  408. anx78xx->powered = true;
  409. }
  410. static void anx78xx_poweroff(struct anx78xx *anx78xx)
  411. {
  412. struct anx78xx_platform_data *pdata = &anx78xx->pdata;
  413. int err;
  414. if (WARN_ON(!anx78xx->powered))
  415. return;
  416. gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
  417. usleep_range(1000, 2000);
  418. gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
  419. usleep_range(1000, 2000);
  420. if (pdata->dvdd10) {
  421. err = regulator_disable(pdata->dvdd10);
  422. if (err) {
  423. DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
  424. err);
  425. return;
  426. }
  427. usleep_range(1000, 2000);
  428. }
  429. anx78xx->powered = false;
  430. }
  431. static int anx78xx_start(struct anx78xx *anx78xx)
  432. {
  433. int err;
  434. /* Power on all modules */
  435. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
  436. SP_POWERDOWN_CTRL_REG,
  437. SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
  438. SP_LINK_PD);
  439. err = anx78xx_enable_interrupts(anx78xx);
  440. if (err) {
  441. DRM_ERROR("Failed to enable interrupts: %d\n", err);
  442. goto err_poweroff;
  443. }
  444. err = anx78xx_rx_initialization(anx78xx);
  445. if (err) {
  446. DRM_ERROR("Failed receiver initialization: %d\n", err);
  447. goto err_poweroff;
  448. }
  449. err = anx78xx_tx_initialization(anx78xx);
  450. if (err) {
  451. DRM_ERROR("Failed transmitter initialization: %d\n", err);
  452. goto err_poweroff;
  453. }
  454. /*
  455. * This delay seems to help keep the hardware in a good state. Without
  456. * it, there are times where it fails silently.
  457. */
  458. usleep_range(10000, 15000);
  459. return 0;
  460. err_poweroff:
  461. DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
  462. anx78xx_poweroff(anx78xx);
  463. return err;
  464. }
  465. static int anx78xx_init_pdata(struct anx78xx *anx78xx)
  466. {
  467. struct anx78xx_platform_data *pdata = &anx78xx->pdata;
  468. struct device *dev = &anx78xx->client->dev;
  469. /* 1.0V digital core power regulator */
  470. pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
  471. if (IS_ERR(pdata->dvdd10)) {
  472. if (PTR_ERR(pdata->dvdd10) != -EPROBE_DEFER)
  473. DRM_ERROR("DVDD10 regulator not found\n");
  474. return PTR_ERR(pdata->dvdd10);
  475. }
  476. /* GPIO for HPD */
  477. pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
  478. if (IS_ERR(pdata->gpiod_hpd))
  479. return PTR_ERR(pdata->gpiod_hpd);
  480. /* GPIO for chip power down */
  481. pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
  482. if (IS_ERR(pdata->gpiod_pd))
  483. return PTR_ERR(pdata->gpiod_pd);
  484. /* GPIO for chip reset */
  485. pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
  486. return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
  487. }
  488. static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
  489. {
  490. u8 dp_bw, dpcd[2];
  491. int err;
  492. err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
  493. 0x0);
  494. if (err)
  495. return err;
  496. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
  497. SP_POWERDOWN_CTRL_REG,
  498. SP_TOTAL_PD);
  499. if (err)
  500. return err;
  501. err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
  502. if (err < 0)
  503. return err;
  504. switch (dp_bw) {
  505. case DP_LINK_BW_1_62:
  506. case DP_LINK_BW_2_7:
  507. case DP_LINK_BW_5_4:
  508. break;
  509. default:
  510. DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
  511. return -EINVAL;
  512. }
  513. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
  514. SP_VIDEO_MUTE);
  515. if (err)
  516. return err;
  517. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
  518. SP_VID_CTRL1_REG, SP_VIDEO_EN);
  519. if (err)
  520. return err;
  521. /* Get DPCD info */
  522. err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
  523. &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
  524. if (err < 0) {
  525. DRM_ERROR("Failed to read DPCD: %d\n", err);
  526. return err;
  527. }
  528. /* Clear channel x SERDES power down */
  529. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
  530. SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
  531. if (err)
  532. return err;
  533. /*
  534. * Power up the sink (DP_SET_POWER register is only available on DPCD
  535. * v1.1 and later).
  536. */
  537. if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) {
  538. err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]);
  539. if (err < 0) {
  540. DRM_ERROR("Failed to read DP_SET_POWER register: %d\n",
  541. err);
  542. return err;
  543. }
  544. dpcd[0] &= ~DP_SET_POWER_MASK;
  545. dpcd[0] |= DP_SET_POWER_D0;
  546. err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]);
  547. if (err < 0) {
  548. DRM_ERROR("Failed to power up DisplayPort link: %d\n",
  549. err);
  550. return err;
  551. }
  552. /*
  553. * According to the DP 1.1 specification, a "Sink Device must
  554. * exit the power saving state within 1 ms" (Section 2.5.3.1,
  555. * Table 5-52, "Sink Control Field" (register 0x600).
  556. */
  557. usleep_range(1000, 2000);
  558. }
  559. /* Possibly enable downspread on the sink */
  560. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
  561. SP_DP_DOWNSPREAD_CTRL1_REG, 0);
  562. if (err)
  563. return err;
  564. if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
  565. DRM_DEBUG("Enable downspread on the sink\n");
  566. /* 4000PPM */
  567. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
  568. SP_DP_DOWNSPREAD_CTRL1_REG, 8);
  569. if (err)
  570. return err;
  571. err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
  572. DP_SPREAD_AMP_0_5);
  573. if (err < 0)
  574. return err;
  575. } else {
  576. err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
  577. if (err < 0)
  578. return err;
  579. }
  580. /* Set the lane count and the link rate on the sink */
  581. if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
  582. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  583. SP_DP_SYSTEM_CTRL_BASE + 4,
  584. SP_ENHANCED_MODE);
  585. else
  586. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
  587. SP_DP_SYSTEM_CTRL_BASE + 4,
  588. SP_ENHANCED_MODE);
  589. if (err)
  590. return err;
  591. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
  592. SP_DP_MAIN_LINK_BW_SET_REG,
  593. anx78xx->dpcd[DP_MAX_LINK_RATE]);
  594. if (err)
  595. return err;
  596. dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd);
  597. if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
  598. dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  599. err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd,
  600. sizeof(dpcd));
  601. if (err < 0) {
  602. DRM_ERROR("Failed to configure link: %d\n", err);
  603. return err;
  604. }
  605. /* Start training on the source */
  606. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
  607. SP_LT_EN);
  608. if (err)
  609. return err;
  610. return 0;
  611. }
  612. static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
  613. {
  614. int err;
  615. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
  616. SP_VIDEO_MUTE);
  617. if (err)
  618. return err;
  619. /* Enable DP output */
  620. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
  621. SP_VIDEO_EN);
  622. if (err)
  623. return err;
  624. return 0;
  625. }
  626. static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
  627. struct hdmi_avi_infoframe *frame)
  628. {
  629. u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
  630. int err;
  631. err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
  632. if (err < 0) {
  633. DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
  634. return err;
  635. }
  636. err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
  637. SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
  638. if (err)
  639. return err;
  640. err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
  641. SP_INFOFRAME_AVI_DB1_REG, buffer,
  642. frame->length);
  643. if (err)
  644. return err;
  645. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  646. SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
  647. if (err)
  648. return err;
  649. err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
  650. SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
  651. if (err)
  652. return err;
  653. return 0;
  654. }
  655. static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
  656. {
  657. u8 value;
  658. int err;
  659. err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
  660. if (err < 0) {
  661. DRM_ERROR("Get sink count failed %d\n", err);
  662. return err;
  663. }
  664. if (!DP_GET_SINK_COUNT(value)) {
  665. DRM_ERROR("Downstream disconnected\n");
  666. return -EIO;
  667. }
  668. return 0;
  669. }
  670. static int anx78xx_get_modes(struct drm_connector *connector)
  671. {
  672. struct anx78xx *anx78xx = connector_to_anx78xx(connector);
  673. int err, num_modes = 0;
  674. if (WARN_ON(!anx78xx->powered))
  675. return 0;
  676. if (anx78xx->edid)
  677. return drm_add_edid_modes(connector, anx78xx->edid);
  678. mutex_lock(&anx78xx->lock);
  679. err = anx78xx_get_downstream_info(anx78xx);
  680. if (err) {
  681. DRM_ERROR("Failed to get downstream info: %d\n", err);
  682. goto unlock;
  683. }
  684. anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);
  685. if (!anx78xx->edid) {
  686. DRM_ERROR("Failed to read EDID\n");
  687. goto unlock;
  688. }
  689. err = drm_connector_update_edid_property(connector,
  690. anx78xx->edid);
  691. if (err) {
  692. DRM_ERROR("Failed to update EDID property: %d\n", err);
  693. goto unlock;
  694. }
  695. num_modes = drm_add_edid_modes(connector, anx78xx->edid);
  696. unlock:
  697. mutex_unlock(&anx78xx->lock);
  698. return num_modes;
  699. }
  700. static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
  701. .get_modes = anx78xx_get_modes,
  702. };
  703. static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
  704. bool force)
  705. {
  706. struct anx78xx *anx78xx = connector_to_anx78xx(connector);
  707. if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
  708. return connector_status_disconnected;
  709. return connector_status_connected;
  710. }
  711. static const struct drm_connector_funcs anx78xx_connector_funcs = {
  712. .fill_modes = drm_helper_probe_single_connector_modes,
  713. .detect = anx78xx_detect,
  714. .destroy = drm_connector_cleanup,
  715. .reset = drm_atomic_helper_connector_reset,
  716. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  717. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  718. };
  719. static int anx78xx_bridge_attach(struct drm_bridge *bridge,
  720. enum drm_bridge_attach_flags flags)
  721. {
  722. struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
  723. int err;
  724. if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
  725. DRM_ERROR("Fix bridge driver to make connector optional!");
  726. return -EINVAL;
  727. }
  728. if (!bridge->encoder) {
  729. DRM_ERROR("Parent encoder object not found");
  730. return -ENODEV;
  731. }
  732. /* Register aux channel */
  733. anx78xx->aux.name = "DP-AUX";
  734. anx78xx->aux.dev = &anx78xx->client->dev;
  735. anx78xx->aux.transfer = anx78xx_aux_transfer;
  736. err = drm_dp_aux_register(&anx78xx->aux);
  737. if (err < 0) {
  738. DRM_ERROR("Failed to register aux channel: %d\n", err);
  739. return err;
  740. }
  741. err = drm_connector_init(bridge->dev, &anx78xx->connector,
  742. &anx78xx_connector_funcs,
  743. DRM_MODE_CONNECTOR_DisplayPort);
  744. if (err) {
  745. DRM_ERROR("Failed to initialize connector: %d\n", err);
  746. return err;
  747. }
  748. drm_connector_helper_add(&anx78xx->connector,
  749. &anx78xx_connector_helper_funcs);
  750. err = drm_connector_register(&anx78xx->connector);
  751. if (err) {
  752. DRM_ERROR("Failed to register connector: %d\n", err);
  753. return err;
  754. }
  755. anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
  756. err = drm_connector_attach_encoder(&anx78xx->connector,
  757. bridge->encoder);
  758. if (err) {
  759. DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
  760. return err;
  761. }
  762. return 0;
  763. }
  764. static enum drm_mode_status
  765. anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
  766. const struct drm_display_info *info,
  767. const struct drm_display_mode *mode)
  768. {
  769. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  770. return MODE_NO_INTERLACE;
  771. /* Max 1200p at 5.4 Ghz, one lane */
  772. if (mode->clock > 154000)
  773. return MODE_CLOCK_HIGH;
  774. return MODE_OK;
  775. }
  776. static void anx78xx_bridge_disable(struct drm_bridge *bridge)
  777. {
  778. struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
  779. /* Power off all modules except configuration registers access */
  780. anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
  781. SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
  782. }
  783. static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
  784. const struct drm_display_mode *mode,
  785. const struct drm_display_mode *adjusted_mode)
  786. {
  787. struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
  788. struct hdmi_avi_infoframe frame;
  789. int err;
  790. if (WARN_ON(!anx78xx->powered))
  791. return;
  792. mutex_lock(&anx78xx->lock);
  793. err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
  794. &anx78xx->connector,
  795. adjusted_mode);
  796. if (err) {
  797. DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
  798. goto unlock;
  799. }
  800. err = anx78xx_send_video_infoframe(anx78xx, &frame);
  801. if (err)
  802. DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
  803. unlock:
  804. mutex_unlock(&anx78xx->lock);
  805. }
  806. static void anx78xx_bridge_enable(struct drm_bridge *bridge)
  807. {
  808. struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
  809. int err;
  810. err = anx78xx_start(anx78xx);
  811. if (err) {
  812. DRM_ERROR("Failed to initialize: %d\n", err);
  813. return;
  814. }
  815. err = anx78xx_set_hpd(anx78xx);
  816. if (err)
  817. DRM_ERROR("Failed to set HPD: %d\n", err);
  818. }
  819. static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
  820. .attach = anx78xx_bridge_attach,
  821. .mode_valid = anx78xx_bridge_mode_valid,
  822. .disable = anx78xx_bridge_disable,
  823. .mode_set = anx78xx_bridge_mode_set,
  824. .enable = anx78xx_bridge_enable,
  825. };
  826. static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
  827. {
  828. struct anx78xx *anx78xx = data;
  829. int err;
  830. if (anx78xx->powered)
  831. return IRQ_HANDLED;
  832. mutex_lock(&anx78xx->lock);
  833. /* Cable is pulled, power on the chip */
  834. anx78xx_poweron(anx78xx);
  835. err = anx78xx_enable_interrupts(anx78xx);
  836. if (err)
  837. DRM_ERROR("Failed to enable interrupts: %d\n", err);
  838. mutex_unlock(&anx78xx->lock);
  839. return IRQ_HANDLED;
  840. }
  841. static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
  842. {
  843. int err;
  844. DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
  845. err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
  846. irq);
  847. if (err)
  848. return err;
  849. if (irq & SP_TRAINING_FINISH) {
  850. DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
  851. err = anx78xx_config_dp_output(anx78xx);
  852. }
  853. return err;
  854. }
  855. static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
  856. {
  857. bool event = false;
  858. int err;
  859. DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
  860. err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
  861. SP_COMMON_INT_STATUS4_REG, irq);
  862. if (err) {
  863. DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
  864. return event;
  865. }
  866. if (irq & SP_HPD_LOST) {
  867. DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
  868. event = true;
  869. anx78xx_poweroff(anx78xx);
  870. /* Free cached EDID */
  871. kfree(anx78xx->edid);
  872. anx78xx->edid = NULL;
  873. } else if (irq & SP_HPD_PLUG) {
  874. DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
  875. event = true;
  876. }
  877. return event;
  878. }
  879. static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
  880. {
  881. unsigned int value;
  882. int err;
  883. DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
  884. err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
  885. irq);
  886. if (err) {
  887. DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
  888. return;
  889. }
  890. if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
  891. DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
  892. err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
  893. SP_SYSTEM_STATUS_REG, &value);
  894. if (err) {
  895. DRM_ERROR("Read system status reg failed: %d\n", err);
  896. return;
  897. }
  898. if (!(value & SP_TMDS_CLOCK_DET)) {
  899. DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
  900. return;
  901. }
  902. if (!(value & SP_TMDS_DE_DET)) {
  903. DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
  904. return;
  905. }
  906. err = anx78xx_dp_link_training(anx78xx);
  907. if (err)
  908. DRM_ERROR("Failed to start link training: %d\n", err);
  909. }
  910. }
  911. static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
  912. {
  913. struct anx78xx *anx78xx = data;
  914. bool event = false;
  915. unsigned int irq;
  916. int err;
  917. mutex_lock(&anx78xx->lock);
  918. err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
  919. &irq);
  920. if (err) {
  921. DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
  922. goto unlock;
  923. }
  924. if (irq)
  925. anx78xx_handle_dp_int_1(anx78xx, irq);
  926. err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
  927. SP_COMMON_INT_STATUS4_REG, &irq);
  928. if (err) {
  929. DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
  930. err);
  931. goto unlock;
  932. }
  933. if (irq)
  934. event = anx78xx_handle_common_int_4(anx78xx, irq);
  935. /* Make sure we are still powered after handle HPD events */
  936. if (!anx78xx->powered)
  937. goto unlock;
  938. err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
  939. &irq);
  940. if (err) {
  941. DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
  942. goto unlock;
  943. }
  944. if (irq)
  945. anx78xx_handle_hdmi_int_1(anx78xx, irq);
  946. unlock:
  947. mutex_unlock(&anx78xx->lock);
  948. if (event)
  949. drm_helper_hpd_irq_event(anx78xx->connector.dev);
  950. return IRQ_HANDLED;
  951. }
  952. static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
  953. {
  954. unsigned int i;
  955. for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
  956. i2c_unregister_device(anx78xx->i2c_dummy[i]);
  957. }
  958. static const struct regmap_config anx78xx_regmap_config = {
  959. .reg_bits = 8,
  960. .val_bits = 8,
  961. };
  962. static const u16 anx78xx_chipid_list[] = {
  963. 0x7808,
  964. 0x7812,
  965. 0x7814,
  966. 0x7818,
  967. };
  968. static int anx78xx_i2c_probe(struct i2c_client *client,
  969. const struct i2c_device_id *id)
  970. {
  971. struct anx78xx *anx78xx;
  972. struct anx78xx_platform_data *pdata;
  973. unsigned int i, idl, idh, version;
  974. const u8 *i2c_addresses;
  975. bool found = false;
  976. int err;
  977. anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
  978. if (!anx78xx)
  979. return -ENOMEM;
  980. pdata = &anx78xx->pdata;
  981. mutex_init(&anx78xx->lock);
  982. #if IS_ENABLED(CONFIG_OF)
  983. anx78xx->bridge.of_node = client->dev.of_node;
  984. #endif
  985. anx78xx->client = client;
  986. i2c_set_clientdata(client, anx78xx);
  987. err = anx78xx_init_pdata(anx78xx);
  988. if (err) {
  989. if (err != -EPROBE_DEFER)
  990. DRM_ERROR("Failed to initialize pdata: %d\n", err);
  991. return err;
  992. }
  993. pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
  994. if (pdata->hpd_irq < 0) {
  995. DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
  996. return -ENODEV;
  997. }
  998. pdata->intp_irq = client->irq;
  999. if (!pdata->intp_irq) {
  1000. DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
  1001. return -ENODEV;
  1002. }
  1003. /* Map slave addresses of ANX7814 */
  1004. i2c_addresses = device_get_match_data(&client->dev);
  1005. for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
  1006. struct i2c_client *i2c_dummy;
  1007. i2c_dummy = i2c_new_dummy_device(client->adapter,
  1008. i2c_addresses[i] >> 1);
  1009. if (IS_ERR(i2c_dummy)) {
  1010. err = PTR_ERR(i2c_dummy);
  1011. DRM_ERROR("Failed to reserve I2C bus %02x: %d\n",
  1012. i2c_addresses[i], err);
  1013. goto err_unregister_i2c;
  1014. }
  1015. anx78xx->i2c_dummy[i] = i2c_dummy;
  1016. anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
  1017. &anx78xx_regmap_config);
  1018. if (IS_ERR(anx78xx->map[i])) {
  1019. err = PTR_ERR(anx78xx->map[i]);
  1020. DRM_ERROR("Failed regmap initialization %02x\n",
  1021. i2c_addresses[i]);
  1022. goto err_unregister_i2c;
  1023. }
  1024. }
  1025. /* Look for supported chip ID */
  1026. anx78xx_poweron(anx78xx);
  1027. err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
  1028. &idl);
  1029. if (err)
  1030. goto err_poweroff;
  1031. err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
  1032. &idh);
  1033. if (err)
  1034. goto err_poweroff;
  1035. anx78xx->chipid = (u8)idl | ((u8)idh << 8);
  1036. err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
  1037. &version);
  1038. if (err)
  1039. goto err_poweroff;
  1040. for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
  1041. if (anx78xx->chipid == anx78xx_chipid_list[i]) {
  1042. DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
  1043. anx78xx->chipid, version);
  1044. found = true;
  1045. break;
  1046. }
  1047. }
  1048. if (!found) {
  1049. DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
  1050. anx78xx->chipid, version);
  1051. err = -ENODEV;
  1052. goto err_poweroff;
  1053. }
  1054. err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
  1055. anx78xx_hpd_threaded_handler,
  1056. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  1057. "anx78xx-hpd", anx78xx);
  1058. if (err) {
  1059. DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
  1060. err);
  1061. goto err_poweroff;
  1062. }
  1063. err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
  1064. anx78xx_intp_threaded_handler,
  1065. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  1066. "anx78xx-intp", anx78xx);
  1067. if (err) {
  1068. DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
  1069. goto err_poweroff;
  1070. }
  1071. anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
  1072. drm_bridge_add(&anx78xx->bridge);
  1073. /* If cable is pulled out, just poweroff and wait for HPD event */
  1074. if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
  1075. anx78xx_poweroff(anx78xx);
  1076. return 0;
  1077. err_poweroff:
  1078. anx78xx_poweroff(anx78xx);
  1079. err_unregister_i2c:
  1080. unregister_i2c_dummy_clients(anx78xx);
  1081. return err;
  1082. }
  1083. static int anx78xx_i2c_remove(struct i2c_client *client)
  1084. {
  1085. struct anx78xx *anx78xx = i2c_get_clientdata(client);
  1086. drm_bridge_remove(&anx78xx->bridge);
  1087. unregister_i2c_dummy_clients(anx78xx);
  1088. kfree(anx78xx->edid);
  1089. return 0;
  1090. }
  1091. static const struct i2c_device_id anx78xx_id[] = {
  1092. { "anx7814", 0 },
  1093. { /* sentinel */ }
  1094. };
  1095. MODULE_DEVICE_TABLE(i2c, anx78xx_id);
  1096. #if IS_ENABLED(CONFIG_OF)
  1097. static const struct of_device_id anx78xx_match_table[] = {
  1098. { .compatible = "analogix,anx7808", .data = anx7808_i2c_addresses },
  1099. { .compatible = "analogix,anx7812", .data = anx781x_i2c_addresses },
  1100. { .compatible = "analogix,anx7814", .data = anx781x_i2c_addresses },
  1101. { .compatible = "analogix,anx7818", .data = anx781x_i2c_addresses },
  1102. { /* sentinel */ },
  1103. };
  1104. MODULE_DEVICE_TABLE(of, anx78xx_match_table);
  1105. #endif
  1106. static struct i2c_driver anx78xx_driver = {
  1107. .driver = {
  1108. .name = "anx7814",
  1109. .of_match_table = of_match_ptr(anx78xx_match_table),
  1110. },
  1111. .probe = anx78xx_i2c_probe,
  1112. .remove = anx78xx_i2c_remove,
  1113. .id_table = anx78xx_id,
  1114. };
  1115. module_i2c_driver(anx78xx_driver);
  1116. MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
  1117. MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
  1118. MODULE_LICENSE("GPL v2");