atmel_hlcdc_crtc.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014 Traphandler
  4. * Copyright (C) 2014 Free Electrons
  5. *
  6. * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
  7. * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/mfd/atmel-hlcdc.h>
  11. #include <linux/pinctrl/consumer.h>
  12. #include <linux/pm.h>
  13. #include <linux/pm_runtime.h>
  14. #include <video/videomode.h>
  15. #include <drm/drm_atomic.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_crtc.h>
  18. #include <drm/drm_modeset_helper_vtables.h>
  19. #include <drm/drm_probe_helper.h>
  20. #include <drm/drm_vblank.h>
  21. #include "atmel_hlcdc_dc.h"
  22. /**
  23. * Atmel HLCDC CRTC state structure
  24. *
  25. * @base: base CRTC state
  26. * @output_mode: RGBXXX output mode
  27. */
  28. struct atmel_hlcdc_crtc_state {
  29. struct drm_crtc_state base;
  30. unsigned int output_mode;
  31. };
  32. static inline struct atmel_hlcdc_crtc_state *
  33. drm_crtc_state_to_atmel_hlcdc_crtc_state(struct drm_crtc_state *state)
  34. {
  35. return container_of(state, struct atmel_hlcdc_crtc_state, base);
  36. }
  37. /**
  38. * Atmel HLCDC CRTC structure
  39. *
  40. * @base: base DRM CRTC structure
  41. * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
  42. * @event: pointer to the current page flip event
  43. * @id: CRTC id (returned by drm_crtc_index)
  44. */
  45. struct atmel_hlcdc_crtc {
  46. struct drm_crtc base;
  47. struct atmel_hlcdc_dc *dc;
  48. struct drm_pending_vblank_event *event;
  49. int id;
  50. };
  51. static inline struct atmel_hlcdc_crtc *
  52. drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc)
  53. {
  54. return container_of(crtc, struct atmel_hlcdc_crtc, base);
  55. }
  56. static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
  57. {
  58. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  59. struct regmap *regmap = crtc->dc->hlcdc->regmap;
  60. struct drm_display_mode *adj = &c->state->adjusted_mode;
  61. struct atmel_hlcdc_crtc_state *state;
  62. unsigned long mode_rate;
  63. struct videomode vm;
  64. unsigned long prate;
  65. unsigned int mask = ATMEL_HLCDC_CLKDIV_MASK | ATMEL_HLCDC_CLKPOL;
  66. unsigned int cfg = 0;
  67. int div, ret;
  68. ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
  69. if (ret)
  70. return;
  71. vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
  72. vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
  73. vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start;
  74. vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay;
  75. vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end;
  76. vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start;
  77. regmap_write(regmap, ATMEL_HLCDC_CFG(1),
  78. (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16));
  79. regmap_write(regmap, ATMEL_HLCDC_CFG(2),
  80. (vm.vfront_porch - 1) | (vm.vback_porch << 16));
  81. regmap_write(regmap, ATMEL_HLCDC_CFG(3),
  82. (vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16));
  83. regmap_write(regmap, ATMEL_HLCDC_CFG(4),
  84. (adj->crtc_hdisplay - 1) |
  85. ((adj->crtc_vdisplay - 1) << 16));
  86. prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
  87. mode_rate = adj->crtc_clock * 1000;
  88. if (!crtc->dc->desc->fixed_clksrc) {
  89. prate *= 2;
  90. cfg |= ATMEL_HLCDC_CLKSEL;
  91. mask |= ATMEL_HLCDC_CLKSEL;
  92. }
  93. div = DIV_ROUND_UP(prate, mode_rate);
  94. if (div < 2) {
  95. div = 2;
  96. } else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) {
  97. /* The divider ended up too big, try a lower base rate. */
  98. cfg &= ~ATMEL_HLCDC_CLKSEL;
  99. prate /= 2;
  100. div = DIV_ROUND_UP(prate, mode_rate);
  101. if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK)
  102. div = ATMEL_HLCDC_CLKDIV_MASK;
  103. } else {
  104. int div_low = prate / mode_rate;
  105. if (div_low >= 2 &&
  106. (10 * (prate / div_low - mode_rate) <
  107. (mode_rate - prate / div)))
  108. /*
  109. * At least 10 times better when using a higher
  110. * frequency than requested, instead of a lower.
  111. * So, go with that.
  112. */
  113. div = div_low;
  114. }
  115. cfg |= ATMEL_HLCDC_CLKDIV(div);
  116. regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), mask, cfg);
  117. state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state);
  118. cfg = state->output_mode << 8;
  119. if (adj->flags & DRM_MODE_FLAG_NVSYNC)
  120. cfg |= ATMEL_HLCDC_VSPOL;
  121. if (adj->flags & DRM_MODE_FLAG_NHSYNC)
  122. cfg |= ATMEL_HLCDC_HSPOL;
  123. regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
  124. ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL |
  125. ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE |
  126. ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY |
  127. ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |
  128. ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK,
  129. cfg);
  130. clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
  131. }
  132. static enum drm_mode_status
  133. atmel_hlcdc_crtc_mode_valid(struct drm_crtc *c,
  134. const struct drm_display_mode *mode)
  135. {
  136. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  137. return atmel_hlcdc_dc_mode_valid(crtc->dc, mode);
  138. }
  139. static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c,
  140. struct drm_crtc_state *old_state)
  141. {
  142. struct drm_device *dev = c->dev;
  143. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  144. struct regmap *regmap = crtc->dc->hlcdc->regmap;
  145. unsigned int status;
  146. drm_crtc_vblank_off(c);
  147. pm_runtime_get_sync(dev->dev);
  148. regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
  149. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  150. (status & ATMEL_HLCDC_DISP))
  151. cpu_relax();
  152. regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
  153. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  154. (status & ATMEL_HLCDC_SYNC))
  155. cpu_relax();
  156. regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
  157. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  158. (status & ATMEL_HLCDC_PIXEL_CLK))
  159. cpu_relax();
  160. clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
  161. pinctrl_pm_select_sleep_state(dev->dev);
  162. pm_runtime_allow(dev->dev);
  163. pm_runtime_put_sync(dev->dev);
  164. }
  165. static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c,
  166. struct drm_crtc_state *old_state)
  167. {
  168. struct drm_device *dev = c->dev;
  169. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  170. struct regmap *regmap = crtc->dc->hlcdc->regmap;
  171. unsigned int status;
  172. pm_runtime_get_sync(dev->dev);
  173. pm_runtime_forbid(dev->dev);
  174. pinctrl_pm_select_default_state(dev->dev);
  175. clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
  176. regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
  177. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  178. !(status & ATMEL_HLCDC_PIXEL_CLK))
  179. cpu_relax();
  180. regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
  181. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  182. !(status & ATMEL_HLCDC_SYNC))
  183. cpu_relax();
  184. regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
  185. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  186. !(status & ATMEL_HLCDC_DISP))
  187. cpu_relax();
  188. pm_runtime_put_sync(dev->dev);
  189. drm_crtc_vblank_on(c);
  190. }
  191. #define ATMEL_HLCDC_RGB444_OUTPUT BIT(0)
  192. #define ATMEL_HLCDC_RGB565_OUTPUT BIT(1)
  193. #define ATMEL_HLCDC_RGB666_OUTPUT BIT(2)
  194. #define ATMEL_HLCDC_RGB888_OUTPUT BIT(3)
  195. #define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0)
  196. static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state)
  197. {
  198. struct drm_connector *connector = state->connector;
  199. struct drm_display_info *info = &connector->display_info;
  200. struct drm_encoder *encoder;
  201. unsigned int supported_fmts = 0;
  202. int j;
  203. encoder = state->best_encoder;
  204. if (!encoder)
  205. encoder = connector->encoder;
  206. switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) {
  207. case 0:
  208. break;
  209. case MEDIA_BUS_FMT_RGB444_1X12:
  210. return ATMEL_HLCDC_RGB444_OUTPUT;
  211. case MEDIA_BUS_FMT_RGB565_1X16:
  212. return ATMEL_HLCDC_RGB565_OUTPUT;
  213. case MEDIA_BUS_FMT_RGB666_1X18:
  214. return ATMEL_HLCDC_RGB666_OUTPUT;
  215. case MEDIA_BUS_FMT_RGB888_1X24:
  216. return ATMEL_HLCDC_RGB888_OUTPUT;
  217. default:
  218. return -EINVAL;
  219. }
  220. for (j = 0; j < info->num_bus_formats; j++) {
  221. switch (info->bus_formats[j]) {
  222. case MEDIA_BUS_FMT_RGB444_1X12:
  223. supported_fmts |= ATMEL_HLCDC_RGB444_OUTPUT;
  224. break;
  225. case MEDIA_BUS_FMT_RGB565_1X16:
  226. supported_fmts |= ATMEL_HLCDC_RGB565_OUTPUT;
  227. break;
  228. case MEDIA_BUS_FMT_RGB666_1X18:
  229. supported_fmts |= ATMEL_HLCDC_RGB666_OUTPUT;
  230. break;
  231. case MEDIA_BUS_FMT_RGB888_1X24:
  232. supported_fmts |= ATMEL_HLCDC_RGB888_OUTPUT;
  233. break;
  234. default:
  235. break;
  236. }
  237. }
  238. return supported_fmts;
  239. }
  240. static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state)
  241. {
  242. unsigned int output_fmts = ATMEL_HLCDC_OUTPUT_MODE_MASK;
  243. struct atmel_hlcdc_crtc_state *hstate;
  244. struct drm_connector_state *cstate;
  245. struct drm_connector *connector;
  246. struct atmel_hlcdc_crtc *crtc;
  247. int i;
  248. crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc);
  249. for_each_new_connector_in_state(state->state, connector, cstate, i) {
  250. unsigned int supported_fmts = 0;
  251. if (!cstate->crtc)
  252. continue;
  253. supported_fmts = atmel_hlcdc_connector_output_mode(cstate);
  254. if (crtc->dc->desc->conflicting_output_formats)
  255. output_fmts &= supported_fmts;
  256. else
  257. output_fmts |= supported_fmts;
  258. }
  259. if (!output_fmts)
  260. return -EINVAL;
  261. hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state);
  262. hstate->output_mode = fls(output_fmts) - 1;
  263. return 0;
  264. }
  265. static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c,
  266. struct drm_crtc_state *s)
  267. {
  268. int ret;
  269. ret = atmel_hlcdc_crtc_select_output_mode(s);
  270. if (ret)
  271. return ret;
  272. ret = atmel_hlcdc_plane_prepare_disc_area(s);
  273. if (ret)
  274. return ret;
  275. return atmel_hlcdc_plane_prepare_ahb_routing(s);
  276. }
  277. static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c,
  278. struct drm_crtc_state *old_s)
  279. {
  280. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  281. if (c->state->event) {
  282. c->state->event->pipe = drm_crtc_index(c);
  283. WARN_ON(drm_crtc_vblank_get(c) != 0);
  284. crtc->event = c->state->event;
  285. c->state->event = NULL;
  286. }
  287. }
  288. static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *crtc,
  289. struct drm_crtc_state *old_s)
  290. {
  291. /* TODO: write common plane control register if available */
  292. }
  293. static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
  294. .mode_valid = atmel_hlcdc_crtc_mode_valid,
  295. .mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
  296. .atomic_check = atmel_hlcdc_crtc_atomic_check,
  297. .atomic_begin = atmel_hlcdc_crtc_atomic_begin,
  298. .atomic_flush = atmel_hlcdc_crtc_atomic_flush,
  299. .atomic_enable = atmel_hlcdc_crtc_atomic_enable,
  300. .atomic_disable = atmel_hlcdc_crtc_atomic_disable,
  301. };
  302. static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c)
  303. {
  304. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  305. drm_crtc_cleanup(c);
  306. kfree(crtc);
  307. }
  308. static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc)
  309. {
  310. struct drm_device *dev = crtc->base.dev;
  311. unsigned long flags;
  312. spin_lock_irqsave(&dev->event_lock, flags);
  313. if (crtc->event) {
  314. drm_crtc_send_vblank_event(&crtc->base, crtc->event);
  315. drm_crtc_vblank_put(&crtc->base);
  316. crtc->event = NULL;
  317. }
  318. spin_unlock_irqrestore(&dev->event_lock, flags);
  319. }
  320. void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
  321. {
  322. drm_crtc_handle_vblank(c);
  323. atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
  324. }
  325. static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
  326. {
  327. struct atmel_hlcdc_crtc_state *state;
  328. if (crtc->state) {
  329. __drm_atomic_helper_crtc_destroy_state(crtc->state);
  330. state = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
  331. kfree(state);
  332. crtc->state = NULL;
  333. }
  334. state = kzalloc(sizeof(*state), GFP_KERNEL);
  335. if (state)
  336. __drm_atomic_helper_crtc_reset(crtc, &state->base);
  337. }
  338. static struct drm_crtc_state *
  339. atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc)
  340. {
  341. struct atmel_hlcdc_crtc_state *state, *cur;
  342. if (WARN_ON(!crtc->state))
  343. return NULL;
  344. state = kmalloc(sizeof(*state), GFP_KERNEL);
  345. if (!state)
  346. return NULL;
  347. __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
  348. cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
  349. state->output_mode = cur->output_mode;
  350. return &state->base;
  351. }
  352. static void atmel_hlcdc_crtc_destroy_state(struct drm_crtc *crtc,
  353. struct drm_crtc_state *s)
  354. {
  355. struct atmel_hlcdc_crtc_state *state;
  356. state = drm_crtc_state_to_atmel_hlcdc_crtc_state(s);
  357. __drm_atomic_helper_crtc_destroy_state(s);
  358. kfree(state);
  359. }
  360. static int atmel_hlcdc_crtc_enable_vblank(struct drm_crtc *c)
  361. {
  362. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  363. struct regmap *regmap = crtc->dc->hlcdc->regmap;
  364. /* Enable SOF (Start Of Frame) interrupt for vblank counting */
  365. regmap_write(regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
  366. return 0;
  367. }
  368. static void atmel_hlcdc_crtc_disable_vblank(struct drm_crtc *c)
  369. {
  370. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  371. struct regmap *regmap = crtc->dc->hlcdc->regmap;
  372. regmap_write(regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
  373. }
  374. static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = {
  375. .page_flip = drm_atomic_helper_page_flip,
  376. .set_config = drm_atomic_helper_set_config,
  377. .destroy = atmel_hlcdc_crtc_destroy,
  378. .reset = atmel_hlcdc_crtc_reset,
  379. .atomic_duplicate_state = atmel_hlcdc_crtc_duplicate_state,
  380. .atomic_destroy_state = atmel_hlcdc_crtc_destroy_state,
  381. .enable_vblank = atmel_hlcdc_crtc_enable_vblank,
  382. .disable_vblank = atmel_hlcdc_crtc_disable_vblank,
  383. .gamma_set = drm_atomic_helper_legacy_gamma_set,
  384. };
  385. int atmel_hlcdc_crtc_create(struct drm_device *dev)
  386. {
  387. struct atmel_hlcdc_plane *primary = NULL, *cursor = NULL;
  388. struct atmel_hlcdc_dc *dc = dev->dev_private;
  389. struct atmel_hlcdc_crtc *crtc;
  390. int ret;
  391. int i;
  392. crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
  393. if (!crtc)
  394. return -ENOMEM;
  395. crtc->dc = dc;
  396. for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
  397. if (!dc->layers[i])
  398. continue;
  399. switch (dc->layers[i]->desc->type) {
  400. case ATMEL_HLCDC_BASE_LAYER:
  401. primary = atmel_hlcdc_layer_to_plane(dc->layers[i]);
  402. break;
  403. case ATMEL_HLCDC_CURSOR_LAYER:
  404. cursor = atmel_hlcdc_layer_to_plane(dc->layers[i]);
  405. break;
  406. default:
  407. break;
  408. }
  409. }
  410. ret = drm_crtc_init_with_planes(dev, &crtc->base, &primary->base,
  411. &cursor->base, &atmel_hlcdc_crtc_funcs,
  412. NULL);
  413. if (ret < 0)
  414. goto fail;
  415. crtc->id = drm_crtc_index(&crtc->base);
  416. for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
  417. struct atmel_hlcdc_plane *overlay;
  418. if (dc->layers[i] &&
  419. dc->layers[i]->desc->type == ATMEL_HLCDC_OVERLAY_LAYER) {
  420. overlay = atmel_hlcdc_layer_to_plane(dc->layers[i]);
  421. overlay->base.possible_crtcs = 1 << crtc->id;
  422. }
  423. }
  424. drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
  425. drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE);
  426. drm_crtc_enable_color_mgmt(&crtc->base, 0, false,
  427. ATMEL_HLCDC_CLUT_SIZE);
  428. dc->crtc = &crtc->base;
  429. return 0;
  430. fail:
  431. atmel_hlcdc_crtc_destroy(&crtc->base);
  432. return ret;
  433. }